From patchwork Tue Oct 4 22:47:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Thaler X-Patchwork-Id: 12998749 X-Patchwork-Delegate: bpf@iogearbox.net Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E86E4C433FE for ; Tue, 4 Oct 2022 22:47:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229967AbiJDWrx (ORCPT ); Tue, 4 Oct 2022 18:47:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229531AbiJDWrw (ORCPT ); Tue, 4 Oct 2022 18:47:52 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9588B6EF04 for ; Tue, 4 Oct 2022 15:47:50 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id a23so6161799pgi.10 for ; Tue, 04 Oct 2022 15:47:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=s9xNB+9pkjsuEgXzNEYq8ChwptKRSqWxHSgvfEMrQ0s=; b=Ho8yNfeynv/wiVDSv7AoCIX8gQxEEQrLKc6lUzcpM5Vc3EYkNgiG5XIQM+Jjr7dMtM t1eR573I1wdnFC+iHyfLX9XwQJCHcKMM/Tgdm6jbwrBEo4kLXISxMmCup7oqyO7Nwf7B zduBveYq6foCkSSkA9f3NxmIHe1KGMX3UQDVK90TfxdF1peYK9nvK8otudr5opLiFJo7 lOgA8LsIb4sPgnJdy8sDq0rap/vfMqDm88KyjpT11atKtWmJixW85ZD9HJ+/vGa5j6GI J73zh0FHK4qMV3a8fPZsr3kuPhqhwpP0YApgkwYxCTOuShVyqt1TxL2CkhPF7rvTGht5 zX1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=s9xNB+9pkjsuEgXzNEYq8ChwptKRSqWxHSgvfEMrQ0s=; b=2qB2y+gS9qKJhFDZL1w8pX/+gsu2OGhkY6KJp35N3FP6sbL9eMpRj1HZHFt4FyXMui O0jpuFHqvwzyGBKIE8GrOIzV8akK1I53rH0tj6HCE+EeyA1hrd6JuSgdqyyb2sRDuCv/ J2XkLtNfXbEyOPNsIjhQLINp5KujjG7CFqWOqPfvPwrXwY95t5subUKponvPpAsa0ULU YfaNisU9fnrxLr7ZCucgKVRbINwMOecEemcJQZVQ83OCFyv18XSSFEzXvqqxzSwUOkb/ q8AfaKs2MQCl/whgPvx32eW7QnsR5ufSdG1rwIcVTU3eDR3IsA+puNByGkjTFqapk1wR eIew== X-Gm-Message-State: ACrzQf3jZ85P/ADrlYhfY/rNeoTOODgIbfjBTvkbX28gFqUou2pAYWCz p1NIy1LOS1/W5qj1KZzRFnYD7Qs8280= X-Google-Smtp-Source: AMsMyM4NzKfKDwmjRkNs0OHMGzid6oEN7VbwUVKDuwYIAxouBeZTqPfnIlgXPvm8yTPakI4JznE7/g== X-Received: by 2002:a05:6a00:a04:b0:534:d8a6:40ce with SMTP id p4-20020a056a000a0400b00534d8a640cemr30001571pfh.15.1664923669153; Tue, 04 Oct 2022 15:47:49 -0700 (PDT) Received: from mariner-vm.. ([131.107.174.139]) by smtp.gmail.com with ESMTPSA id c13-20020a170902d48d00b0016c0eb202a5sm9487369plg.225.2022.10.04.15.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 15:47:48 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 1/9] bpf, docs: Add note about type convention Date: Tue, 4 Oct 2022 22:47:37 +0000 Message-Id: <20221004224745.1430-1-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Add note about type convention Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 4997d2088..6847a4cbf 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -7,6 +7,11 @@ eBPF Instruction Set Specification, v1.0 This document specifies version 1.0 of the eBPF instruction set. +Documentation conventions +========================= + +For brevity, this document uses the type notion "u64", "u32", etc. +to mean an unsigned integer whose width is the specified number of bits. Registers and calling convention ================================ @@ -116,6 +121,8 @@ BPF_END 0xd0 byte swap operations (see `Byte swap instructions`_ below) dst_reg = (u32) dst_reg + (u32) src_reg; +where '(u32)' indicates truncation to 32 bits. + ``BPF_ADD | BPF_X | BPF_ALU64`` means:: dst_reg = dst_reg + src_reg From patchwork Tue Oct 4 22:47:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Thaler X-Patchwork-Id: 12998750 X-Patchwork-Delegate: bpf@iogearbox.net Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABDE5C433F5 for ; Tue, 4 Oct 2022 22:47:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229531AbiJDWry (ORCPT ); Tue, 4 Oct 2022 18:47:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230037AbiJDWrx (ORCPT ); Tue, 4 Oct 2022 18:47:53 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 898366CF78 for ; Tue, 4 Oct 2022 15:47:51 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id w2so14378268pfb.0 for ; Tue, 04 Oct 2022 15:47:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=rCDmQ9xrAmjZGrgEFa9vY4JR2yCT6Jw9ahBiSCvLJ/g=; b=nk0bbYG7LEC2zzhSCCt9z6ZmFvvnVVwoKn3ejpjiNwNFqeEJDB+ObBFHb8u6fXiS6p VcBd4XDhdeDvslTMYYXTtcBvLAElEexkTciMIkcFkQstCo4OOIkEOL+W0ZCvVlt89/R8 iOfc8SJ2GSVyUwc9dW70ayL9u5nsaCfmF0M2p9vDS6uHVpYul8bm86HZ/P6RrqUBx7PE 5OHCtrpnxRJcILpR07CMt13TbgUnPO8+7xoutlstM8QFUXUS+omKNYMqPjwtUkRaH0xh heV95TubwbHyFgZfhSIaURleUi20iFVTbgttRbi10B8PC26vjzIxcAxO2Kefd9n6QdIj do9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=rCDmQ9xrAmjZGrgEFa9vY4JR2yCT6Jw9ahBiSCvLJ/g=; b=r7x4N58sR6WlmvJaGpeHWWkZvrUJuazqc5WS5l/RXYoRHU5Kc8/tbV6fd48wSstmYn 4t0ZAQ5KLLVShVLAFOb92XaTaWfOwOdliv7OW2yIvmNZU+Wm/0N9PWwX26FppWaTWqkN F/9++n2zDoo8cKGJ6ZMs4OxnIGLWdewDZ7B9nylVV9SxghkmJD7o96Gzaz1zXrI8Mkfj 784kXwV+HthOzCYC38zqwZ88g71HD1AE1ARza/uMVtlb6u0GFq/zpNvzOWlF6a3jPqAl wCSxgFiBJtxJV/v2imlhol1jq+rCq2ZBeTJyARboV+DuDVLig29t7KaiS61xRdUJOs25 TRZA== X-Gm-Message-State: ACrzQf2oVf2J02QcoGuAh0RBITSNWVKgN9sL8usO+5TRwkAZ1zbf752y MPI9WUjbCwVRnY3sIqY6lXcCv6bu/tQ= X-Google-Smtp-Source: AMsMyM76Y95ktXGnRIjZMvjJGT+JosVCzgeoBahSGZrEQnGK903BXez6IhUjKehGAXozevdt2eyKyA== X-Received: by 2002:a05:6a00:3392:b0:547:f861:1fc9 with SMTP id cm18-20020a056a00339200b00547f8611fc9mr29792961pfb.17.1664923670003; Tue, 04 Oct 2022 15:47:50 -0700 (PDT) Received: from mariner-vm.. ([131.107.174.139]) by smtp.gmail.com with ESMTPSA id c13-20020a170902d48d00b0016c0eb202a5sm9487369plg.225.2022.10.04.15.47.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 15:47:49 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 2/9] bpf, docs: Fix modulo zero, division by zero, overflow, and underflow Date: Tue, 4 Oct 2022 22:47:38 +0000 Message-Id: <20221004224745.1430-2-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 In-Reply-To: <20221004224745.1430-1-dthaler1968@googlemail.com> References: <20221004224745.1430-1-dthaler1968@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Fix modulo zero, division by zero, overflow, and underflow. Also clarify how a negative immediate value is ued in unsigned division Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 6847a4cbf..3a64d4b49 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -104,19 +104,26 @@ code value description BPF_ADD 0x00 dst += src BPF_SUB 0x10 dst -= src BPF_MUL 0x20 dst \*= src -BPF_DIV 0x30 dst /= src +BPF_DIV 0x30 dst = (src != 0) ? (dst / src) : 0 BPF_OR 0x40 dst \|= src BPF_AND 0x50 dst &= src BPF_LSH 0x60 dst <<= src BPF_RSH 0x70 dst >>= src BPF_NEG 0x80 dst = ~src -BPF_MOD 0x90 dst %= src +BPF_MOD 0x90 dst = (src != 0) ? (dst % src) : dst BPF_XOR 0xa0 dst ^= src BPF_MOV 0xb0 dst = src BPF_ARSH 0xc0 sign extending shift right BPF_END 0xd0 byte swap operations (see `Byte swap instructions`_ below) ======== ===== ========================================================== +Underflow and overflow are allowed during arithmetic operations, +meaning the 64-bit or 32-bit value will wrap. If +eBPF program execution would result in division by zero, +the destination register is instead set to zero. +If execution would result in modulo by zero, +the destination register is instead left unchanged. + ``BPF_ADD | BPF_X | BPF_ALU`` means:: dst_reg = (u32) dst_reg + (u32) src_reg; @@ -135,6 +142,10 @@ where '(u32)' indicates truncation to 32 bits. src_reg = src_reg ^ imm32 +Also note that the division and modulo operations are unsigned, +where 'imm' is first sign extended to 64 bits and then converted +to an unsigned 64-bit value. There are no instructions for +signed division or modulo. Byte swap instructions ~~~~~~~~~~~~~~~~~~~~~~ From patchwork Tue Oct 4 22:47:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Thaler X-Patchwork-Id: 12998751 X-Patchwork-Delegate: bpf@iogearbox.net Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C4A0C433FE for ; Tue, 4 Oct 2022 22:47:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230189AbiJDWrz (ORCPT ); Tue, 4 Oct 2022 18:47:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230041AbiJDWrx (ORCPT ); Tue, 4 Oct 2022 18:47:53 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 370516D543 for ; Tue, 4 Oct 2022 15:47:52 -0700 (PDT) Received: by mail-pg1-x52f.google.com with SMTP id c7so13849579pgt.11 for ; Tue, 04 Oct 2022 15:47:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=jcX2mJ3fFojEo2hfaxGiaRqzWuPlP1L0U3++56+JvDo=; b=D//wAtQBjlQMiDgnfHg/NO3Od/RZ0+P8XSy4F61jts5Libcp3uKN21QTA2858vil1x dGX8y9fKLPsIycuRWR1f5Hj62qYVJCAn5F7CG9zzoFMaWIXB/MVpugyMzP8oscOmrk/B t2zHqFbuU2h0rx41Oi4S1ip8tmZab03KCR1RZy02vGRK8zTf3/zRuwOfNIplIPZvkAXN 41WI6rJJLniqkZHyErr6cZ4OyEXJ7z+rP//uCvLAhaXiuJ83lvvB4YmsatByYmDcQDjb k31PM3BTb7wzhlknhVXkStbkWQKD1A8Kukdg2+4pHnX5jFFt51aG14UXtk5T6KsImh8C lzyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=jcX2mJ3fFojEo2hfaxGiaRqzWuPlP1L0U3++56+JvDo=; b=g3nUJU3mANUDn4r2hRt/ZNEKKLD5poJnzYLSAw7CssLxT2s5QzAw7cWpgc5C6wy5Wy O9TiSx1bcm58MDMHdH9DkOYRUHqb4FRZXOFFTIcD6Hbid783nVzj/IhxVdN64KElm/uN qubcE6WuBhLR+pn6pFFvKRTilAEE3TnM9J/CDrUSHT9SUhmWzJt106w+Gih+ugnRyhoY fEXUtoD+Bo6Q2FX1oYBuJ0Lpjn1H1uP4bNSjkY0I2C2/eR/omFf4peDgJefY2ZJyikqU J6AEkt5fdc/JM/8gLc0GfN1C1H7jb0SVqv+ytvAhC/RIbwT/zICDqp8NZl2x3SlQx7ra eQzQ== X-Gm-Message-State: ACrzQf0jz5UZEfvjQjQLyqkhTTUae/XDI+K8FQpD628w9f59riaRcZF1 2uJB6112y7GJ24lb8f1BVCiHk6Olw0c= X-Google-Smtp-Source: AMsMyM5slwPyWrR25T7+GVKnEaZUdOnoIjRPY/4FITs5w2Q9VZy1jpzdrNUlIyEzSPKC8NgFl45BBg== X-Received: by 2002:a05:6a00:8d0:b0:53b:2cbd:fab6 with SMTP id s16-20020a056a0008d000b0053b2cbdfab6mr29733774pfu.3.1664923671138; Tue, 04 Oct 2022 15:47:51 -0700 (PDT) Received: from mariner-vm.. ([131.107.174.139]) by smtp.gmail.com with ESMTPSA id c13-20020a170902d48d00b0016c0eb202a5sm9487369plg.225.2022.10.04.15.47.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 15:47:50 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 3/9] bpf, docs: Use consistent names for the same field Date: Tue, 4 Oct 2022 22:47:39 +0000 Message-Id: <20221004224745.1430-3-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 In-Reply-To: <20221004224745.1430-1-dthaler1968@googlemail.com> References: <20221004224745.1430-1-dthaler1968@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Use consistent names for the same field Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 107 ++++++++++++++++++-------- 1 file changed, 76 insertions(+), 31 deletions(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 3a64d4b49..29b599c70 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -35,20 +35,59 @@ Instruction encoding eBPF has two instruction encodings: * the basic instruction encoding, which uses 64 bits to encode an instruction -* the wide instruction encoding, which appends a second 64-bit immediate value - (imm64) after the basic instruction for a total of 128 bits. +* the wide instruction encoding, which appends a second 64-bit immediate (i.e., + constant) value after the basic instruction for a total of 128 bits. -The basic instruction encoding looks as follows: +The basic instruction encoding is as follows, where MSB and LSB mean the most significant +bits and least significant bits, respectively: ============= ======= =============== ==================== ============ 32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB) ============= ======= =============== ==================== ============ -immediate offset source register destination register opcode +imm offset src dst opcode ============= ======= =============== ==================== ============ +imm + signed integer immediate value + +offset + signed integer offset used with pointer arithmetic + +src + the source register number (0-10), except where otherwise specified + (`64-bit immediate instructions`_ reuse this field for other purposes) + +dst + destination register number (0-10) + +opcode + operation to perform + Note that most instructions do not use all of the fields. Unused fields shall be cleared to zero. +As discussed below in `64-bit immediate instructions`_, a 64-bit immediate +instruction uses a 64-bit immediate value that is constructed as follows. +The 64 bits following the basic instruction contain a pseudo instruction +using the same format but with opcode, dst, src, and offset all set to zero, +and imm containing the high 32 bits of the immediate value. + +================= ================== +64 bits (MSB) 64 bits (LSB) +================= ================== +basic instruction pseudo instruction +================= ================== + +Thus the 64-bit immediate value is constructed as follows: + + imm64 = imm + (next_imm << 32) + +where 'next_imm' refers to the imm value of the pseudo instruction +following the basic instruction. + +In the remainder of this document 'src' and 'dst' refer to the values of the source +and destination registers, respectively, rather than the register number. + Instruction classes ------------------- @@ -76,20 +115,24 @@ For arithmetic and jump instructions (``BPF_ALU``, ``BPF_ALU64``, ``BPF_JMP`` an ============== ====== ================= 4 bits (MSB) 1 bit 3 bits (LSB) ============== ====== ================= -operation code source instruction class +code source instruction class ============== ====== ================= -The 4th bit encodes the source operand: +code + the operation code, whose meaning varies by instruction class - ====== ===== ======================================== - source value description - ====== ===== ======================================== - BPF_K 0x00 use 32-bit immediate as source operand - BPF_X 0x08 use 'src_reg' register as source operand - ====== ===== ======================================== +source + the source operand location, which unless otherwise specified is one of: -The four MSB bits store the operation code. + ====== ===== ========================================== + source value description + ====== ===== ========================================== + BPF_K 0x00 use 32-bit 'imm' value as source operand + BPF_X 0x08 use 'src' register value as source operand + ====== ===== ========================================== +instruction class + the instruction class (see `Instruction classes`_) Arithmetic instructions ----------------------- @@ -117,6 +160,8 @@ BPF_ARSH 0xc0 sign extending shift right BPF_END 0xd0 byte swap operations (see `Byte swap instructions`_ below) ======== ===== ========================================================== +where 'src' is the source operand value. + Underflow and overflow are allowed during arithmetic operations, meaning the 64-bit or 32-bit value will wrap. If eBPF program execution would result in division by zero, @@ -126,21 +171,21 @@ the destination register is instead left unchanged. ``BPF_ADD | BPF_X | BPF_ALU`` means:: - dst_reg = (u32) dst_reg + (u32) src_reg; + dst = (u32) (dst + src) where '(u32)' indicates truncation to 32 bits. ``BPF_ADD | BPF_X | BPF_ALU64`` means:: - dst_reg = dst_reg + src_reg + dst = dst + src ``BPF_XOR | BPF_K | BPF_ALU`` means:: - src_reg = (u32) src_reg ^ (u32) imm32 + src = (u32) src ^ (u32) imm ``BPF_XOR | BPF_K | BPF_ALU64`` means:: - src_reg = src_reg ^ imm32 + src = src ^ imm Also note that the division and modulo operations are unsigned, where 'imm' is first sign extended to 64 bits and then converted @@ -173,11 +218,11 @@ Examples: ``BPF_ALU | BPF_TO_LE | BPF_END`` with imm = 16 means:: - dst_reg = htole16(dst_reg) + dst = htole16(dst) ``BPF_ALU | BPF_TO_BE | BPF_END`` with imm = 64 means:: - dst_reg = htobe64(dst_reg) + dst = htobe64(dst) Jump instructions ----------------- @@ -252,15 +297,15 @@ instructions that transfer data between a register and memory. ``BPF_MEM | | BPF_STX`` means:: - *(size *) (dst_reg + off) = src_reg + *(size *) (dst + offset) = src_reg ``BPF_MEM | | BPF_ST`` means:: - *(size *) (dst_reg + off) = imm32 + *(size *) (dst + offset) = imm32 ``BPF_MEM | | BPF_LDX`` means:: - dst_reg = *(size *) (src_reg + off) + dst = *(size *) (src + offset) Where size is one of: ``BPF_B``, ``BPF_H``, ``BPF_W``, or ``BPF_DW``. @@ -294,11 +339,11 @@ BPF_XOR 0xa0 atomic xor ``BPF_ATOMIC | BPF_W | BPF_STX`` with 'imm' = BPF_ADD means:: - *(u32 *)(dst_reg + off16) += src_reg + *(u32 *)(dst + offset) += src ``BPF_ATOMIC | BPF_DW | BPF_STX`` with 'imm' = BPF ADD means:: - *(u64 *)(dst_reg + off16) += src_reg + *(u64 *)(dst + offset) += src In addition to the simple atomic operations, there also is a modifier and two complex atomic operations: @@ -313,16 +358,16 @@ BPF_CMPXCHG 0xf0 | BPF_FETCH atomic compare and exchange The ``BPF_FETCH`` modifier is optional for simple atomic operations, and always set for the complex atomic operations. If the ``BPF_FETCH`` flag -is set, then the operation also overwrites ``src_reg`` with the value that +is set, then the operation also overwrites ``src`` with the value that was in memory before it was modified. -The ``BPF_XCHG`` operation atomically exchanges ``src_reg`` with the value -addressed by ``dst_reg + off``. +The ``BPF_XCHG`` operation atomically exchanges ``src`` with the value +addressed by ``dst + offset``. The ``BPF_CMPXCHG`` operation atomically compares the value addressed by -``dst_reg + off`` with ``R0``. If they match, the value addressed by -``dst_reg + off`` is replaced with ``src_reg``. In either case, the -value that was at ``dst_reg + off`` before the operation is zero-extended +``dst + offset`` with ``R0``. If they match, the value addressed by +``dst + offset`` is replaced with ``src``. In either case, the +value that was at ``dst + offset`` before the operation is zero-extended and loaded back to ``R0``. 64-bit immediate instructions @@ -335,7 +380,7 @@ There is currently only one such instruction. ``BPF_LD | BPF_DW | BPF_IMM`` means:: - dst_reg = imm64 + dst = imm64 Legacy BPF Packet access instructions From patchwork Tue Oct 4 22:47:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Thaler X-Patchwork-Id: 12998752 X-Patchwork-Delegate: bpf@iogearbox.net Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65562C4332F for ; Tue, 4 Oct 2022 22:47:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230282AbiJDWr5 (ORCPT ); Tue, 4 Oct 2022 18:47:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230043AbiJDWrx (ORCPT ); Tue, 4 Oct 2022 18:47:53 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F10FF6E88E for ; Tue, 4 Oct 2022 15:47:52 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id gf8so11545086pjb.5 for ; Tue, 04 Oct 2022 15:47:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=M0k3UitIuZs8QbREBS2h3Pc+EVFq/RHeV38kSddPEQQ=; b=NMfBKlnwsWwXQGP5WhQI/VFLnw0jJ8sENJXELWGqZuwJu4lbWmZXbshzam+ZYYuyQB U88T7SDsEDdP6tLOIDswmyRmGhI3IKOytgHi+Rf3UN64iBoo6togvHpwApRvGU3xjvji c5YKqIMDl5+uIbR4NO7PD23SfSqsr5n/TYMKuq5AK4AHGryhTBKf1SXr66taAJKTb6HF y3czNb3Tl7DKQN8sexHq4CE1Whu4ccKUz8UTRtife7rNjMH+VnTN6c0WLVXIj5Vp9dhL h24FXrnnr+GVM1z9YGDDwVowGmBN3V2YrsARZzLspXQyBzk5ch/mZayre868H5RGGvXF 5vnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=M0k3UitIuZs8QbREBS2h3Pc+EVFq/RHeV38kSddPEQQ=; b=qDcAvUfLd5aUmjU8ex4MfSEjcB57VZW9mqMuVrSfVmZnUSbAiwWAw0QIdMjIf13Kxm UslwgJoIhbsQiLGIEoJnPHCJwaY/l/jC7TCpFwsgiUBQ+yeHpGj0+VYnJElCGjHvEC4Y ZAMbzztfyMndMcd7F+6qO72i1BdKljiLPG1Bb+oyXOIbkn+jBel7ylTSj21+GfHOOR1j IqJy33vBngeAhGFk6ZeZ9l97+XY6oYYvyH+iIY0y0iDQAIyXweHf93FiE9rQ6B8wceHh BVkz/t9WMeTA9MsEK5e8g5wys6SNv0hDCpUDbcOOB3l4JI3F+GxYYGlIAdxoyLQt4MEl M7FQ== X-Gm-Message-State: ACrzQf1B5q8etGionA4URvFLA62xd0FrM8pk+kJArOgfVySZFasGlhGl WM5HO7FsXEoaszpaKTOHSPVXXuLxw8g= X-Google-Smtp-Source: AMsMyM7cfTOScEbOHe6ORrAhJVsARAJWE9KzemXNaPAW/F4TCiKCx0SE3UZjfcrTUXUS7LBMEajvdw== X-Received: by 2002:a17:902:7009:b0:178:b9c9:979f with SMTP id y9-20020a170902700900b00178b9c9979fmr28005821plk.39.1664923672098; Tue, 04 Oct 2022 15:47:52 -0700 (PDT) Received: from mariner-vm.. ([131.107.174.139]) by smtp.gmail.com with ESMTPSA id c13-20020a170902d48d00b0016c0eb202a5sm9487369plg.225.2022.10.04.15.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 15:47:51 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 4/9] bpf, docs: Explain helper functions Date: Tue, 4 Oct 2022 22:47:40 +0000 Message-Id: <20221004224745.1430-4-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 In-Reply-To: <20221004224745.1430-1-dthaler1968@googlemail.com> References: <20221004224745.1430-1-dthaler1968@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Explain helper functions. Kernel functions and bpf to bpf calls are covered in a later commit in this set ("Add extended call instructions"). Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 29b599c70..f9e56d9d5 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -242,7 +242,7 @@ BPF_JSET 0x40 PC += off if dst & src BPF_JNE 0x50 PC += off if dst != src BPF_JSGT 0x60 PC += off if dst > src signed BPF_JSGE 0x70 PC += off if dst >= src signed -BPF_CALL 0x80 function call +BPF_CALL 0x80 function call see `Helper functions`_ BPF_EXIT 0x90 function / program return BPF_JMP only BPF_JLT 0xa0 PC += off if dst < src unsigned BPF_JLE 0xb0 PC += off if dst <= src unsigned @@ -253,6 +253,22 @@ BPF_JSLE 0xd0 PC += off if dst <= src signed The eBPF program needs to store the return value into register R0 before doing a BPF_EXIT. +Helper functions +~~~~~~~~~~~~~~~~ +Helper functions are a concept whereby BPF programs can call into a +set of function calls exposed by the eBPF runtime. Each helper +function is identified by an integer used in a ``BPF_CALL`` instruction. +The available helper functions may differ for each eBPF program type. + +Conceptually, each helper function is implemented with a commonly shared function +signature defined as: + + u64 function(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) + +In actuality, each helper function is defined as taking between 0 and 5 arguments, +with the remaining registers being ignored. The definition of a helper function +is responsible for specifying the type (e.g., integer, pointer, etc.) of the value returned, +the number of arguments, and the type of each argument. Load and store instructions =========================== From patchwork Tue Oct 4 22:47:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Thaler X-Patchwork-Id: 12998753 X-Patchwork-Delegate: bpf@iogearbox.net Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31ED1C433F5 for ; Tue, 4 Oct 2022 22:48:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230122AbiJDWr6 (ORCPT ); Tue, 4 Oct 2022 18:47:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230256AbiJDWr4 (ORCPT ); Tue, 4 Oct 2022 18:47:56 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 952066E2D7 for ; Tue, 4 Oct 2022 15:47:54 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id d24so13903485pls.4 for ; Tue, 04 Oct 2022 15:47:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=zEN3tJpO8t5ZqWwyNkIZ+G7P4+jm/GP+61Xy5HR+PNs=; b=QFVeWuJqKXKFre5KI+N33U+Qv4fstjllxZpe7j8kOPSwdfEaDQ9k1aHO+EoGV8sLcA VT2yfMGuyPhZMfw/lHd/moJOozICzHcmU7MfYYRQI+QpYAtfZuhQJuHsUowS6ru7YRu4 S6suI39KphtGYFMq8tjpLioed2uLN9E8wOx5IG0DesgCpRzM966zaMtTBiYLMdrT6wkO 2+lt6si3cyoSuI93TImUwFSis9Iqy1JPWoyWzz1vhSkW10HsZzdCKHaWRHRHtT5xvZeo AZ/GRr1HxNfe6i1SeVR8x371KVYT6EedflyY6ki4zmBqNRcKsubkfuYM8k/EuoLkL6pk lReA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=zEN3tJpO8t5ZqWwyNkIZ+G7P4+jm/GP+61Xy5HR+PNs=; b=XO4fog4yGi33x1qnC35bvIIwsvzHTiYv7zq1FDNeRflOgr5pExPLlQNEJDxG1s9HVH MPzJ3ltY5IPUkSr9DWpyG+7ZGLKqruFL6LG3DP5USYn7WOaorAdNT9Xqd/1Q/6dmKR5O NmIY073jBGlwr9UwqhNkutO3c6jfWOEynH2htHSk8K8sTZzYY4zzzpJt5l64DTtoOoWI Tojvbr323a850gjGL+ydkEBC7s2s8Ai1Jv2oH2P4jNxAsutFeyGkUOEiJSValzMtLJJK zW3xLRHKahNdJAr/yP94Zg4dM+dYqkhVVmY72+TI+q1d21sj9FKo9BWt+nh+E4zL5CRx IxhQ== X-Gm-Message-State: ACrzQf1r941tZvgP615gAOvhhVML9fSOQxNk7BFx30W4hPw+6u297BHR 6oMYT94Aea36FWgjZDDkZtrWRY9ngXI= X-Google-Smtp-Source: AMsMyM5REV+Ay/iev+8aN+7lMkdJy64zovKcymzQ5pM5d0lWOLfuFJkHcuVl8JhmXWLZ3zUYcbgsNg== X-Received: by 2002:a17:902:9a8b:b0:17a:455:d967 with SMTP id w11-20020a1709029a8b00b0017a0455d967mr28354291plp.52.1664923673226; Tue, 04 Oct 2022 15:47:53 -0700 (PDT) Received: from mariner-vm.. ([131.107.174.139]) by smtp.gmail.com with ESMTPSA id c13-20020a170902d48d00b0016c0eb202a5sm9487369plg.225.2022.10.04.15.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 15:47:52 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 5/9] bpf, docs: Add appendix of all opcodes in order Date: Tue, 4 Oct 2022 22:47:41 +0000 Message-Id: <20221004224745.1430-5-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 In-Reply-To: <20221004224745.1430-1-dthaler1968@googlemail.com> References: <20221004224745.1430-1-dthaler1968@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Add appendix of all opcodes in order. A couple of reviewers explicitly asked for this and have indicated it was the most useful addition in the doc. Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 200 +++++++++++++++++++++++++- 1 file changed, 199 insertions(+), 1 deletion(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index f9e56d9d5..7c1e245df 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -11,7 +11,8 @@ Documentation conventions ========================= For brevity, this document uses the type notion "u64", "u32", etc. -to mean an unsigned integer whose width is the specified number of bits. +to mean an unsigned integer whose width is the specified number of bits, +and "s32", etc. to mean a signed integer of the specified number of bits. Registers and calling convention ================================ @@ -405,3 +406,200 @@ Legacy BPF Packet access instructions eBPF previously introduced special instructions for access to packet data that were carried over from classic BPF. However, these instructions are deprecated and should no longer be used. + +Appendix +======== + +For reference, the following table lists opcodes in order by value. + +====== === ==== =================================================== ======================================== +opcode src imm description reference +====== === ==== =================================================== ======================================== +0x00 0x0 any (additional immediate value) `64-bit immediate instructions`_ +0x04 0x0 any dst = (u32)(dst + imm) `Arithmetic instructions`_ +0x05 0x0 0x00 goto +offset `Jump instructions`_ +0x07 0x0 any dst += imm `Arithmetic instructions`_ +0x0c any 0x00 dst = (u32)(dst + src) `Arithmetic instructions`_ +0x0f any 0x00 dst += src `Arithmetic instructions`_ +0x14 0x0 any dst = (u32)(dst - imm) `Arithmetic instructions`_ +0x15 0x0 any if dst == imm goto +offset `Jump instructions`_ +0x16 0x0 any if (u32)dst == imm goto +offset `Jump instructions`_ +0x17 0x0 any dst -= imm `Arithmetic instructions`_ +0x18 0x0 any dst = imm64 `64-bit immediate instructions`_ +0x1c any 0x00 dst = (u32)(dst - src) `Arithmetic instructions`_ +0x1d any 0x00 if dst == src goto +offset `Jump instructions`_ +0x1e any 0x00 if (u32)dst == (u32)src goto +offset `Jump instructions`_ +0x1f any 0x00 dst -= src `Arithmetic instructions`_ +0x20 any any (deprecated, implementation-specific) `Legacy BPF Packet access instructions`_ +0x24 0x0 any dst = (u32)(dst \* imm) `Arithmetic instructions`_ +0x25 0x0 any if dst > imm goto +offset `Jump instructions`_ +0x26 0x0 any if (u32)dst > imm goto +offset `Jump instructions`_ +0x27 0x0 any dst \*= imm `Arithmetic instructions`_ +0x28 any any (deprecated, implementation-specific) `Legacy BPF Packet access instructions`_ +0x2c any 0x00 dst = (u32)(dst \* src) `Arithmetic instructions`_ +0x2d any 0x00 if dst > src goto +offset `Jump instructions`_ +0x2e any 0x00 if (u32)dst > (u32)src goto +offset `Jump instructions`_ +0x2f any 0x00 dst \*= src `Arithmetic instructions`_ +0x30 any any (deprecated, implementation-specific) `Legacy BPF Packet access instructions`_ +0x34 0x0 any dst = (u32)((imm != 0) ? (dst / imm) : 0) `Arithmetic instructions`_ +0x35 0x0 any if dst >= imm goto +offset `Jump instructions`_ +0x36 0x0 any if (u32)dst >= imm goto +offset `Jump instructions`_ +0x37 0x0 any dst = (imm != 0) ? (dst / imm) : 0 `Arithmetic instructions`_ +0x38 any any (deprecated, implementation-specific) `Legacy BPF Packet access instructions`_ +0x3c any 0x00 dst = (u32)((imm != 0) ? (dst / src) : 0) `Arithmetic instructions`_ +0x3d any 0x00 if dst >= src goto +offset `Jump instructions`_ +0x3e any 0x00 if (u32)dst >= (u32)src goto +offset `Jump instructions`_ +0x3f any 0x00 dst = (src !+ 0) ? (dst / src) : 0 `Arithmetic instructions`_ +0x40 any any (deprecated, implementation-specific) `Legacy BPF Packet access instructions`_ +0x44 0x0 any dst = (u32)(dst \| imm) `Arithmetic instructions`_ +0x45 0x0 any if dst & imm goto +offset `Jump instructions`_ +0x46 0x0 any if (u32)dst & imm goto +offset `Jump instructions`_ +0x47 0x0 any dst \|= imm `Arithmetic instructions`_ +0x48 any any (deprecated, implementation-specific) `Legacy BPF Packet access instructions`_ +0x4c any 0x00 dst = (u32)(dst \| src) `Arithmetic instructions`_ +0x4d any 0x00 if dst & src goto +offset `Jump instructions`_ +0x4e any 0x00 if (u32)dst & (u32)src goto +offset `Jump instructions`_ +0x4f any 0x00 dst \|= src `Arithmetic instructions`_ +0x50 any any (deprecated, implementation-specific) `Legacy BPF Packet access instructions`_ +0x54 0x0 any dst = (u32)(dst & imm) `Arithmetic instructions`_ +0x55 0x0 any if dst != imm goto +offset `Jump instructions`_ +0x56 0x0 any if (u32)dst != imm goto +offset `Jump instructions`_ +0x57 0x0 any dst &= imm `Arithmetic instructions`_ +0x58 any any (deprecated, implementation-specific) `Legacy BPF Packet access instructions`_ +0x5c any 0x00 dst = (u32)(dst & src) `Arithmetic instructions`_ +0x5d any 0x00 if dst != src goto +offset `Jump instructions`_ +0x5e any 0x00 if (u32)dst != (u32)src goto +offset `Jump instructions`_ +0x5f any 0x00 dst &= src `Arithmetic instructions`_ +0x61 any 0x00 dst = \*(u32 \*)(src + offset) `Load and store instructions`_ +0x62 0x0 any \*(u32 \*)(dst + offset) = imm `Load and store instructions`_ +0x63 any 0x00 \*(u32 \*)(dst + offset) = src `Load and store instructions`_ +0x64 0x0 any dst = (u32)(dst << imm) `Arithmetic instructions`_ +0x65 0x0 any if dst s> imm goto +offset `Jump instructions`_ +0x66 0x0 any if (s32)dst s> (s32)imm goto +offset `Jump instructions`_ +0x67 0x0 any dst <<= imm `Arithmetic instructions`_ +0x69 any 0x00 dst = \*(u16 \*)(src + offset) `Load and store instructions`_ +0x6a 0x0 any \*(u16 \*)(dst + offset) = imm `Load and store instructions`_ +0x6b any 0x00 \*(u16 \*)(dst + offset) = src `Load and store instructions`_ +0x6c any 0x00 dst = (u32)(dst << src) `Arithmetic instructions`_ +0x6d any 0x00 if dst s> src goto +offset `Jump instructions`_ +0x6e any 0x00 if (s32)dst s> (s32)src goto +offset `Jump instructions`_ +0x6f any 0x00 dst <<= src `Arithmetic instructions`_ +0x71 any 0x00 dst = \*(u8 \*)(src + offset) `Load and store instructions`_ +0x72 0x0 any \*(u8 \*)(dst + offset) = imm `Load and store instructions`_ +0x73 any 0x00 \*(u8 \*)(dst + offset) = src `Load and store instructions`_ +0x74 0x0 any dst = (u32)(dst >> imm) `Arithmetic instructions`_ +0x75 0x0 any if dst s>= imm goto +offset `Jump instructions`_ +0x76 0x0 any if (s32)dst s>= (s32)imm goto +offset `Jump instructions`_ +0x77 0x0 any dst >>= imm `Arithmetic instructions`_ +0x79 any 0x00 dst = \*(u64 \*)(src + offset) `Load and store instructions`_ +0x7a 0x0 any \*(u64 \*)(dst + offset) = imm `Load and store instructions`_ +0x7b any 0x00 \*(u64 \*)(dst + offset) = src `Load and store instructions`_ +0x7c any 0x00 dst = (u32)(dst >> src) `Arithmetic instructions`_ +0x7d any 0x00 if dst s>= src goto +offset `Jump instructions`_ +0x7e any 0x00 if (s32)dst s>= (s32)src goto +offset `Jump instructions`_ +0x7f any 0x00 dst >>= src `Arithmetic instructions`_ +0x84 0x0 0x00 dst = (u32)-dst `Arithmetic instructions`_ +0x85 0x0 any call helper function imm `Helper functions`_ +0x87 0x0 0x00 dst = -dst `Arithmetic instructions`_ +0x94 0x0 any dst = (u32)((imm != 0) ? (dst % imm) : dst) `Arithmetic instructions`_ +0x95 0x0 0x00 return `Jump instructions`_ +0x97 0x0 any dst = (imm != 0) ? (dst % imm) : dst `Arithmetic instructions`_ +0x9c any 0x00 dst = (u32)((src != 0) ? (dst % src) : dst) `Arithmetic instructions`_ +0x9f any 0x00 dst = (src != 0) ? (dst % src) : dst `Arithmetic instructions`_ +0xa4 0x0 any dst = (u32)(dst ^ imm) `Arithmetic instructions`_ +0xa5 0x0 any if dst < imm goto +offset `Jump instructions`_ +0xa6 0x0 any if (u32)dst < imm goto +offset `Jump instructions`_ +0xa7 0x0 any dst ^= imm `Arithmetic instructions`_ +0xac any 0x00 dst = (u32)(dst ^ src) `Arithmetic instructions`_ +0xad any 0x00 if dst < src goto +offset `Jump instructions`_ +0xae any 0x00 if (u32)dst < (u32)src goto +offset `Jump instructions`_ +0xaf any 0x00 dst ^= src `Arithmetic instructions`_ +0xb4 0x0 any dst = (u32) imm `Arithmetic instructions`_ +0xb5 0x0 any if dst <= imm goto +offset `Jump instructions`_ +0xa6 0x0 any if (u32)dst <= imm goto +offset `Jump instructions`_ +0xb7 0x0 any dst = imm `Arithmetic instructions`_ +0xbc any 0x00 dst = (u32) src `Arithmetic instructions`_ +0xbd any 0x00 if dst <= src goto +offset `Jump instructions`_ +0xbe any 0x00 if (u32)dst <= (u32)src goto +offset `Jump instructions`_ +0xbf any 0x00 dst = src `Arithmetic instructions`_ +0xc3 any 0x00 lock \*(u32 \*)(dst + offset) += src `Atomic operations`_ +0xc3 any 0x01 lock:: `Atomic operations`_ + + *(u32 *)(dst + offset) += src + src = *(u32 *)(dst + offset) +0xc3 any 0x40 \*(u32 \*)(dst + offset) \|= src `Atomic operations`_ +0xc3 any 0x41 lock:: `Atomic operations`_ + + *(u32 *)(dst + offset) |= src + src = *(u32 *)(dst + offset) +0xc3 any 0x50 \*(u32 \*)(dst + offset) &= src `Atomic operations`_ +0xc3 any 0x51 lock:: `Atomic operations`_ + + *(u32 *)(dst + offset) &= src + src = *(u32 *)(dst + offset) +0xc3 any 0xa0 \*(u32 \*)(dst + offset) ^= src `Atomic operations`_ +0xc3 any 0xa1 lock:: `Atomic operations`_ + + *(u32 *)(dst + offset) ^= src + src = *(u32 *)(dst + offset) +0xc3 any 0xe1 lock:: `Atomic operations`_ + + temp = *(u32 *)(dst + offset) + *(u32 *)(dst + offset) = src + src = temp +0xc3 any 0xf1 lock:: `Atomic operations`_ + + temp = *(u32 *)(dst + offset) + if *(u32)(dst + offset) == R0 + *(u32)(dst + offset) = src + R0 = temp +0xc4 0x0 any dst = (u32)(dst s>> imm) `Arithmetic instructions`_ +0xc5 0x0 any if dst s< imm goto +offset `Jump instructions`_ +0xc6 0x0 any if (s32)dst s< (s32)imm goto +offset `Jump instructions`_ +0xc7 0x0 any dst s>>= imm `Arithmetic instructions`_ +0xcc any 0x00 dst = (u32)(dst s>> src) `Arithmetic instructions`_ +0xcd any 0x00 if dst s< src goto +offset `Jump instructions`_ +0xce any 0x00 if (s32)dst s< (s32)src goto +offset `Jump instructions`_ +0xcf any 0x00 dst s>>= src `Arithmetic instructions`_ +0xd4 0x0 0x10 dst = htole16(dst) `Byte swap instructions`_ +0xd4 0x0 0x20 dst = htole32(dst) `Byte swap instructions`_ +0xd4 0x0 0x40 dst = htole64(dst) `Byte swap instructions`_ +0xd5 0x0 any if dst s<= imm goto +offset `Jump instructions`_ +0xd6 0x0 any if (s32)dst s<= (s32)imm goto +offset `Jump instructions`_ +0xdb any 0x00 lock \*(u64 \*)(dst + offset) += src `Atomic operations`_ +0xdb any 0x01 lock:: `Atomic operations`_ + + *(u64 *)(dst + offset) += src + src = *(u64 *)(dst + offset) +0xdb any 0x40 \*(u64 \*)(dst + offset) \|= src `Atomic operations`_ +0xdb any 0x41 lock:: `Atomic operations`_ + + *(u64 *)(dst + offset) |= src + lock src = *(u64 *)(dst + offset) +0xdb any 0x50 \*(u64 \*)(dst + offset) &= src `Atomic operations`_ +0xdb any 0x51 lock:: `Atomic operations`_ + + *(u64 *)(dst + offset) &= src + src = *(u64 *)(dst + offset) +0xdb any 0xa0 \*(u64 \*)(dst + offset) ^= src `Atomic operations`_ +0xdb any 0xa1 lock:: `Atomic operations`_ + + *(u64 *)(dst + offset) ^= src + src = *(u64 *)(dst + offset) +0xdb any 0xe1 lock:: `Atomic operations`_ + + temp = *(u64 *)(dst + offset) + *(u64 *)(dst + offset) = src + src = temp +0xdb any 0xf1 lock:: `Atomic operations`_ + + temp = *(u64 *)(dst + offset) + if *(u64)(dst + offset) == R0 + *(u64)(dst + offset) = src + R0 = temp +0xdc 0x0 0x10 dst = htobe16(dst) `Byte swap instructions`_ +0xdc 0x0 0x20 dst = htobe32(dst) `Byte swap instructions`_ +0xdc 0x0 0x40 dst = htobe64(dst) `Byte swap instructions`_ +0xdd any 0x00 if dst s<= src goto +offset `Jump instructions`_ +0xde any 0x00 if (s32)dst s<= (s32)src goto +offset `Jump instructions`_ +====== === ==== =================================================== ======================================== From patchwork Tue Oct 4 22:47:42 2022 Content-Type: text/plain; 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([131.107.174.139]) by smtp.gmail.com with ESMTPSA id c13-20020a170902d48d00b0016c0eb202a5sm9487369plg.225.2022.10.04.15.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 15:47:53 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 6/9] bpf, docs: Improve English readability Date: Tue, 4 Oct 2022 22:47:42 +0000 Message-Id: <20221004224745.1430-6-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 In-Reply-To: <20221004224745.1430-1-dthaler1968@googlemail.com> References: <20221004224745.1430-1-dthaler1968@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Improve English readability Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 110 +++++++++++++++++--------- Documentation/bpf/linux-notes.rst | 5 ++ 2 files changed, 77 insertions(+), 38 deletions(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 7c1e245df..4d5a506be 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -7,6 +7,9 @@ eBPF Instruction Set Specification, v1.0 This document specifies version 1.0 of the eBPF instruction set. +The eBPF instruction set consists of eleven 64 bit registers, a program counter, +and an implementation-specific amount (e.g., 512 bytes) of stack space. + Documentation conventions ========================= @@ -27,12 +30,24 @@ The eBPF calling convention is defined as: * R6 - R9: callee saved registers that function calls will preserve * R10: read-only frame pointer to access stack -R0 - R5 are scratch registers and eBPF programs needs to spill/fill them if -necessary across calls. +Registers R0 - R5 are caller-saved registers, meaning the BPF program needs to either +spill them to the BPF stack or move them to callee saved registers if these +arguments are to be reused across multiple function calls. Spilling means +that the value in the register is moved to the BPF stack. The reverse operation +of moving the variable from the BPF stack to the register is called filling. +The reason for spilling/filling is due to the limited number of registers. + +Upon entering execution of an eBPF program, registers R1 - R5 initially can contain +the input arguments for the program (similar to the argc/argv pair for a typical C program). +The actual number of registers used, and their meaning, is defined by the program type; +for example, a networking program might have an argument that includes network packet data +and/or metadata. Instruction encoding ==================== +An eBPF program is a sequence of instructions. + eBPF has two instruction encodings: * the basic instruction encoding, which uses 64 bits to encode an instruction @@ -65,7 +80,7 @@ opcode operation to perform Note that most instructions do not use all of the fields. -Unused fields shall be cleared to zero. +Unused fields must be set to zero. As discussed below in `64-bit immediate instructions`_, a 64-bit immediate instruction uses a 64-bit immediate value that is constructed as follows. @@ -92,7 +107,9 @@ and destination registers, respectively, rather than the register number. Instruction classes ------------------- -The three LSB bits of the 'opcode' field store the instruction class: +The encoding of the 'opcode' field varies and can be determined from +the three least significant bits (LSB) of the 'opcode' field which holds +the "instruction class", as follows: ========= ===== =============================== =================================== class value description reference @@ -138,9 +155,11 @@ instruction class Arithmetic instructions ----------------------- -``BPF_ALU`` uses 32-bit wide operands while ``BPF_ALU64`` uses 64-bit wide operands for +Instruction class ``BPF_ALU`` uses 32-bit wide operands (zeroing the upper 32 bits +of the destination register) while ``BPF_ALU64`` uses 64-bit wide operands for otherwise identical operations. -The 'code' field encodes the operation as below: + +The 4-bit 'code' field encodes the operation as follows: ======== ===== ========================================================== code value description @@ -170,21 +189,23 @@ the destination register is instead set to zero. If execution would result in modulo by zero, the destination register is instead left unchanged. -``BPF_ADD | BPF_X | BPF_ALU`` means:: +Examples: + +``BPF_ADD | BPF_X | BPF_ALU`` (0x0c) means:: dst = (u32) (dst + src) where '(u32)' indicates truncation to 32 bits. -``BPF_ADD | BPF_X | BPF_ALU64`` means:: +``BPF_ADD | BPF_X | BPF_ALU64`` (0x0f) means:: dst = dst + src -``BPF_XOR | BPF_K | BPF_ALU`` means:: +``BPF_XOR | BPF_K | BPF_ALU`` (0xa4) means:: src = (u32) src ^ (u32) imm -``BPF_XOR | BPF_K | BPF_ALU64`` means:: +``BPF_XOR | BPF_K | BPF_ALU64`` (0xa7) means:: src = src ^ imm @@ -202,8 +223,9 @@ The byte swap instructions use an instruction class of ``BPF_ALU`` and a 4-bit The byte swap instructions operate on the destination register only and do not use a separate source register or immediate value. -The 1-bit source operand field in the opcode is used to to select what byte -order the operation convert from or to: +Byte swap instructions use the 1-bit 'source' field in the 'opcode' field +as follows. Instead of indicating the source operator, it is instead +used to select what byte order the operation converts from or to: ========= ===== ================================================= source value description @@ -213,24 +235,33 @@ BPF_TO_BE 0x08 convert between host byte order and big endian ========= ===== ================================================= The 'imm' field encodes the width of the swap operations. The following widths -are supported: 16, 32 and 64. - -Examples: - -``BPF_ALU | BPF_TO_LE | BPF_END`` with imm = 16 means:: - - dst = htole16(dst) - -``BPF_ALU | BPF_TO_BE | BPF_END`` with imm = 64 means:: - - dst = htobe64(dst) +are supported: 16, 32 and 64. The following table summarizes the resulting +possibilities: + +============================= ========= === ======== ================== +opcode construction opcode imm mnemonic pseudocode +============================= ========= === ======== ================== +BPF_END | BPF_TO_LE | BPF_ALU 0xd4 16 le16 dst dst = htole16(dst) +BPF_END | BPF_TO_LE | BPF_ALU 0xd4 32 le32 dst dst = htole32(dst) +BPF_END | BPF_TO_LE | BPF_ALU 0xd4 64 le64 dst dst = htole64(dst) +BPF_END | BPF_TO_BE | BPF_ALU 0xdc 16 be16 dst dst = htobe16(dst) +BPF_END | BPF_TO_BE | BPF_ALU 0xdc 32 be32 dst dst = htobe32(dst) +BPF_END | BPF_TO_BE | BPF_ALU 0xdc 64 be64 dst dst = htobe64(dst) +============================= ========= === ======== ================== + +where + +* mnenomic indicates a short form that might be displayed by some tools such as disassemblers +* 'htoleNN()' indicates converting a NN-bit value from host byte order to little-endian byte order +* 'htobeNN()' indicates converting a NN-bit value from host byte order to big-endian byte order Jump instructions ----------------- -``BPF_JMP32`` uses 32-bit wide operands while ``BPF_JMP`` uses 64-bit wide operands for +Instruction class ``BPF_JMP32`` uses 32-bit wide operands while ``BPF_JMP`` uses 64-bit wide operands for otherwise identical operations. -The 'code' field encodes the operation as below: + +The 4-bit 'code' field encodes the operation as below, where PC is the program counter: ======== ===== ========================= ============ code value description notes @@ -251,9 +282,6 @@ BPF_JSLT 0xc0 PC += off if dst < src signed BPF_JSLE 0xd0 PC += off if dst <= src signed ======== ===== ========================= ============ -The eBPF program needs to store the return value into register R0 before doing a -BPF_EXIT. - Helper functions ~~~~~~~~~~~~~~~~ Helper functions are a concept whereby BPF programs can call into a @@ -283,7 +311,8 @@ For load and store instructions (``BPF_LD``, ``BPF_LDX``, ``BPF_ST``, and ``BPF_ mode size instruction class ============ ====== ================= -The mode modifier is one of: +mode + one of: ============= ===== ==================================== ============= mode modifier value description reference @@ -295,7 +324,8 @@ The mode modifier is one of: BPF_ATOMIC 0xc0 atomic operations `Atomic operations`_ ============= ===== ==================================== ============= -The size modifier is one of: +size + one of: ============= ===== ===================== size modifier value description @@ -306,6 +336,9 @@ The size modifier is one of: BPF_DW 0x18 double word (8 bytes) ============= ===== ===================== +instruction class + the instruction class (see `Instruction classes`_) + Regular load and store operations --------------------------------- @@ -324,7 +357,7 @@ instructions that transfer data between a register and memory. dst = *(size *) (src + offset) -Where size is one of: ``BPF_B``, ``BPF_H``, ``BPF_W``, or ``BPF_DW``. +where size is one of: ``BPF_B``, ``BPF_H``, ``BPF_W``, or ``BPF_DW``. Atomic operations ----------------- @@ -336,9 +369,11 @@ by other eBPF programs or means outside of this specification. All atomic operations supported by eBPF are encoded as store operations that use the ``BPF_ATOMIC`` mode modifier as follows: -* ``BPF_ATOMIC | BPF_W | BPF_STX`` for 32-bit operations -* ``BPF_ATOMIC | BPF_DW | BPF_STX`` for 64-bit operations -* 8-bit and 16-bit wide atomic operations are not supported. +* ``BPF_ATOMIC | BPF_W | BPF_STX`` (0xc3) for 32-bit operations +* ``BPF_ATOMIC | BPF_DW | BPF_STX`` (0xdb) for 64-bit operations + +Note that 8-bit (``BPF_B``) and 16-bit (``BPF_H``) wide atomic operations are not supported, +nor is ``BPF_ATOMIC | | BPF_ST``. The 'imm' field is used to encode the actual atomic operation. Simple atomic operation use a subset of the values defined to encode @@ -353,16 +388,15 @@ BPF_AND 0x50 atomic and BPF_XOR 0xa0 atomic xor ======== ===== =========== - -``BPF_ATOMIC | BPF_W | BPF_STX`` with 'imm' = BPF_ADD means:: +``BPF_ATOMIC | BPF_W | BPF_STX`` (0xc3) with 'imm' = BPF_ADD means:: *(u32 *)(dst + offset) += src -``BPF_ATOMIC | BPF_DW | BPF_STX`` with 'imm' = BPF ADD means:: +``BPF_ATOMIC | BPF_DW | BPF_STX`` (0xdb) with 'imm' = BPF ADD means:: *(u64 *)(dst + offset) += src -In addition to the simple atomic operations, there also is a modifier and +In addition to the simple atomic operations above, there also is a modifier and two complex atomic operations: =========== ================ =========================== diff --git a/Documentation/bpf/linux-notes.rst b/Documentation/bpf/linux-notes.rst index 956b0c866..5860b73ea 100644 --- a/Documentation/bpf/linux-notes.rst +++ b/Documentation/bpf/linux-notes.rst @@ -7,6 +7,11 @@ Linux implementation notes This document provides more details specific to the Linux kernel implementation of the eBPF instruction set. +Stack space +====================== + +Linux currently supports 512 bytes of stack space. + Byte swap instructions ====================== From patchwork Tue Oct 4 22:47:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Thaler X-Patchwork-Id: 12998755 X-Patchwork-Delegate: bpf@iogearbox.net Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E51EC4332F for ; Tue, 4 Oct 2022 22:48:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230167AbiJDWsB (ORCPT ); Tue, 4 Oct 2022 18:48:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230037AbiJDWr5 (ORCPT ); Tue, 4 Oct 2022 18:47:57 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 608F26E889 for ; Tue, 4 Oct 2022 15:47:56 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id z20so7373368plb.10 for ; Tue, 04 Oct 2022 15:47:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=M+IB90+kiyf5PcAMVfEmmklfs6ttME515JdIhVOn4jQ=; b=RabfViOgzEUSM9XQGogxF2OWnylCKPAnQpXn8MzytDYxttnYz+OnIzaSidHfaVaK0j m+nCE5U1qIlD/qvwsri066QofeuCEdam1NA9ON9JG3mvmsFxtgs77IJVSUqodJ0yUaE2 OjLGAnMERqs0T48jhP8tjvG5OUu1GghApecLeu7zVB47OpMz67a07foL1n/VGo6iP+Vo Jpt3ohOxx6lUOdlpxzSr+3TVSXrg9BFdtnsvfUV5Vnw9H6A32+F2YKr0ILQ99dW3obxn qhxAZ2KunKsMdYY/pUClOR4BLdwNuK3wri91K9zW13q+fpwcYGcYQj3kdy9gs7RZqAOJ AtXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=M+IB90+kiyf5PcAMVfEmmklfs6ttME515JdIhVOn4jQ=; b=tFRpm9JAJt5mxsB3gkXg1y+d+2+ad8PpA2uHqU3w7HxfXq2hnWpRSCvvEbqi5PVtZZ GPdlseMkq9Npwc1A/S1s4o6keoc2gpF8glMA/Yvtf8NazQAEUrRDMyeZWIem8/8UnJPJ 38KR2jv35eOsbwnmIaCf8i6FGcO/fxsRbEcjHWVaNvo1mXVitmA0ETaRXI3pyOwwfZyI WM5BxRFLatE/S3SMOu14/NqHSN4PyAMfhdoak1r6VaMBkm7J4w5vFACxUip5HubNFeja wc+HuNurbxDW6FhoZCZyViqGwuWtCWTuqUBH+NHgWkLxxbkbjGQuPgGAF5sQoUnARepw UmxA== X-Gm-Message-State: ACrzQf2klFnGvANCBbe/RWlKD9aCPfrx9T4Su+oqgRBXQdyVO9EBe7ua dgLA1eTsnaos3ScSX4XjkyW+7sRGRUE= X-Google-Smtp-Source: AMsMyM6bQacfZXene3Hf2h1Owmtp0oGUtLm7ZYb8hKhO885WxM6OQm/uGH1KoJdZALv6mrN55P5k2g== X-Received: by 2002:a17:902:d4d2:b0:17a:a33:e334 with SMTP id o18-20020a170902d4d200b0017a0a33e334mr29132980plg.17.1664923675441; Tue, 04 Oct 2022 15:47:55 -0700 (PDT) Received: from mariner-vm.. ([131.107.174.139]) by smtp.gmail.com with ESMTPSA id c13-20020a170902d48d00b0016c0eb202a5sm9487369plg.225.2022.10.04.15.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 15:47:54 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 7/9] bpf, docs: Add extended 64-bit immediate instructions Date: Tue, 4 Oct 2022 22:47:43 +0000 Message-Id: <20221004224745.1430-7-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 In-Reply-To: <20221004224745.1430-1-dthaler1968@googlemail.com> References: <20221004224745.1430-1-dthaler1968@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Add extended 64-bit immediate instructions Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 54 +++++++++++++++++++++++++-- Documentation/bpf/linux-notes.rst | 10 +++++ 2 files changed, 60 insertions(+), 4 deletions(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 4d5a506be..5ce1a85cd 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -425,14 +425,54 @@ and loaded back to ``R0``. ----------------------------- Instructions with the ``BPF_IMM`` 'mode' modifier use the wide instruction -encoding for an extra imm64 value. +encoding defined in `Instruction encoding`_, and use the 'src' field of the +basic instruction to hold an opcode subtype. + +The following instructions are defined, and use additional concepts defined below: + +========================= ====== === ===================================== =========== ============== +opcode construction opcode src pseudocode imm type dst type +========================= ====== === ===================================== =========== ============== +BPF_IMM | BPF_DW | BPF_LD 0x18 0x0 dst = imm64 integer integer +BPF_IMM | BPF_DW | BPF_LD 0x18 0x1 dst = map_by_fd(imm) map fd map +BPF_IMM | BPF_DW | BPF_LD 0x18 0x2 dst = mva(map_by_fd(imm)) + next_imm map fd data pointer +BPF_IMM | BPF_DW | BPF_LD 0x18 0x3 dst = variable_addr(imm) variable id data pointer +BPF_IMM | BPF_DW | BPF_LD 0x18 0x4 dst = code_addr(imm) integer code pointer +BPF_IMM | BPF_DW | BPF_LD 0x18 0x5 dst = map_by_idx(imm) map index map +BPF_IMM | BPF_DW | BPF_LD 0x18 0x6 dst = mva(map_by_idx(imm)) + next_imm map index data pointer +========================= ====== === ===================================== =========== ============== -There is currently only one such instruction. +where + +* map_by_fd(fd) means to convert a 32-bit POSIX file descriptor into an address of a map object (see `Map objects`_) +* map_by_index(index) means to convert a 32-bit index into an address of a map object +* mva(map) gets the address of the first value in a given map object +* variable_addr(id) gets the address of a variable (see `Variables`_) with a given id +* code_addr(offset) gets the address of the instruction at a specified relative offset in units of 64-bit blocks +* the 'imm type' can be used by disassemblers for display +* the 'dst type' can be used for verification and JIT compilation purposes + +Map objects +~~~~~~~~~~~ + +Maps are shared memory regions accessible by eBPF programs on some platforms, where we use the term "map object" +to refer to an object containing the data and metadata (e.g., size) about the memory region. +A map can have various semantics as defined in a separate document, and may or may not have a single +contiguous memory region, but the 'mva(map)' is currently only defined for maps that do have a single +contiguous memory region. Support for maps is optional. -``BPF_LD | BPF_DW | BPF_IMM`` means:: +Each map object can have a POSIX file descriptor (fd) if supported by the platform, +where 'map_by_fd(fd)' means to get the map with the specified file descriptor. +Each eBPF program can also be defined to use a set of maps associated with the program +at load time, and 'map_by_index(index)' means to get the map with the given index in the set +associated with the eBPF program containing the instruction. - dst = imm64 +Variables +~~~~~~~~~ +Variables are memory regions, identified by integer ids, accessible by eBPF programs on +some platforms. The 'variable_addr(id)' operation means to get the address of the memory region +identified by the given id. Support for such variables is optional. Legacy BPF Packet access instructions ------------------------------------- @@ -460,6 +500,12 @@ opcode src imm description referenc 0x16 0x0 any if (u32)dst == imm goto +offset `Jump instructions`_ 0x17 0x0 any dst -= imm `Arithmetic instructions`_ 0x18 0x0 any dst = imm64 `64-bit immediate instructions`_ +0x18 0x1 any dst = map_by_fd(imm) `64-bit immediate instructions`_ +0x18 0x2 any dst = mva(map_by_fd(imm)) + next_imm `64-bit immediate instructions`_ +0x18 0x3 any dst = variable_addr(imm) `64-bit immediate instructions`_ +0x18 0x4 any dst = code_addr(imm) `64-bit immediate instructions`_ +0x18 0x5 any dst = map_by_idx(imm) `64-bit immediate instructions`_ +0x18 0x6 any dst = mva(map_by_idx(imm)) + next_imm `64-bit immediate instructions`_ 0x1c any 0x00 dst = (u32)(dst - src) `Arithmetic instructions`_ 0x1d any 0x00 if dst == src goto +offset `Jump instructions`_ 0x1e any 0x00 if (u32)dst == (u32)src goto +offset `Jump instructions`_ diff --git a/Documentation/bpf/linux-notes.rst b/Documentation/bpf/linux-notes.rst index 5860b73ea..fb050a485 100644 --- a/Documentation/bpf/linux-notes.rst +++ b/Documentation/bpf/linux-notes.rst @@ -17,6 +17,16 @@ Byte swap instructions ``BPF_FROM_LE`` and ``BPF_FROM_BE`` exist as aliases for ``BPF_TO_LE`` and ``BPF_TO_BE`` respectively. +Map objects +=========== + +Linux only supports the 'mva(map)' operation on array maps with a single element. + +Variables +========= + +Linux uses BTF ids to identify variables. + Legacy BPF Packet access instructions ===================================== From patchwork Tue Oct 4 22:47:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Thaler X-Patchwork-Id: 12998756 X-Patchwork-Delegate: bpf@iogearbox.net Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4DF7C43217 for ; Tue, 4 Oct 2022 22:48:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230037AbiJDWsC (ORCPT ); Tue, 4 Oct 2022 18:48:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230043AbiJDWr6 (ORCPT ); Tue, 4 Oct 2022 18:47:58 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FB756E892 for ; Tue, 4 Oct 2022 15:47:57 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id r18so759622pgr.12 for ; Tue, 04 Oct 2022 15:47:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=L3HBuLVOIuSnWaNCSD43IXohM6FfOxl09nrs6BQJGy8=; b=naqZgqRyry8QYE1r+A2R8AKLunuEGem5xZRaT3JkGY3DqSMcUqCdSud68bBgi0KBA8 FWKzftoOWfsBBrMi4M67csNCwSwuUrvSBovZ1i56OXMdWbNFr+jTChsBfyo7/f3Iktgu 7/deZqdzGjm0kuISGzZz/ZmKma/Cy8qP/vrV1TppTGUkv5Od9j7L/+XV5liU50tN74un Ub5OOqvaaCcDdPPiEg1YJC396kTiMeBHFDpxiuiZSdQmAgBTZCgBBI1XnKmsLCUxW/0t CBuYdDjPbhLJkYZTJ5nubJh6tuAUfYX7YkTgOCSPoeVYvO0VYarBcgrF/qgF6d3K0yTY 40kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=L3HBuLVOIuSnWaNCSD43IXohM6FfOxl09nrs6BQJGy8=; b=MQpku5dSzcr5aBwyyBfMr5/EpVswG5nYtjslkn8t+KLAQqnKq1nIQqSamfArDRs/2D YCyt10RjWXVIbxI+Vir/d7UoQi0Ir5AFpqiC+oQzvKv/zltYFgUrEymsAUy6LSv4CJVc baCqcqUM7bCsfYwq0S9N2B9i/BZbLJXfplRyNv9AFC6yRtMkEpDdHjh1lwCO/KtQGI8T 6lLXNXUvNGU9VGIdjCalPbyJOdrCocmE1qsj5pblVqu9uEWixgtYO/CUmhscQQcyBTzk hy89cbt+Mc4kA5xP65MK7meLvtahhGu6zJQoK/pvB94b+LyOxS6VsyM3NDKiQcC8fgqu /53g== X-Gm-Message-State: ACrzQf0syz7bml0S+xUIDtSxRcda8jVrRUMogIuwLUGtl8YonFEm8jdx 9JXJDCflGem0xbzTI4iDXIu9brfUfbw= X-Google-Smtp-Source: AMsMyM5zpXRsZZJbWupZUAcwi2/Lq/VlqZ7+hLyymexXxDjNutmLLe/OXW6a49epSPXwqmcKz5HpBw== X-Received: by 2002:a63:fa42:0:b0:44d:b59c:674b with SMTP id g2-20020a63fa42000000b0044db59c674bmr11301355pgk.207.1664923676563; Tue, 04 Oct 2022 15:47:56 -0700 (PDT) Received: from mariner-vm.. ([131.107.174.139]) by smtp.gmail.com with ESMTPSA id c13-20020a170902d48d00b0016c0eb202a5sm9487369plg.225.2022.10.04.15.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 15:47:56 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 8/9] bpf, docs: Add extended call instructions Date: Tue, 4 Oct 2022 22:47:44 +0000 Message-Id: <20221004224745.1430-8-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 In-Reply-To: <20221004224745.1430-1-dthaler1968@googlemail.com> References: <20221004224745.1430-1-dthaler1968@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Add extended call instructions Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 52 +++++++++++++++++---------- 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 5ce1a85cd..d0685a06f 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -263,24 +263,26 @@ otherwise identical operations. The 4-bit 'code' field encodes the operation as below, where PC is the program counter: -======== ===== ========================= ============ -code value description notes -======== ===== ========================= ============ -BPF_JA 0x00 PC += off BPF_JMP only -BPF_JEQ 0x10 PC += off if dst == src -BPF_JGT 0x20 PC += off if dst > src unsigned -BPF_JGE 0x30 PC += off if dst >= src unsigned -BPF_JSET 0x40 PC += off if dst & src -BPF_JNE 0x50 PC += off if dst != src -BPF_JSGT 0x60 PC += off if dst > src signed -BPF_JSGE 0x70 PC += off if dst >= src signed -BPF_CALL 0x80 function call see `Helper functions`_ -BPF_EXIT 0x90 function / program return BPF_JMP only -BPF_JLT 0xa0 PC += off if dst < src unsigned -BPF_JLE 0xb0 PC += off if dst <= src unsigned -BPF_JSLT 0xc0 PC += off if dst < src signed -BPF_JSLE 0xd0 PC += off if dst <= src signed -======== ===== ========================= ============ +======== ===== === ========================== ======================== +code value src description notes +======== ===== === ========================== ======================== +BPF_JA 0x0 0x0 PC += offset BPF_JMP only +BPF_JEQ 0x1 any PC += offset if dst == src +BPF_JGT 0x2 any PC += offset if dst > src unsigned +BPF_JGE 0x3 any PC += offset if dst >= src unsigned +BPF_JSET 0x4 any PC += offset if dst & src +BPF_JNE 0x5 any PC += offset if dst != src +BPF_JSGT 0x6 any PC += offset if dst > src signed +BPF_JSGE 0x7 any PC += offset if dst >= src signed +BPF_CALL 0x8 0x0 call helper function imm see `Helper functions`_ +BPF_CALL 0x8 0x1 call PC += offset see `eBPF functions`_ +BPF_CALL 0x8 0x2 call runtime function imm see `Runtime functions`_ +BPF_EXIT 0x9 0x0 return BPF_JMP only +BPF_JLT 0xa any PC += offset if dst < src unsigned +BPF_JLE 0xb any PC += offset if dst <= src unsigned +BPF_JSLT 0xc any PC += offset if dst < src signed +BPF_JSLE 0xd any PC += offset if dst <= src signed +======== ===== === ========================== ======================== Helper functions ~~~~~~~~~~~~~~~~ @@ -299,6 +301,18 @@ with the remaining registers being ignored. The definition of a helper function is responsible for specifying the type (e.g., integer, pointer, etc.) of the value returned, the number of arguments, and the type of each argument. +Runtime functions +~~~~~~~~~~~~~~~~~ +Runtime functions are like helper functions except that they are not specific +to eBPF programs. They use a different numbering space from helper functions, +but otherwise the same considerations apply. + +eBPF functions +~~~~~~~~~~~~~~ +eBPF functions are functions exposed by the same eBPF program as the caller, +and are referenced by offset from the call instruction, similar to ``BPF_JA``. +A ``BPF_EXIT`` within the eBPF function will return to the caller. + Load and store instructions =========================== @@ -580,6 +594,8 @@ opcode src imm description referenc 0x7f any 0x00 dst >>= src `Arithmetic instructions`_ 0x84 0x0 0x00 dst = (u32)-dst `Arithmetic instructions`_ 0x85 0x0 any call helper function imm `Helper functions`_ +0x85 0x1 any call PC += offset `eBPF functions`_ +0x85 0x2 any call runtime function imm `Runtime functions`_ 0x87 0x0 0x00 dst = -dst `Arithmetic instructions`_ 0x94 0x0 any dst = (u32)((imm != 0) ? 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([131.107.174.139]) by smtp.gmail.com with ESMTPSA id c13-20020a170902d48d00b0016c0eb202a5sm9487369plg.225.2022.10.04.15.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 15:47:56 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 9/9] bpf, docs: Add note about reserved instruction Date: Tue, 4 Oct 2022 22:47:45 +0000 Message-Id: <20221004224745.1430-9-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 In-Reply-To: <20221004224745.1430-1-dthaler1968@googlemail.com> References: <20221004224745.1430-1-dthaler1968@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Add note about reserved instruction Signed-off-by: Dave Thaler --- Documentation/bpf/clang-notes.rst | 5 +++++ Documentation/bpf/instruction-set.rst | 3 +++ 2 files changed, 8 insertions(+) diff --git a/Documentation/bpf/clang-notes.rst b/Documentation/bpf/clang-notes.rst index 528feddf2..40c618551 100644 --- a/Documentation/bpf/clang-notes.rst +++ b/Documentation/bpf/clang-notes.rst @@ -20,6 +20,11 @@ Arithmetic instructions For CPU versions prior to 3, Clang v7.0 and later can enable ``BPF_ALU`` support with ``-Xclang -target-feature -Xclang +alu32``. In CPU version 3, support is automatically included. +Reserved instructions +==================== + +Clang will generate the reserved ``BPF_CALL | BPF_X | BPF_JMP`` (0x8d) instruction if ``-O0`` is used. + Atomic operations ================= diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index d0685a06f..72d59b3c6 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -301,6 +301,9 @@ with the remaining registers being ignored. The definition of a helper function is responsible for specifying the type (e.g., integer, pointer, etc.) of the value returned, the number of arguments, and the type of each argument. +Note that ``BPF_CALL | BPF_X | BPF_JMP`` (0x8d), where the helper function integer +would be read from a specified register, is reserved and currently not permitted. + Runtime functions ~~~~~~~~~~~~~~~~~ Runtime functions are like helper functions except that they are not specific