From patchwork Wed Oct 5 09:06:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12999085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1DF37C433FE for ; Wed, 5 Oct 2022 09:07:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B19A10E46D; Wed, 5 Oct 2022 09:07:48 +0000 (UTC) Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3423310E202; Wed, 5 Oct 2022 09:07:45 +0000 (UTC) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2958vh8N013875; Wed, 5 Oct 2022 09:07:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=y5Wja1p/9P93G5DwYgWzDk04yKR4AAF3vxxCF5pAYHk=; b=aW1nFi86sTNiRUTo+dLOTh00AtXy8oZOLLDFe7RFgzL6cpCCd/HrJsF2SCmUdOyRu2sY lRi6Blvm3cW8ZXEMPsLGREJS4irhLVIJ8JJVCck1exyT7DnIjLhU1/aIjjtlt3HKOqFC 72MB619O4+mWqfP/GfKmDL9vrKMW5hTalBaygCizKI4Jfg0EKj6Vyub64JJ5de2nYe/B aVpgfxIG5WjPDNOEYoDVz3ZFFBtFPIoxIlRIsRBNzoDBtnJQlkWGiHtFxxU7hFYmoeBn Jb8luUAId9ii3zff00pccJi8tjQcFcoDjHZUphpQq2PR+ifjOO9ZtY2Xl/4kX3ZVubVs qw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k0jtdjfpc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 09:07:35 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29597YaL021343 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 5 Oct 2022 09:07:34 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 5 Oct 2022 02:07:28 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , Stephen Boyd , Dmitry Baryshkov , Philipp Zabel Subject: [PATCH v7 1/6] dt-bindings: clk: qcom: Support gpu cx gdsc reset Date: Wed, 5 Oct 2022 14:36:59 +0530 Message-ID: <20221005143618.v7.1.I68b749219741db01356a42d782f74265d29a2ac3@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> References: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Qp5z7f0LSDOnr_19LVap__WJocwp0Ljr X-Proofpoint-ORIG-GUID: Qp5z7f0LSDOnr_19LVap__WJocwp0Ljr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-04_09,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 suspectscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210050057 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Akhil P Oommen , Michael Turquette , Konrad Dybcio , Douglas Anderson , Rob Herring , linux-kernel@vger.kernel.org, Stephen Boyd , krzysztof.kozlowski@linaro.org, Andy Gross , Krzysztof Kozlowski , linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add necessary definitions in gpucc bindings to ensure gpu cx gdsc collapse through 'reset' framework for SC7280. Signed-off-by: Akhil P Oommen Acked-by: Krzysztof Kozlowski --- (no changes since v1) include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gpucc-sc7280.h b/include/dt-bindings/clock/qcom,gpucc-sc7280.h index 669b23b..843a31b 100644 --- a/include/dt-bindings/clock/qcom,gpucc-sc7280.h +++ b/include/dt-bindings/clock/qcom,gpucc-sc7280.h @@ -32,4 +32,7 @@ #define GPU_CC_CX_GDSC 0 #define GPU_CC_GX_GDSC 1 +/* GPU_CC reset IDs */ +#define GPU_CX_COLLAPSE 0 + #endif From patchwork Wed Oct 5 09:07:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12999086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE14BC433FE for ; Wed, 5 Oct 2022 09:07:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A39EA10E466; Wed, 5 Oct 2022 09:07:49 +0000 (UTC) Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id B21C510E46D; Wed, 5 Oct 2022 09:07:45 +0000 (UTC) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29590MI5019005; Wed, 5 Oct 2022 09:07:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=yTjmXTJTL0m+AUUrj2ObPl+pUncLDzooc+5ieL1P0bs=; b=eOPbdjxvCfK4rNyLljVafL0lvorBiDY1LMTkEDitpxzlppdkGpRqsILZbvYs3Ad9lHTA e2Wz3PznGuX504I1v1Cf+PBYdBLRVtvQUmiofd1liH9N00FlPyd6hZ3mGB3NzMCm/MWX HqyHHZNq2n2NbvOT98T+RHOxd6kivjb0YsIgfgTffps7uHi8FfI9W18DoRga/Af0birS G31kjMQgJ2ek9BnapQTlc2c9SDsDk0eOLe5LhEXeAq6KtUTBk8xUPv0VjPIv0dmdhHF+ mu7kSMh69/0sm1VEn4JckrEiYxXcPa7oHYyRS6aNQfaQphABdN86BERsGkPpN2gCOmZh /w== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k0jtdjfpf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 09:07:40 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29597djo000910 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 5 Oct 2022 09:07:39 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 5 Oct 2022 02:07:34 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , Stephen Boyd , Dmitry Baryshkov , Philipp Zabel Subject: [PATCH v7 2/6] clk: qcom: Allow custom reset ops Date: Wed, 5 Oct 2022 14:37:00 +0530 Message-ID: <20221005143618.v7.2.I75baff799a363bbb960376539e3a0f737377c3f1@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> References: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nDgqOmhTpEoIdgZnL772SocnNQj5_ihz X-Proofpoint-ORIG-GUID: nDgqOmhTpEoIdgZnL772SocnNQj5_ihz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-04_09,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 suspectscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210050057 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Akhil P Oommen , Michael Turquette , Konrad Dybcio , Douglas Anderson , linux-kernel@vger.kernel.org, Stephen Boyd , krzysztof.kozlowski@linaro.org, Andy Gross , linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Allow soc specific clk drivers to specify a custom reset operation. We will use this in an upcoming patch to allow gpucc driver to specify a differet reset operation for cx_gdsc. Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- (no changes since v3) Changes in v3: - Use pointer to const for "struct qcom_reset_ops" in qcom_reset_map (Krzysztof) Changes in v2: - Return error when a particular custom reset op is not implemented. (Dmitry) drivers/clk/qcom/reset.c | 27 ++++++++++++++++++++++++++- drivers/clk/qcom/reset.h | 8 ++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c index 2a16adb..10ef71b 100644 --- a/drivers/clk/qcom/reset.c +++ b/drivers/clk/qcom/reset.c @@ -13,7 +13,20 @@ static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id) { - struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev); + struct qcom_reset_controller *rst; + const struct qcom_reset_map *map; + + rst = to_qcom_reset_controller(rcdev); + map = &rst->reset_map[id]; + + if (map->ops && map->ops->reset) + return map->ops->reset(map->priv); + /* + * If custom ops is implemented but just not this callback, return + * error + */ + else if (map->ops) + return -EOPNOTSUPP; rcdev->ops->assert(rcdev, id); udelay(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */ @@ -30,6 +43,12 @@ qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) rst = to_qcom_reset_controller(rcdev); map = &rst->reset_map[id]; + + if (map->ops && map->ops->assert) + return map->ops->assert(map->priv); + else if (map->ops) + return -EOPNOTSUPP; + mask = BIT(map->bit); return regmap_update_bits(rst->regmap, map->reg, mask, mask); @@ -44,6 +63,12 @@ qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) rst = to_qcom_reset_controller(rcdev); map = &rst->reset_map[id]; + + if (map->ops && map->ops->deassert) + return map->ops->deassert(map->priv); + else if (map->ops) + return -EOPNOTSUPP; + mask = BIT(map->bit); return regmap_update_bits(rst->regmap, map->reg, mask, 0); diff --git a/drivers/clk/qcom/reset.h b/drivers/clk/qcom/reset.h index b8c1135..a4d767b 100644 --- a/drivers/clk/qcom/reset.h +++ b/drivers/clk/qcom/reset.h @@ -8,10 +8,18 @@ #include +struct qcom_reset_ops { + int (*reset)(void *priv); + int (*assert)(void *priv); + int (*deassert)(void *priv); +}; + struct qcom_reset_map { unsigned int reg; u8 bit; u8 udelay; + const struct qcom_reset_ops *ops; + void *priv; }; struct regmap; From patchwork Wed Oct 5 09:07:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12999087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6DABC43217 for ; Wed, 5 Oct 2022 09:08:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8426710E202; Wed, 5 Oct 2022 09:07:59 +0000 (UTC) Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3FC6A10E477; Wed, 5 Oct 2022 09:07:51 +0000 (UTC) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2958utO6018604; Wed, 5 Oct 2022 09:07:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=W8u9tnQA1mw68k4uf7jskmgEvULBCNvvvouNBcP0KiU=; b=YDflREScp6o3Tz7OsZcKUlRq+SOKmjtZxYHGQPo3m/Zs9UtIM0BPcGudzXzK5IPTa9FI xcnETmZT/yt0pTk2EfCmUbm3W8MUTVkYSsZH0OuvwMLi3BcVKb4ue4u178gRWPmAO0fY 027zK7LBgqJPbkdfu0VdwimogqM1seewBKL+ZRwNmGnVaA2C/K/QPMZs6kzqy2r3DckE QM1z1znjGwWTHiAdWf6YKkS0d53mx9eeNhh/qUV3aH6IjbcsidoUucCMrzuPDtw6mmpY 10aoIyFrtSj2SANZZbe84KuszJmMR8uwr0Aj11JBnPaMKeT1DXTFW4y36Y4Sk2VL+zYO ow== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k0esctw9p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 09:07:46 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29597jke000915 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 5 Oct 2022 09:07:45 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 5 Oct 2022 02:07:40 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , Stephen Boyd , Dmitry Baryshkov , Philipp Zabel Subject: [PATCH v7 3/6] clk: qcom: gdsc: Add a reset op to poll gdsc collapse Date: Wed, 5 Oct 2022 14:37:01 +0530 Message-ID: <20221005143618.v7.3.I162c4be55f230cd439f0643f1624527bdc8a9831@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> References: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: aou67NIQS7VoPsrnE1ynqyOLpjiMSD0h X-Proofpoint-ORIG-GUID: aou67NIQS7VoPsrnE1ynqyOLpjiMSD0h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-04_09,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210050057 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Akhil P Oommen , Michael Turquette , Konrad Dybcio , Douglas Anderson , linux-kernel@vger.kernel.org, Stephen Boyd , krzysztof.kozlowski@linaro.org, Andy Gross , linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a reset op compatible function to poll for gdsc collapse. This is required because: 1. We don't wait for it to turn OFF at hardware for VOTABLE GDSCs. 2. There is no way for client drivers (eg. gpu driver) to do put-with-wait for these gdscs which is required in some scenarios (eg. GPU recovery). Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- Changes in v7: - Update commit message (Bjorn) Changes in v2: - Minor update to function prototype drivers/clk/qcom/gdsc.c | 23 +++++++++++++++++++---- drivers/clk/qcom/gdsc.h | 7 +++++++ 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 7cf5e13..ccef742 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -17,6 +17,7 @@ #include #include #include "gdsc.h" +#include "reset.h" #define PWR_ON_MASK BIT(31) #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20) @@ -116,7 +117,8 @@ static int gdsc_hwctrl(struct gdsc *sc, bool en) return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); } -static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) +static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status, + s64 timeout_us, unsigned int interval_ms) { ktime_t start; @@ -124,7 +126,9 @@ static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status) do { if (gdsc_check_status(sc, status)) return 0; - } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US); + if (interval_ms) + msleep(interval_ms); + } while (ktime_us_delta(ktime_get(), start) < timeout_us); if (gdsc_check_status(sc, status)) return 0; @@ -189,7 +193,7 @@ static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status) udelay(1); } - ret = gdsc_poll_status(sc, status); + ret = gdsc_poll_status(sc, status, TIMEOUT_US, 0); WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n"); if (!ret && status == GDSC_OFF && sc->rsupply) { @@ -360,7 +364,7 @@ static int _gdsc_disable(struct gdsc *sc) */ udelay(1); - ret = gdsc_poll_status(sc, GDSC_ON); + ret = gdsc_poll_status(sc, GDSC_ON, TIMEOUT_US, 0); if (ret) return ret; } @@ -608,3 +612,14 @@ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) return 0; } EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable); + +int gdsc_wait_for_collapse(void *priv) +{ + struct gdsc *sc = priv; + int ret; + + ret = gdsc_poll_status(sc, GDSC_OFF, 500000, 5); + WARN(ret, "%s status stuck at 'on'", sc->pd.name); + return ret; +} +EXPORT_SYMBOL_GPL(gdsc_wait_for_collapse); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 981a12c..5395f69 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -12,6 +12,7 @@ struct regmap; struct regulator; struct reset_controller_dev; +struct qcom_reset_map; /** * struct gdsc - Globally Distributed Switch Controller @@ -88,6 +89,7 @@ int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *, struct regmap *); void gdsc_unregister(struct gdsc_desc *desc); int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain); +int gdsc_wait_for_collapse(void *priv); #else static inline int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *rcdev, @@ -97,5 +99,10 @@ static inline int gdsc_register(struct gdsc_desc *desc, } static inline void gdsc_unregister(struct gdsc_desc *desc) {}; + +static int gdsc_wait_for_collapse(void *priv) +{ + return -ENOSYS; +} #endif /* CONFIG_QCOM_GDSC */ #endif /* __QCOM_GDSC_H__ */ From patchwork Wed Oct 5 09:07:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12999088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 559FDC433F5 for ; Wed, 5 Oct 2022 09:08:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D4DD10E480; Wed, 5 Oct 2022 09:08:03 +0000 (UTC) Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id D583910E202; Wed, 5 Oct 2022 09:07:56 +0000 (UTC) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2958u87L031102; Wed, 5 Oct 2022 09:07:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=2cXmoaZmUvxrzyNuWMuVIZ2vrVLcb3DzfphaeWIbGlE=; b=OYSHzGXo+aCBtiw4pl5yUOVRSl4PUGEFNoOLxBtWGFrIvOuw/PG71xCNdbaarJT7bZnF YXOizmdBF0A8SPutXXEz6YKS1ytxOn702s+oIvIgPYZRYYtp+Fe4bVC/sKWoQVb69c83 qIODSJH9WaXLfRVcbL3TPhDmRrBt6bp8ZFZcyicTi6B4SkIl7dR4TjHyV8PCccCVKVZt m2nffGQCjHH1K14OTsMIKU1qZV/eB4WSLyJmvMmhkN/4kILtBoJrAbFHfyYDS0xFwqbN PwG7/2/PcWvIRytpUc4r5JGJe1pJlALkIF+tCIz//23FKj+Y5MUOVFdjdp2OZQTX5ld9 rw== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k0m88jc31-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 09:07:51 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29597pTS000940 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 5 Oct 2022 09:07:51 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 5 Oct 2022 02:07:45 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , Stephen Boyd , Dmitry Baryshkov , Philipp Zabel Subject: [PATCH v7 4/6] clk: qcom: gpucc-sc7280: Add cx collapse reset support Date: Wed, 5 Oct 2022 14:37:02 +0530 Message-ID: <20221005143618.v7.4.I5e64ff4b77bb9079eb2edeea8a02585c9e76778f@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> References: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: o6lKBJLVZhDBxI_U4fxJxwsRA1KGLR2t X-Proofpoint-ORIG-GUID: o6lKBJLVZhDBxI_U4fxJxwsRA1KGLR2t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-04_09,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 adultscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 suspectscore=0 bulkscore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210050057 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Akhil P Oommen , Michael Turquette , Konrad Dybcio , Douglas Anderson , linux-kernel@vger.kernel.org, Stephen Boyd , krzysztof.kozlowski@linaro.org, Andy Gross , linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Allow a consumer driver to poll for cx gdsc collapse through Reset framework. Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov --- (no changes since v3) Changes in v3: - Convert 'struct qcom_reset_ops cx_gdsc_reset' to 'static const' (Krzysztof) Changes in v2: - Minor update to use the updated custom reset ops implementation drivers/clk/qcom/gpucc-sc7280.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index 9a832f2..fece3f4 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -433,12 +433,22 @@ static const struct regmap_config gpu_cc_sc7280_regmap_config = { .fast_io = true, }; +static const struct qcom_reset_ops cx_gdsc_reset = { + .reset = gdsc_wait_for_collapse, +}; + +static const struct qcom_reset_map gpucc_sc7280_resets[] = { + [GPU_CX_COLLAPSE] = { .ops = &cx_gdsc_reset, .priv = &cx_gdsc }, +}; + static const struct qcom_cc_desc gpu_cc_sc7280_desc = { .config = &gpu_cc_sc7280_regmap_config, .clks = gpu_cc_sc7280_clocks, .num_clks = ARRAY_SIZE(gpu_cc_sc7280_clocks), .gdscs = gpu_cc_sc7180_gdscs, .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs), + .resets = gpucc_sc7280_resets, + .num_resets = ARRAY_SIZE(gpucc_sc7280_resets), }; static const struct of_device_id gpu_cc_sc7280_match_table[] = { From patchwork Wed Oct 5 09:07:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12999089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26F3FC433FE for ; Wed, 5 Oct 2022 09:08:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2EEA710E4AC; Wed, 5 Oct 2022 09:08:10 +0000 (UTC) Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id A2B6510E48A; Wed, 5 Oct 2022 09:08:03 +0000 (UTC) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29597JO2016971; Wed, 5 Oct 2022 09:07:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=SP4Y9BgfE42D6Oc8eIt8Kgqn2zuvP2VZ7va2Ala/Aqg=; b=bZI72s+boI19QMikaGplQUkVYzT8Bty5YG4QMwKChemrbNHhTJ2Y+krV8jlu7RNIv+q4 ej51z2FPssQ4BZytSh4vhAzp45293uS8jeyVubqXbvjRoCFG2h6KbH37TCLzlk5DsYm9 Zox+Rqq/LBK1oPxnOP/6Q/0oi3FdNLEEKavAKZ0saIB7nPsxiPBqTUHn679M/2+xAaJE cB06aw2ll9jS1AAHvHSoDCWfHmiSV0389ISuyr8MPxogRia+WIaoLRYzMx0aTbjBWENh QQRF5pQYK+p17eBo1K8H266pc103ItQrvXGk0DQebzk2BCGPSEJRzTfvlQRecgefEG8J pA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k0esctw9v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 09:07:57 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29597vYZ006155 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 5 Oct 2022 09:07:57 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 5 Oct 2022 02:07:51 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , Stephen Boyd , Dmitry Baryshkov , Philipp Zabel Subject: [PATCH v7 5/6] dt-bindings: drm/msm/gpu: Add optional resets Date: Wed, 5 Oct 2022 14:37:03 +0530 Message-ID: <20221005143618.v7.5.Ieffadd08a071a233213ced4406bf84bb5922ab9a@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> References: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9lQHNYY-FBHr4AFisXlkzqXgCDDlSX7j X-Proofpoint-ORIG-GUID: 9lQHNYY-FBHr4AFisXlkzqXgCDDlSX7j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-04_09,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210050057 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Krzysztof Kozlowski , Akhil P Oommen , linux-kernel@vger.kernel.org, Douglas Anderson , Abhinav Kumar , David Airlie , krzysztof.kozlowski@linaro.org, Rob Herring , Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add an optional reference to GPUCC reset which can be used to ensure cx gdsc collapse during gpu recovery. Signed-off-by: Akhil P Oommen Acked-by: Rob Herring Acked-by: Krzysztof Kozlowski --- (no changes since v5) Changes in v5: - Nit: Remove a duplicate blank line (Krzysztof) Changes in v4: - New patch in v4 Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 3397bc3..408ed97 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -109,6 +109,12 @@ properties: For GMU attached devices a phandle to the GMU device that will control the power for the GPU. + resets: + maxItems: 1 + + reset-names: + items: + - const: cx_collapse required: - compatible From patchwork Wed Oct 5 09:07:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 12999090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51A11C433FE for ; Wed, 5 Oct 2022 09:08:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 41E8E10E477; Wed, 5 Oct 2022 09:08:14 +0000 (UTC) Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6CA6810E48A; Wed, 5 Oct 2022 09:08:07 +0000 (UTC) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2958upN5021784; Wed, 5 Oct 2022 09:08:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=zOz9DK0Yg3l8J1gu2rZxNW57wndut0TuBanZP/1eDxQ=; b=gFloYDbF4iF5l5qYWZrqFTPuuD9JEjrlf/8a3JJjMB3jVSZ1xH/Kfr55WPAQWuc1NqAl aabs7b6VEQC2LVdEhsUDLmS5ULytHcovVfcjcmcBtD+vY7Sg2Xv16PttaPQKNYuVVYMF qEKn/PwX/I/OktiUTdbjb2Fkp1As0GTwCtcbAOvXHVW//1t1+EwBebHAhgi6kBQKUB78 1wJ3sVU8WPX1mzdTg/tX0jV2twVPn3Ww1mtIMO9lI6k8w/6u5z8RU69JT9URsdiona8J 2AAnXY0FcIAf4KD6Gt/qjw7G0v+PM6LrizGQSTtKvq5qo4TFadpZbzXASS999BcV8Fm0 IQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3k06sjkrkx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 09:08:03 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 295982tX021829 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 5 Oct 2022 09:08:02 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 5 Oct 2022 02:07:57 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , Stephen Boyd , Dmitry Baryshkov , Philipp Zabel Subject: [PATCH v7 6/6] arm64: dts: qcom: sc7280: Add Reset support for gpu Date: Wed, 5 Oct 2022 14:37:04 +0530 Message-ID: <20221005143618.v7.6.I6a1fca5d53c886c05ea3e24cd4282d31c9c0cd0b@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> References: <1664960824-20951-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Mav_tV04SwmxJ7L7HRA0Hy4wXhJxxjxB X-Proofpoint-GUID: Mav_tV04SwmxJ7L7HRA0Hy4wXhJxxjxB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-04_09,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 phishscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210050057 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Akhil P Oommen , Konrad Dybcio , Douglas Anderson , Rob Herring , linux-kernel@vger.kernel.org, krzysztof.kozlowski@linaro.org, Andy Gross , Krzysztof Kozlowski Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for Reset using GPUCC driver for GPU. This helps to ensure that GPU state is reset by making sure that CX head switch is collapsed. Signed-off-by: Akhil P Oommen --- (no changes since v1) arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 2125803..3e559b3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2535,6 +2535,9 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + resets = <&gpucc GPU_CX_COLLAPSE>; + reset-names = "cx_collapse"; + gpu_opp_table: opp-table { compatible = "operating-points-v2";