From patchwork Tue Oct 11 18:42:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13004249 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5386CC433F5 for ; Tue, 11 Oct 2022 18:42:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229838AbiJKSmR (ORCPT ); Tue, 11 Oct 2022 14:42:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229778AbiJKSmQ (ORCPT ); Tue, 11 Oct 2022 14:42:16 -0400 Received: from mail-qk1-x72b.google.com (mail-qk1-x72b.google.com [IPv6:2607:f8b0:4864:20::72b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27EA87F13D; Tue, 11 Oct 2022 11:42:16 -0700 (PDT) Received: by mail-qk1-x72b.google.com with SMTP id o2so1883480qkk.10; Tue, 11 Oct 2022 11:42:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=VS2GXG21DjRdeQjnmza5VEtpvDq1HC+087/4J2zXY70=; b=kIkrDBQ649U2RhFRoxOmCqKmWosJ2Ya9xlSmG2NtSdMT3UM92ZKefI1r2Cfqec69Fb i0H8dvUKeDZmxx+kB8/kXIPJ9U7da18cXsq2PnSsQNMTmetDy+gD+N+GjWYhz0dhWIMz ycBtLQVh4RfCPGWwwbWAbVAF+7QfwEtiejNgtuabQU6ColpwLbXSQAk/9zFN46aYY4+F 8p/7fnoOSLEK47Muc8DjH5qam7YY44lBmsMNNEqWXQ5//TE+lwTK7gWFegK69LZJWv8v QNM4nTj7OtA4vZC9MHnElaE100dG/0R0ixMl479xEx9Yw+lQ4eyEAYPL4OpTHzZq3EQr 1kfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=VS2GXG21DjRdeQjnmza5VEtpvDq1HC+087/4J2zXY70=; b=UBstajXbKsTPxwPD42RlkHZvezQCqHUHFaGooJ9B6kRiUNSgZ2pSWsmWSXnyEIEcDO pZhKGDtWUaywtJHZn5ErVDSuHHfwHQliykkGUzwCtIIG25XrXcCUU2g7wLKZYgegDyuO pvpWFagShMkiwSJDo03JeRV2jqtzxWYlaeP7uDrIgcE8XWgR63y36ouw4raHpRQ+Gjo4 h07kAIGbTTQvDVaB+W/R/jc9US28Q9lvXYnbG8O6ZJtW6MDO09tVAJXKELBUPMxx4syu qizkl9904EIDdi8dX5bqmcJ1U9U5Qk9c4/hp8ls9gv9EW2lykRVinRLFyw7CBHSBpFf3 Y5vw== X-Gm-Message-State: ACrzQf1uclqC/0WYEMjjatmw+/Irw2sqbxdWE7ZxhPEwaNg/YQiiXBIM XKqfAhbMwN+A/t7A6bfSS/1FYRHZHm4= X-Google-Smtp-Source: AMsMyM53rDZRF8GSDj2tWNygq39EPCcGobdIWvrgxjFSBGYyZVwV0M5jHCi6Y28pLL6YgxnDaTLfEA== X-Received: by 2002:a05:620a:25d0:b0:6bb:f597:1a3 with SMTP id y16-20020a05620a25d000b006bbf59701a3mr17401628qko.43.1665513735071; Tue, 11 Oct 2022 11:42:15 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id fc8-20020a05622a488800b003938a65479bsm10961732qtb.10.2022.10.11.11.42.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 11:42:14 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 1/5] PCI: brcmstb: Enable Multi-MSI Date: Tue, 11 Oct 2022 14:42:06 -0400 Message-Id: <20221011184211.18128-2-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011184211.18128-1-jim2101024@gmail.com> References: <20221011184211.18128-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org We always wanted to enable Multi-MSI but didn't have a test device until recently. In addition, there are some devices out there that will ask for multiple MSI but refuse to work if they are only granted one. Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 521acd632f1a..a45ce7d61847 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -445,7 +445,8 @@ static struct irq_chip brcm_msi_irq_chip = { static struct msi_domain_info brcm_msi_domain_info = { /* Multi MSI is supported by the controller, but not by this driver */ - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_MULTI_PCI_MSI), .chip = &brcm_msi_irq_chip, }; @@ -505,21 +506,23 @@ static struct irq_chip brcm_msi_bottom_irq_chip = { .irq_ack = brcm_msi_ack_irq, }; -static int brcm_msi_alloc(struct brcm_msi *msi) +static int brcm_msi_alloc(struct brcm_msi *msi, unsigned int nr_irqs) { int hwirq; mutex_lock(&msi->lock); - hwirq = bitmap_find_free_region(msi->used, msi->nr, 0); + hwirq = bitmap_find_free_region(msi->used, msi->nr, + order_base_2(nr_irqs)); mutex_unlock(&msi->lock); return hwirq; } -static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq) +static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq, + unsigned int nr_irqs) { mutex_lock(&msi->lock); - bitmap_release_region(msi->used, hwirq, 0); + bitmap_release_region(msi->used, hwirq, order_base_2(nr_irqs)); mutex_unlock(&msi->lock); } @@ -527,16 +530,17 @@ static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *args) { struct brcm_msi *msi = domain->host_data; - int hwirq; + int hwirq, i; - hwirq = brcm_msi_alloc(msi); + hwirq = brcm_msi_alloc(msi, nr_irqs); if (hwirq < 0) return hwirq; - irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq, - &brcm_msi_bottom_irq_chip, domain->host_data, - handle_edge_irq, NULL, NULL); + for (i = 0; i < nr_irqs; i++) + irq_domain_set_info(domain, virq + i, hwirq + i, + &brcm_msi_bottom_irq_chip, domain->host_data, + handle_edge_irq, NULL, NULL); return 0; } @@ -546,7 +550,7 @@ static void brcm_irq_domain_free(struct irq_domain *domain, struct irq_data *d = irq_domain_get_irq_data(domain, virq); struct brcm_msi *msi = irq_data_get_irq_chip_data(d); - brcm_msi_free(msi, d->hwirq); + brcm_msi_free(msi, d->hwirq, nr_irqs); } static const struct irq_domain_ops msi_domain_ops = { From patchwork Tue Oct 11 18:42:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13004250 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71D46C433FE for ; Tue, 11 Oct 2022 18:42:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229847AbiJKSmU (ORCPT ); Tue, 11 Oct 2022 14:42:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229843AbiJKSmS (ORCPT ); Tue, 11 Oct 2022 14:42:18 -0400 Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC7EF7F099; Tue, 11 Oct 2022 11:42:17 -0700 (PDT) Received: by mail-qk1-x734.google.com with SMTP id 8so1622376qka.1; Tue, 11 Oct 2022 11:42:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=ZtG62yJbqIS8I6QUrG+przRY/17aM7QpmVb3R+LpRSg=; b=e2UxZkjdHT1/gH9KPu5K9mIPgqAyJ+P/9Q3AnM2oh7crO1Pgm4GlT8rINymylRbreu XAfbmh8brx1W5NZfau9uVaqUHOWAUEI8XR1etIHH+h23ZeEnjXXBc0xXhRXqF6AlNsGr 1+phwmIjU9gG0h/jwO1Y7RKIIoNzlga2sEKX87DdpkJle7dvQUcEqWuflF05fvWEvQot eWKVgv8toCT1Tz3qgwmQNj6wByo0Or7aw3jzCLcVqmxudf9D+SffB5XHWx2lOCpQ2ouU m1iYsrmOA+LnkkyGZiySuCzsgfGVmbcLYqCZ4gcFVPo14Pw6S+echD7eU9iLGs8ehoSo QUvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ZtG62yJbqIS8I6QUrG+przRY/17aM7QpmVb3R+LpRSg=; b=PxL+EtDUefZnCDcsYnN/XZC8X0sADDU6rwa97Y8Csquch2x0IBuz3L7MKu6nrEnE59 giGtClTUX5eEJ8JXLn8xgbXdIjud5zrNNdlt+ntfhoAgoQ4uNJgO2xzmZWF+zqC8c2tN SdW6GBPziS9nTERg+pLio6M5GCdTc4EvQ48zjK/HzjrE+sDuwPac0B9j1FoJAe6volfT RzExmcOpj5cZ9fGuXIuGvyby9l5GBseoW+sCws42wCog3a6AH4lh1Mw7JmPNO6PrRJct WY6taPo/uBPr8BZ73CkweCZ9ueKcySOvUCmqya22c4DqbMSIVA8f6cLehyOPTAUKP2i/ Z4zw== X-Gm-Message-State: ACrzQf1LNFvNqLdEVrZV6x+epSWX8WFh8T75Yzn2433jxdcZHWjn9OUY j51t22syARvbGdHofbPUp5blSGtG1FM= X-Google-Smtp-Source: AMsMyM5O7zbQttUz+a7lUjKpe6+4O68+pvNdZSPYmodxGpzocDWp7GUPiIVxzDTOzwDMl5+XVATp0w== X-Received: by 2002:a05:620a:530a:b0:6df:b743:9671 with SMTP id oo10-20020a05620a530a00b006dfb7439671mr17009906qkn.762.1665513736435; Tue, 11 Oct 2022 11:42:16 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id fc8-20020a05622a488800b003938a65479bsm10961732qtb.10.2022.10.11.11.42.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 11:42:15 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 2/5] PCI: brcmstb: Wait for 100ms following PERST# deassert Date: Tue, 11 Oct 2022 14:42:07 -0400 Message-Id: <20221011184211.18128-3-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011184211.18128-1-jim2101024@gmail.com> References: <20221011184211.18128-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Be prudent and give some time for power and clocks to become stable. As described in the PCIe CEM specification sections 2.2 and 2.2.1; as well as PCIe r5.0, 6.6.1. Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index a45ce7d61847..39b545713ba0 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1037,8 +1037,15 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) pcie->perst_set(pcie, 0); /* - * Give the RC/EP time to wake up, before trying to configure RC. - * Intermittently check status for link-up, up to a total of 100ms. + * Wait for 100ms after PERST# deassertion; see PCIe CEM specification + * sections 2.2, PCIe r5.0, 6.6.1. + */ + msleep(100); + + /* + * Give the RC/EP even more time to wake up, before trying to + * configure RC. Intermittently check status for link-up, up to a + * total of 100ms. */ for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) msleep(5); From patchwork Tue Oct 11 18:42:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13004251 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88C47C433FE for ; Tue, 11 Oct 2022 18:42:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229866AbiJKSmY (ORCPT ); Tue, 11 Oct 2022 14:42:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229867AbiJKSmV (ORCPT ); Tue, 11 Oct 2022 14:42:21 -0400 Received: from mail-qk1-x72c.google.com (mail-qk1-x72c.google.com [IPv6:2607:f8b0:4864:20::72c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7501780EBC; Tue, 11 Oct 2022 11:42:19 -0700 (PDT) Received: by mail-qk1-x72c.google.com with SMTP id m6so3984324qkm.4; Tue, 11 Oct 2022 11:42:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=yC68PwSujcmdozdXRLObvH5ia1utZiSGZZx8tkWQRwM=; b=BM856Tof1maVbKADbUoeep+v/Kh8Xs4qIGjPkd1Sxt3W/8Y6ieF7VVHMspdh6BFj6G iXG0PCB0OrR+maaj9i05cbmgMrUiZ2Yv2KMwekF2Xr7SwJ5Xu5raHGepeHyp3GCCYAiZ PWgBi8HaDT6cWz1658v8xfGY8Yw//RrgNDoOwgB5eTmtFhNiN91sht2mLWf1qJ6CNpOy daMwLlGgcLOAw6XYIgAZZ+bdCx0AruOla8hAtt/N/HLDEEzgvtt58sv1osYo5Jr2k04o C9MHMrsCz4sa5JnMTMiDonVFbcyD/IdAgZGUBbqxwwMljnoY1n6cUvkpvp6ZEZb1uXmz 1Dqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=yC68PwSujcmdozdXRLObvH5ia1utZiSGZZx8tkWQRwM=; b=W3ch532dbW7gvOat49fUBvAaMocoXh13fwPRSMOrNeAqqx10XR9q3Qb0EVUZ5bU+s9 6gu0zVBf+XZmuRHsy5PEl1ebvCqWyLZktQOygaofFDpbT4+rc0pn7j4IPIZusel5Vgje aZ+eOpVApWdWKeB2qcQklLADuRWDbDeXG3pRPYC2OVTLmalcypGHHvU1PNGgrnrUpjQ1 VtWwJWAjEPh0/MJ0QprwAwyzTrU7Le1y8nqWgaWMgUYq6y5I3twuUI/xapnoq0Lf8VAF zGohM1Nh4LpPMJ6W19qKNMMHu5Bv48YoYpR27HE+rfPEws4mtnMOVDJpPoeL/FI/n1cd DcVQ== X-Gm-Message-State: ACrzQf0p4+WOTU2SquNikBtYneK3ygLpAKBFodYthcePXcDmusRxqVAk TUY0mybqmZ4CT3R4x1uq1xU5u8gUqYY= X-Google-Smtp-Source: AMsMyM4Vf6sWyq8Gx07MlfotRqmjQhuQIEe0h6hqEI4mPD99OXt3GmtehfAZuvdtbMJqLkVQo7HZWw== X-Received: by 2002:a05:620a:12fb:b0:6ee:79f2:3716 with SMTP id f27-20020a05620a12fb00b006ee79f23716mr3676940qkl.348.1665513738030; Tue, 11 Oct 2022 11:42:18 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id fc8-20020a05622a488800b003938a65479bsm10961732qtb.10.2022.10.11.11.42.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 11:42:17 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 3/5] PCI: brcmstb: Replace status loops with read_poll_timeout_atomic() Date: Tue, 11 Oct 2022 14:42:08 -0400 Message-Id: <20221011184211.18128-4-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011184211.18128-1-jim2101024@gmail.com> References: <20221011184211.18128-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org It would be nice to replace the PCIe link-up loop as well but there are too many uses of this that do not poll (and the read_poll_timeout uses "timeout==0" to loop forever). Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 39b545713ba0..c7210cec1f58 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -302,42 +303,34 @@ static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd) /* negative return value indicates error */ static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val) { - int tries; u32 data; + int err; writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ), base + PCIE_RC_DL_MDIO_ADDR); readl(base + PCIE_RC_DL_MDIO_ADDR); - - data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); - for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) { - udelay(10); - data = readl(base + PCIE_RC_DL_MDIO_RD_DATA); - } - + err = readl_poll_timeout_atomic(base + PCIE_RC_DL_MDIO_RD_DATA, data, + MDIO_RD_DONE(data), 10, 100); *val = FIELD_GET(MDIO_DATA_MASK, data); - return MDIO_RD_DONE(data) ? 0 : -EIO; + + return err; } /* negative return value indicates error */ static int brcm_pcie_mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata) { - int tries; u32 data; + int err; writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE), base + PCIE_RC_DL_MDIO_ADDR); readl(base + PCIE_RC_DL_MDIO_ADDR); writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA); - data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); - for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) { - udelay(10); - data = readl(base + PCIE_RC_DL_MDIO_WR_DATA); - } - - return MDIO_WT_DONE(data) ? 0 : -EIO; + err = readw_poll_timeout_atomic(base + PCIE_RC_DL_MDIO_WR_DATA, data, + MDIO_WT_DONE(data), 10, 100); + return err; } /* From patchwork Tue Oct 11 18:42:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13004252 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 368E5C433FE for ; Tue, 11 Oct 2022 18:42:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229917AbiJKSmd (ORCPT ); Tue, 11 Oct 2022 14:42:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229880AbiJKSmW (ORCPT ); Tue, 11 Oct 2022 14:42:22 -0400 Received: from mail-qt1-x82d.google.com (mail-qt1-x82d.google.com [IPv6:2607:f8b0:4864:20::82d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F5617CB48; Tue, 11 Oct 2022 11:42:21 -0700 (PDT) Received: by mail-qt1-x82d.google.com with SMTP id r19so623140qtx.6; Tue, 11 Oct 2022 11:42:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=jC9v6x5O9g4o36lTWYhNYvUXqkkWlvK03fmUWelD46Y=; b=QJXGNK69c45gXxMdpzsU32P1osw4qt8d4ezCrzK7p+V9A9LWM7zYJYKdkJi4RCVhU/ xlprNjlA0EEFoHkTc98wUvsr0TGnRoDMxZEQNJ/2AVBdNKFGpAKU6W1udWq4eeNdpFpj 3qLuT1Xli21zAtRxMdp8YsiAtmUKH5nPqzUL8MpDKW4sFAT+30a2U3pzok4z9qJGHjzk Lkh/5rsq73Ib6fXEJfZboA1ADYW8kK4sdtBUb1F3qYC8vqmiys/xoge+3oX4Eo0/beDF Sg+1iuecagwXvBNWP+pfASw79MbYknWYbyaFHSgHDDdB6bimib1Ir8YC2509qr+R4PaE 8x3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=jC9v6x5O9g4o36lTWYhNYvUXqkkWlvK03fmUWelD46Y=; b=x+i03wfxTVLadnNXxVBrvOU6f0Q25OC+G1K+skZriv+jIxTTA3AJUY2+hWivxPFZuo LbHRpxRubw9RYt6vBBT+rtcQH4bO+QY+jBslEHjjTbMR4Xx3yeUuGT2SB5wJ1uknxMzg X0Af4Y7rFuHP8CypQpghgULMX6WMuHMRgysiIseaczE9a4JB0irxBfelqNij+s/gjwe/ UJDdbLts6kwZlNqFtmGsMyJY2aXVatpGm+7R1sX6bp1ODMp/HisnWZ2BlS3GRFqmylYe SKYbqON/YuP1Cdln29FuzUWe8xQ6ETqYHcwp7AWx9NDAD9SYbtrOHXHyRVIHbNfxYtwV RwZQ== X-Gm-Message-State: ACrzQf1BTH0a0sOgpXviH1tXFzUqaUX760AiwTtHCfYYjo1so5CrkE84 ctsXtMNvu4p24yL0CU7jy+9LWIPqBDM= X-Google-Smtp-Source: AMsMyM7LATMcDiFcvI+0/DRZQnhodXci0t2uK77a9y8u6aghVCj0Oo0ASbgemMCgyldZFJrJqqrrHw== X-Received: by 2002:ac8:5751:0:b0:39c:b848:198f with SMTP id 17-20020ac85751000000b0039cb848198fmr2170312qtx.429.1665513739432; Tue, 11 Oct 2022 11:42:19 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id fc8-20020a05622a488800b003938a65479bsm10961732qtb.10.2022.10.11.11.42.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 11:42:18 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 4/5] PCI: brcmstb: Functions needlessly specified as "inline" Date: Tue, 11 Oct 2022 14:42:09 -0400 Message-Id: <20221011184211.18128-5-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011184211.18128-1-jim2101024@gmail.com> References: <20221011184211.18128-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org A number of inline functions are called rarely and/or are not time-critical. Take out the "inline" and let the compiler do its work. Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli Reviewed-by: Bjorn Helgaas --- drivers/pci/controller/pcie-brcmstb.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index c7210cec1f58..e3045f1eadbc 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -723,7 +723,7 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus, return base + DATA_ADDR(pcie); } -static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) +static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) { u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK; u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT; @@ -733,7 +733,7 @@ static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); } -static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) +static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) { u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK; u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT; @@ -743,7 +743,7 @@ static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); } -static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) +static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) { if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) return; @@ -754,7 +754,7 @@ static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) reset_control_deassert(pcie->perst_reset); } -static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) +static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) { u32 tmp; @@ -764,7 +764,7 @@ static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); } -static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) +static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) { u32 tmp; @@ -773,7 +773,7 @@ static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); } -static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, +static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, u64 *rc_bar2_size, u64 *rc_bar2_offset) { From patchwork Tue Oct 11 18:42:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13004253 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DA81C433F5 for ; Tue, 11 Oct 2022 18:42:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229921AbiJKSme (ORCPT ); Tue, 11 Oct 2022 14:42:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229852AbiJKSmX (ORCPT ); Tue, 11 Oct 2022 14:42:23 -0400 Received: from mail-qv1-xf2c.google.com (mail-qv1-xf2c.google.com [IPv6:2607:f8b0:4864:20::f2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1551E8285E; Tue, 11 Oct 2022 11:42:22 -0700 (PDT) Received: by mail-qv1-xf2c.google.com with SMTP id g9so9497144qvo.12; Tue, 11 Oct 2022 11:42:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=EpuVq5iO2zl1W3X3kc36q+RPKt7tweIdU1vHs5t+3eg=; b=Gj5Nqr+LDbbfdcwkpISaFWC3XdZGLsNhMyp9yQ7I2jPcpQFr3j9ML16AFN5gJP5fqd BggKYoQCVRge/F/uQcDXmxPixlp26y/RiwefonggUi8wI5Tlwj9BOqncJN50vyboUfsG e1KfLU7BdpAPHtq7FjP0mMGBepXyaQm3kwLTR2uAqZn0I/OboA/lrzEZJh+vYUoBmKj4 FoOnn8aDImOV0axl6bToLeNcYB88xFfEQfErGYk5v0Hq7aRZ0/L7CfN1yJtl2G6pIo1X yM5JxaruyYzUbEp8e/GyPnWxEHcvIzLSnOuA99XIpnKk3U32vJyhVpxYqW4undxRX6Ip 8REw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=EpuVq5iO2zl1W3X3kc36q+RPKt7tweIdU1vHs5t+3eg=; b=hRSGcfagrpAe3/N9VvOg80ElYyBqpIEDfI3sBRyTYiA7QJyIjqeLTbqlvToh+Jb4wc hTFO8O9BMEsa9RahUcqF1f/8SascYaai7guPP4leJUE75TkU8i1rgMA+TruqvAflf/kR evtlakjc56j35v0oMtxYcrZS9DgpXlkLqoTlP83cWqI2eERKTxcsMcT35kHIGw5DgqDo rnkaJtt4ZtUR5F75AtGuTiSr9dVBPPdM5DBimsncj7g9VufF26UTuqmn6VcoHgxiQp8X 0HwOwEd6a120uM8xdY6jnbw9CZYWbaA+gwkZDapDk3EiYOIOMg7xATdX6jSz6BPK97IX JTvQ== X-Gm-Message-State: ACrzQf3ZtH4hcMT0YJ48m1oFVd7gNUnJ1TlXw+rURFRl13B6PhXDfBe1 9xNz7XOhWIcEsAFt3gWY7TPBtkXlUIo= X-Google-Smtp-Source: AMsMyM4cEoY8/pxM0W8zIScP7/MI6kym/0Bnwf2jYpcX+HtPFjAmBxPBvLmmdBInV4CuI83G8h7/kg== X-Received: by 2002:a05:6214:2aaa:b0:4b1:8f0b:97ac with SMTP id js10-20020a0562142aaa00b004b18f0b97acmr20181393qvb.84.1665513740738; Tue, 11 Oct 2022 11:42:20 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id fc8-20020a05622a488800b003938a65479bsm10961732qtb.10.2022.10.11.11.42.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 11:42:20 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 5/5] PCI: brcmstb: Set RCB_{MPS,64B}_MODE bits Date: Tue, 11 Oct 2022 14:42:10 -0400 Message-Id: <20221011184211.18128-6-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011184211.18128-1-jim2101024@gmail.com> References: <20221011184211.18128-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Set RCB_MPS mode bit so that data for PCIe read requests up to the size of the Maximum Payload Size (MPS) are returned in one completion, and data for PCIe read requests greater than the MPS are split at the specified Read Completion Boundary setting. Set RCB_64B so that the Read Compeletion Boundary is 64B. Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index e3045f1eadbc..edf283e2b5dd 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -53,6 +53,8 @@ #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 #define PCIE_MISC_MISC_CTRL 0x4008 +#define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80 +#define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000 @@ -900,11 +902,16 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) else burst = 0x2; /* 512 bytes */ - /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */ + /* + * Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN, + * RCB_MPS_MODE, RCB_64B_MODE + */ tmp = readl(base + PCIE_MISC_MISC_CTRL); u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK); u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK); u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK); + u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK); + u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK); writel(tmp, base + PCIE_MISC_MISC_CTRL); ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,