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Subject: [Patch v3 01/15] dt-bindings: media: s5p-mfc: Add new DT schema for MFC Date: Tue, 11 Oct 2022 17:55:02 +0530 Message-Id: <20221011122516.32135-2-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTe0zTVxTHd39tfy0a9Ac4vUNAUsMEDNDO0l1YwQ2Z+y1uSyfZXMQIpfxs GaXt2iLMZJuCgKIIuC1CB5RRGAHksdIyYDB5l6lgyJxNJuVVFh5bmLwcDqNrKWz/fe73fM89 5557L4vmPoF7spLkGkolF8nY+DZ6S2+Af9AwOirmFN0ToN9bixlooqwFR/q1GQyN65fpqKfZ xETG+9/QULW5i4F0fcMM9EP3FB19P2uPjhRb6WhG1wDQnHYMRwbbAwaanD+BfmkvwdHVJhMD 1fdZmajKMoKh7wxPMVRhWmGirM4+JrJ2tAB0MbsPex2SN8tuArLVWglIS+USjWzTWpmkvmMO Iw21l3Fy9EEHTjZXfkFm9f9DJ68ZawH5LKOUSeb2WXBy2eBD3l5dZgp3nEwWSClRIqXypeRi RWKSXBLBPhYTdyQulM/hBnHD0KtsX7kohYpgR78jDDqaJLOPge17ViRLtUtCkVrNDokUqBSp GspXqlBrItiUMlGm5CmD1aIUdapcEiynNOFcDueVULsxPll6rXsBKE1h6eX3apnnQUZALnBh QYIH+y/dALlgG8ud+BFAQ2MO07lYAnDIXI85XO7EYwBvLQm2MoZ1DZjT1AngotaGO01ZGCxY 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LBcnkYsIAV75WDRniU0aGrUsuykQfa7O4aOO/EoCaX/3YOijdghHpvIKEhne5vHQradGPiow N/NRVcMnHN3/+s++zrHhqKegDKDe3HYC6bta+aizbw968/AagS7cq+CjUrONRCWW1xi6qZ/A UFHFMInUdWYS2WorATpz1oythczd/LuAqbYVA8ZSbOcxD3JtJKOt7cUYvS6dYKyttQRTXnyC UTeO4UyGQQeYydPXSUZjthDMkH4O83xkiAx33ScIjmblsUdYbqn4oCAmo2EAxFesOlr4Skee BKd9NcCZgnQgbC4owzRAQAnpGgDbhsaIaTEb/jn7hJxmN3h7smeKhXQaBtVvQxxM0EvgoxIj 4QjPotUAWm6nTzXx6Dwc/s408jWAotzocFje5+YI4PQCONFlxR3sQofAkUsX8emBufDOPSPP wc60GP4seUJMj4XAU4NXsMvAtRA46YAnG69SyBSqgPiAODbJXyVRqBLjZP5RSoUeTH3n51sN qnQ//E0Ao4AJQIonmuUCCtZHCV2iJckpLKeM5BLlrMoEvClc5OHSonkWKaRlkgT2EMvGs9x/ i1HOXicxo/i9qW6RQhsaqVwM2vrrJ9Qr8sQan63nYGORcvMW1bVBY5jo0v4P0WPdwx6lYYFc Zu671EHteFDj47zjW86sWuvUtiH71pX2lvym0f7opHE23XvHnazelCO7L1+t8SqVWKuz/FZe d/+SuMs0kLbY7u8TUWY+WjI8LBBrug0D9U7bQqg9ReGu9esiTKKgjp0GakRtt6ctl0rHM3V7 rd6BGaNhskl3/rrtycHwpdsbbyn9nfv6q3Rivnymcl5nqNSz8oDFnn1e841jV1yYIW1LsrKu CxuOpaSeWxPKdRnUnEfhi4aNq9Xt3TmSbfmbzst+7VSkmW90Bfs2bz7MJstFuCpGEuDH41SS v4BPiMEqAwAA X-CMS-MailID: 20221011125142epcas5p13c858a5f27830fb1de50fa51e9730eca X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125142epcas5p13c858a5f27830fb1de50fa51e9730eca References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy Convert DT schema for s5p-mfc in yaml format Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- .../devicetree/bindings/media/s5p-mfc.txt | 75 -------- .../bindings/media/samsung,s5p-mfc.yaml | 163 ++++++++++++++++++ 2 files changed, 163 insertions(+), 75 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt index aa54c8159d9f..8b137891791f 100644 --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt @@ -1,76 +1 @@ -* Samsung Multi Format Codec (MFC) -Multi Format Codec (MFC) is the IP present in Samsung SoCs which -supports high resolution decoding and encoding functionalities. -The MFC device driver is a v4l2 driver which can encode/decode -video raw/elementary streams and has support for all popular -video codecs. - -Required properties: - - compatible : value should be either one among the following - (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs - (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs - (c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC - (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC - (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC - (f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : MFC interrupt number to the CPU. - - clocks : from common clock binding: handle to mfc clock. - - clock-names : from common clock binding: must contain "mfc", - corresponding to entry in the clocks property. - -Optional properties: - - power-domains : power-domain property defined with a phandle - to respective power domain. - - memory-region : from reserved memory binding: phandles to two reserved - memory regions, first is for "left" mfc memory bus interfaces, - second if for the "right" mfc memory bus, used when no SYSMMU - support is available; used only by MFC v5 present in Exynos4 SoCs - -Obsolete properties: - - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region - property instead - - -Example: -SoC specific DT entry: - -mfc: codec@13400000 { - compatible = "samsung,mfc-v5"; - reg = <0x13400000 0x10000>; - interrupts = <0 94 0>; - power-domains = <&pd_mfc>; - clocks = <&clock 273>; - clock-names = "mfc"; -}; - -Reserved memory specific DT entry for given board (see reserved memory binding -for more information): - -reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mfc_left: region@51000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x51000000 0x800000>; - }; - - mfc_right: region@43000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x43000000 0x800000>; - }; -}; - -Board specific DT entry: - -codec@13400000 { - memory-region = <&mfc_left>, <&mfc_right>; -}; diff --git a/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml new file mode 100644 index 000000000000..ad61b509846f --- /dev/null +++ b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Multi Format Codec (MFC) + +maintainers: + - Marek Szyprowski + - Smitha T Murthy + - Aakarsh Jain + +description: + Multi Format Codec (MFC) is the IP present in Samsung SoCs which + supports high resolution decoding and encoding functionalities. + +properties: + compatible: + enum: + - samsung,mfc-v5 # Exynos4 + - samsung,mfc-v6 # Exynos5 + - samsung,mfc-v7 # Exynos5420 + - samsung,mfc-v8 # Exynos5800 + - samsung,exynos5433-mfc # Exynos5433 + - samsung,mfc-v10 # Exynos7880 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + + interrupts: + maxItems: 1 + + iommus: + maxItems: 2 + + iommu-names: + maxItems: 2 + + power-domains: + maxItems: 1 + + memory-region: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,mfc-v6 + - samsung,mfc-v7 + - samsung,mfc-v8 + - tesla,fsd-mfc + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: mfc + + - if: + properties: + compatible: + contains: + enum: + - samsung,mfc-v5 + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: mfc + - const: sclk_mfc + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos5433-mfc + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: pclk + - const: aclk + - const: aclk_xiu + + - if: + properties: + compatible: + contains: + enum: + - samsung,mfc-v5 + - samsung,mfc-v6 + - samsung,mfc-v7 + - samsung,mfc-v8 + - samsung,exynos5433-mfc + + then: + properties: + iommus: + minItems: 2 + maxItems: 2 + iommu-names: + items: + - const: left + - const: right + + - if: + properties: + compatible: + contains: + enum: + - tesla,fsd-mfc + then: + properties: + memory-region: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + codec@13400000 { + compatible = "samsung,mfc-v5"; + reg = <0x13400000 0x10000>; + interrupts = ; + power-domains = <&pd_mfc>; + clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; + clock-names = "mfc", "sclk_mfc"; + iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; + iommu-names = "left", "right"; + + }; From patchwork Tue Oct 11 12:25:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aakarsh Jain X-Patchwork-Id: 13004610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20BB9C4332F for ; Wed, 12 Oct 2022 03:47:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229604AbiJLDrt (ORCPT ); Tue, 11 Oct 2022 23:47:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229586AbiJLDri (ORCPT ); Tue, 11 Oct 2022 23:47:38 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Oct 2022 12:51:45 +0000 (GMT) X-AuditID: b6c32a4a-007ff70000019a35-38-634638d20ea8 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 0A.0D.14392.1E665436; Tue, 11 Oct 2022 21:51:45 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125142epsmtip1a70854be8c175ac3ab0544709f0a685a~dBMnR6j1P2178621786epsmtip1q; Tue, 11 Oct 2022 12:51:41 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, 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Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml index ad61b509846f..9fb4cae1b68f 100644 --- a/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml +++ b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml @@ -24,6 +24,7 @@ properties: - samsung,mfc-v8 # Exynos5800 - samsung,exynos5433-mfc # Exynos5433 - samsung,mfc-v10 # Exynos7880 + - tesla,fsd-mfc # Tesla FSD reg: maxItems: 1 From patchwork Tue Oct 11 12:25:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aakarsh Jain X-Patchwork-Id: 13004611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96BD7C433FE for ; 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Tue, 11 Oct 2022 12:51:48 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20221011125148epsmtrp1d831b2610c551d6a40db53da27afd6ae~dBMtfYLSl2654526545epsmtrp1E; Tue, 11 Oct 2022 12:51:48 +0000 (GMT) X-AuditID: b6c32a4a-259fb70000019a35-4b-634638d8ac0c Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id AB.0D.14392.4E665436; Tue, 11 Oct 2022 21:51:48 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125145epsmtip130e4165128e4af80772d985220791620~dBMqdGuN62344423444epsmtip1X; Tue, 11 Oct 2022 12:51:45 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 03/15] media: s5p-mfc: Rename IS_MFCV10 macro Date: Tue, 11 Oct 2022 17:55:04 +0530 Message-Id: <20221011122516.32135-4-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTfVBUVRjGO/fu3l0g9Ipixy1xuw0WJLiLCx4cvgpx7khjVDM17sTQnd0b EMvutnchokmRhMkVJEomvr8WaEQFXL4/FIINHLNmNg0adFkQCEErAjIM1HZZqP9+7/M+zzlz 3nOOEPcYI0TCRLWe1akZFUW48toGfHz8fkGHFBJLw3Y03VHER+PlbQQyLs9gyGZc5KH+5lYB arlZgqNvhvr4qML8Ix+1f3uHhy7dtXctRVYemqloAGi2eIxApslhPpqYewfd6ColUE5TKx9d NFsFqHbEgqE60yqGqluXBCjrslmArD1tAJ3MNmMRkL5QfgHQHdYaQI/ULOB0Z7FVQBt7ZjHa VH+KoG8P9xB0c81xOuu7f3j0mZZ6QD/OLBPQBvMIQS+avOhrfy0KYjbJk0ISWEbJ6sSsWqFR JqrjQ6not+Ii4wKDJFI/aTDaT4nVTDIbSh18LcbvUKLKPgZKnMqoUuxSDMNx1N6wEJ0mRc+K EzScPpRitUqVVqb155hkLkUd769m9QekEklAoN34XlLCcHkvpp06kDb0aJGfAb6XGoBQCEkZ vLLsagAuQg+yG8AVW4gBuNp5AUBTp43vLB4A2DG6CjYCt+qOOvXLANY2zmHOIguDts5K3LEU QfrB3to+wsHbyBMATn6ud5hw8jMetF5fETgaW8kImNdUvhbgkd4wZ+7WGruTobBgYX7NA8ld 8HxT35ruQobBP2sHCcdCkDztAtutVYTTdBBezfkJd/JWODfUsh4Wwdm87HVWwMnq2XWPCjb2 nOU5ORz23SzlOY6Gkz6wsWuvU94JC641YA7GyU0wd2UKc+rusKN8g3fD0tvLfCc/BwfO1wIn 0/Be/zjfOdN8ADO+ivwCeBX/v0MlAPVgB6vlkuNZLlAboGY/+u/OFJpkE1h76L6HO8DE+Lx/ P8CEoB9AIU5tcwcVryo83JXMx+msThOnS1GxXD8ItM8vHxd5KjT2n6LWx0llwRJZUFCQLHhf kJR6xt1Y6KvwIOMZPZvEslpWt5HDhC6iDKxg85szqcouo9zycmXGGzXd42fpX1cbPuA+aQ+L 3Nye6yXeWXip+krz/NEPqd60Z5lw1Nry1LGydyt+M+SGlwoa1MY/FlLzJ/Tp1x80HRu98QQW pv+cye0o2iLPnqbhuSOe5wg/A7f8w2DT3/eTzdhSo1bp7UXJ3Q7vTrs6d4R5W/RSneWi5yvR j8owc3NV8Z4+7UmbdfpEVNFS1dc2udionLF07r+7Pfb0fezJ2OipOM99sTq+7Mukcfnv3sJV N/3r0VNRj+/V5VXWDWQz3VtkoST2wpmHJZHaTLfhPRG7jj988X2s7XnenacHcREKDsksjU0r CQ8QRU34SKotuoqJTykel8BIfXEdx/wL+XohFnEEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBIsWRmVeSWpSXmKPExsWy7bCSnO6TNNdkg0WP1Cye7pjJavFg3jY2 i8U/njNZ3F/8mcXi0Oat7BZbrsxmtlh+/ACrxfwj51gtth98xGKx8QVQ9uLMuywWz+evY7R4 Oesem8Wmx9dYLR6+Cre4vGsOm0XPhq2sFmuP3GW3WHr9IpPFsk1/mCwWbf3CbtG69wi7xd09 2xgtWtqOMDlIeKyZt4bRY8fdJYwe15d8YvbYOesuu8fiPS+ZPDat6mTzuHNtD5vH5iX1Hq1H f7F49G1Zxejxr2kuu0fXketsHp83yXmc+vqZPYAvissmJTUnsyy1SN8ugSvj2rz9TAVPrCqO //3M2sB42rCLkYNDQsBE4vayyC5GLg4hgd2MEi/P3mLsYuQEistI/G87xg5hC0us/PecHaKo mUni3I3tLCAJNgFdif1LD7CBJEQEWhklrq/sZAJxmAVms0j8mHSAFaRKWMBBon/DPGYQm0VA VaLn1W0wm1fAVmLqpw9QK+QlVm84ABbnFLCT+Lj0GBuILQRU0/h+KtMERr4FjAyrGCVTC4pz 03OLDQsM81LL9YoTc4tL89L1kvNzNzGCI09Lcwfj9lUf9A4xMnEwHmKU4GBWEuFlnO+ULMSb klhZlVqUH19UmpNafIhRmoNFSZz3QtfJeCGB9MSS1OzU1ILUIpgsEwenVAOTgKgw74PFcqsu ldiUve1ku+wlm6Saddm9KN7/7Nl9kw7VfvrvdHfXyZMvHP+t55mwXLha+IfktF2qsz9VrfEs annVsfJKRk6KbeiOx+bNvN/uu5/8w1Kx4c77vEnNE5Wzzn7rKHA7/frc1CvFP69PETJaNbuC o8ursiRdVDz4P0uAQ0nMIoPtGZn7Lwc4GW0qfbPo9WT5H482NOl+CmKv4H8mFnyRqWdmCbv6 o4bzzcxsXTy3t81ui45vdrp8MekuO/OxncqHbU8Yn7Nm8v27YMHL5+Uxs20PvLqh7XBuWtMi T/67H3/U7SvvlrMonL34KbfDrzNerDkmcRdrO28I58T51zVNZJY97CZ14OdBJZbijERDLeai 4kQAQhLBvSsDAAA= X-CMS-MailID: 20221011125148epcas5p10f1788595398637dbceebe1c4dbf0df2 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125148epcas5p10f1788595398637dbceebe1c4dbf0df2 References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy Renames macro IS_MFCV10 to IS_MFCV10_PLUS so that the MFCv10 code can be resued for MFCv12 support. Since some part of MFCv10 specific code holds good for MFCv12 also. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- .../platform/samsung/s5p-mfc/s5p_mfc_common.h | 10 +++---- .../platform/samsung/s5p-mfc/s5p_mfc_ctrl.c | 2 +- .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 28 +++++++++---------- 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h index 5304f42c8c72..e6ec4a43b290 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h @@ -771,11 +771,11 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq); #define HAS_PORTNUM(dev) (dev ? (dev->variant ? \ (dev->variant->port_num ? 1 : 0) : 0) : 0) #define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0) -#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0) -#define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0) -#define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80 ? 1 : 0) -#define IS_MFCV10(dev) (dev->variant->version >= 0xA0 ? 1 : 0) -#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev)) +#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60) +#define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70) +#define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80) +#define IS_MFCV10_PLUS(dev) (dev->variant->version >= 0xA0) +#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10_PLUS(dev)) #define MFC_V5_BIT BIT(0) #define MFC_V6_BIT BIT(1) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c index 72d70984e99a..ffe9f7e79eca 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c @@ -236,7 +236,7 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev) else mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET); - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10); mfc_debug(2, "Will now wait for completion of firmware transfer\n"); diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c index 8227004f6746..728d255e65fc 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c @@ -72,9 +72,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->luma_size, ctx->chroma_size, ctx->mv_size); mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count); } else if (ctx->type == MFCINST_ENCODER) { - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) ctx->tmv_buffer_size = 0; - } else if (IS_MFCV8_PLUS(dev)) + else if (IS_MFCV8_PLUS(dev)) ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height), S5P_FIMV_TMV_BUFFER_ALIGN_V6); @@ -82,7 +82,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height), S5P_FIMV_TMV_BUFFER_ALIGN_V6); - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width); lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height); if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) { @@ -133,7 +133,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) switch (ctx->codec_mode) { case S5P_MFC_CODEC_H264_DEC: case S5P_MFC_CODEC_H264_MVC_DEC: - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_debug(2, "Use min scratch buffer size\n"); else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = @@ -152,7 +152,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) (ctx->mv_count * ctx->mv_size); break; case S5P_MFC_CODEC_MPEG4_DEC: - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_debug(2, "Use min scratch buffer size\n"); else if (IS_MFCV7_PLUS(dev)) { ctx->scratch_buf_size = @@ -172,7 +172,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) break; case S5P_MFC_CODEC_VC1RCV_DEC: case S5P_MFC_CODEC_VC1_DEC: - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_debug(2, "Use min scratch buffer size\n"); else ctx->scratch_buf_size = @@ -189,7 +189,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->bank2.size = 0; break; case S5P_MFC_CODEC_H263_DEC: - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_debug(2, "Use min scratch buffer size\n"); else ctx->scratch_buf_size = @@ -201,7 +201,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->bank1.size = ctx->scratch_buf_size; break; case S5P_MFC_CODEC_VP8_DEC: - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_debug(2, "Use min scratch buffer size\n"); else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = @@ -230,7 +230,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) DEC_VP9_STATIC_BUFFER_SIZE; break; case S5P_MFC_CODEC_H264_ENC: - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); ctx->me_buffer_size = ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16); @@ -254,7 +254,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) break; case S5P_MFC_CODEC_MPEG4_ENC: case S5P_MFC_CODEC_H263_ENC: - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); ctx->me_buffer_size = ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width, @@ -273,7 +273,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->bank2.size = 0; break; case S5P_MFC_CODEC_VP8_ENC: - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); ctx->me_buffer_size = ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height), @@ -452,7 +452,7 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx) if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) { - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width, ctx->img_height); } else { @@ -668,7 +668,7 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx) mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1); - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { /* start address of per buffer is aligned */ for (i = 0; i < ctx->pb_count; i++) { writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); @@ -2455,7 +2455,7 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev) R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8); R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8); - if (!IS_MFCV10(dev)) + if (!IS_MFCV10_PLUS(dev)) goto done; /* Initialize registers used in MFC v10 only. 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Gateway) with SMTP id 9E.84.18644.7E665436; Tue, 11 Oct 2022 21:51:52 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125148epsmtip184e73f6e1c42751e055122decc293f32~dBMtmSfeC2178621786epsmtip1r; Tue, 11 Oct 2022 12:51:48 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 04/15] media: s5p-mfc: Add initial support for MFCv12 Date: Tue, 11 Oct 2022 17:55:05 +0530 Message-Id: <20221011122516.32135-5-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTeVBTVxTG5773khechnmNtlwpRUy1UzIFE7ZeHECrlD6gCx07I60daCa8 EoaQZLK0inXKUhAYxYDaCkSgJGiHTQlbwKCAKbZ0UZaBTjGspRBqFwkWKw5tQqD97/ed8517 zpx7LwfnTbO9OWlyDaOSi2V89hai/ab/CwHjKEYivJ7lhebMZSw0VdnORoaH8xiaNDgI1NfS RqLWkQocXb7Vw0JV1h9YqKN3hkDNC87sYJmNQPNVTQDZyyfYyDQ7ykLTi4fRcJeejU5dbWOh RquNRLVjgxi6ZHqMoZq2ZRLldVtJZLO0A/RpvhXbD+mGygZAm21GQI8Zl3C6s9xG0gaLHaNN dYVs+u6ohU23GD+h8756RNDFrXWAXsu5SNJF1jE27TD50gMPHGSC57vpEVJGnMKo/Bi5RJGS Jk+N5McfSj6YHBomFAWIwtFLfD+5OIOJ5Ee/lhAQkyZzroHv96FYpnWGEsRqNX9PVIRKodUw flKFWhPJZ5QpMmWIMlAtzlBr5amBckazVyQUBoU6je+nS22nn1MWnARHO2uCs0CJsgh4cCAV Am1dy2QR2MLhUdcANBZPY26xBOBi/S+EWzgAXKvLZm+WPGqy4+5EF4BT3WaWW+RhcObcN6TL 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20221011125152epcas5p3a9966cfafa53928023a97143d5e3a7f0 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125152epcas5p3a9966cfafa53928023a97143d5e3a7f0 References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy Add support for MFCv12, with a new register file and necessary hw control, decoder, encoder and structural changes. Add luma dbp, chroma dpb and mv sizes for each codec as per the UM for MFCv12, along with appropriate alignment. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- .../platform/samsung/s5p-mfc/regs-mfc-v12.h | 50 +++++++++++ .../media/platform/samsung/s5p-mfc/s5p_mfc.c | 30 +++++++ .../platform/samsung/s5p-mfc/s5p_mfc_common.h | 15 +++- .../platform/samsung/s5p-mfc/s5p_mfc_ctrl.c | 2 +- .../platform/samsung/s5p-mfc/s5p_mfc_dec.c | 6 +- .../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 5 +- .../platform/samsung/s5p-mfc/s5p_mfc_opr.h | 8 +- .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 83 ++++++++++++++++--- .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h | 6 +- 9 files changed, 175 insertions(+), 30 deletions(-) create mode 100644 drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h new file mode 100644 index 000000000000..6c68a45082d0 --- /dev/null +++ b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Register definition file for Samsung MFC V12.x Interface (FIMV) driver + * + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + */ + +#ifndef _REGS_MFC_V12_H +#define _REGS_MFC_V12_H + +#include +#include "regs-mfc-v10.h" + +/* MFCv12 Context buffer sizes */ +#define MFC_CTX_BUF_SIZE_V12 (30 * SZ_1K) +#define MFC_H264_DEC_CTX_BUF_SIZE_V12 (2 * SZ_1M) +#define MFC_OTHER_DEC_CTX_BUF_SIZE_V12 (30 * SZ_1K) +#define MFC_H264_ENC_CTX_BUF_SIZE_V12 (100 * SZ_1K) +#define MFC_HEVC_ENC_CTX_BUF_SIZE_V12 (40 * SZ_1K) +#define MFC_OTHER_ENC_CTX_BUF_SIZE_V12 (25 * SZ_1K) + +/* MFCv12 variant defines */ +#define MAX_FW_SIZE_V12 (SZ_1M) +#define MAX_CPB_SIZE_V12 (7 * SZ_1M) +#define MFC_VERSION_V12 0xC0 +#define MFC_NUM_PORTS_V12 1 +#define S5P_FIMV_CODEC_VP9_ENC 27 + +/* Encoder buffer size for MFCv12 */ +#define ENC_V120_BASE_SIZE(x, y) \ + (((x + 3) * (y + 3) * 8) \ + + (((y * 64) + 2304) * (x + 7) / 8)) + +#define ENC_V120_H264_ME_SIZE(x, y) \ + ALIGN((ENC_V120_BASE_SIZE(x, y) \ + + (DIV_ROUND_UP(x * y, 64) * 32)), 256) + +#define ENC_V120_MPEG4_ME_SIZE(x, y) \ + ALIGN((ENC_V120_BASE_SIZE(x, y) \ + + (DIV_ROUND_UP(x * y, 128) * 16)), 256) + +#define ENC_V120_VP8_ME_SIZE(x, y) \ + ALIGN(ENC_V120_BASE_SIZE(x, y), 256) + +#define ENC_V120_HEVC_ME_SIZE(x, y) \ + ALIGN((((x + 3) * (y + 3) * 32) \ + + (((y * 128) + 2304) * (x + 3) / 4)), 256) + +#endif /*_REGS_MFC_V12_H*/ diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c index fca5c6405eec..fe07112f013f 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c @@ -775,6 +775,8 @@ static int s5p_mfc_open(struct file *file) INIT_LIST_HEAD(&ctx->dst_queue); ctx->src_queue_cnt = 0; ctx->dst_queue_cnt = 0; + ctx->is_422 = 0; + ctx->is_10bit = 0; /* Get context number */ ctx->num = 0; while (dev->ctx[ctx->num]) { @@ -1637,6 +1639,31 @@ static struct s5p_mfc_variant mfc_drvdata_v10 = { .fw_name[0] = "s5p-mfc-v10.fw", }; +static struct s5p_mfc_buf_size_v6 mfc_buf_size_v12 = { + .dev_ctx = MFC_CTX_BUF_SIZE_V12, + .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V12, + .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V12, + .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V12, + .hevc_enc_ctx = MFC_HEVC_ENC_CTX_BUF_SIZE_V12, + .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V12, +}; + +static struct s5p_mfc_buf_size buf_size_v12 = { + .fw = MAX_FW_SIZE_V12, + .cpb = MAX_CPB_SIZE_V12, + .priv = &mfc_buf_size_v12, +}; + +static struct s5p_mfc_variant mfc_drvdata_v12 = { + .version = MFC_VERSION_V12, + .version_bit = MFC_V12_BIT, + .port_num = MFC_NUM_PORTS_V12, + .buf_size = &buf_size_v12, + .fw_name[0] = "s5p-mfc-v12.fw", + .clk_names = {"mfc"}, + .num_clocks = 1, +}; + static const struct of_device_id exynos_mfc_match[] = { { .compatible = "samsung,mfc-v5", @@ -1656,6 +1683,9 @@ static const struct of_device_id exynos_mfc_match[] = { }, { .compatible = "samsung,mfc-v10", .data = &mfc_drvdata_v10, + }, { + .compatible = "tesla,fsd-mfc", + .data = &mfc_drvdata_v12, }, {}, }; diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h index e6ec4a43b290..dd2e9f7704ab 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h @@ -19,7 +19,7 @@ #include #include #include "regs-mfc.h" -#include "regs-mfc-v10.h" +#include "regs-mfc-v12.h" #define S5P_MFC_NAME "s5p-mfc" @@ -720,6 +720,8 @@ struct s5p_mfc_ctx { struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS]; struct v4l2_ctrl_handler ctrl_handler; size_t scratch_buf_size; + int is_10bit; + int is_422; }; /* @@ -775,6 +777,7 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq); #define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70) #define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80) #define IS_MFCV10_PLUS(dev) (dev->variant->version >= 0xA0) +#define IS_MFCV12(dev) (dev->variant->version >= 0xC0) #define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10_PLUS(dev)) #define MFC_V5_BIT BIT(0) @@ -782,11 +785,15 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq); #define MFC_V7_BIT BIT(2) #define MFC_V8_BIT BIT(3) #define MFC_V10_BIT BIT(5) +#define MFC_V12_BIT BIT(7) #define MFC_V5PLUS_BITS (MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \ - MFC_V8_BIT | MFC_V10_BIT) + MFC_V8_BIT | MFC_V10_BIT | MFC_V12_BIT) #define MFC_V6PLUS_BITS (MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \ - MFC_V10_BIT) -#define MFC_V7PLUS_BITS (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT) + MFC_V10_BIT | MFC_V12_BIT) +#define MFC_V7PLUS_BITS (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT | \ + MFC_V12_BIT) + +#define MFC_V10PLUS_BITS (MFC_V10_BIT | MFC_V12_BIT) #endif /* S5P_MFC_COMMON_H_ */ diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c index ffe9f7e79eca..877e5bceb75b 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c @@ -130,7 +130,7 @@ int s5p_mfc_reset(struct s5p_mfc_dev *dev) mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4)); /* check bus reset control before reset */ - if (dev->risc_on) + if (dev->risc_on && !IS_MFCV12(dev)) if (s5p_mfc_bus_reset(dev)) return -EIO; /* Reset diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c index 268ffe4da53c..e219cbcd86d5 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c @@ -146,7 +146,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_FIMV_CODEC_HEVC_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V10_BIT, + .versions = MFC_V10PLUS_BITS, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM, }, @@ -155,7 +155,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_FIMV_CODEC_VP9_DEC, .type = MFC_FMT_DEC, .num_planes = 1, - .versions = MFC_V10_BIT, + .versions = MFC_V10PLUS_BITS, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION, }, }; @@ -355,7 +355,7 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f) pix_mp->width = ctx->buf_width; pix_mp->height = ctx->buf_height; pix_mp->field = V4L2_FIELD_NONE; - pix_mp->num_planes = 2; + pix_mp->num_planes = ctx->dst_fmt->num_planes; /* Set pixelformat to the format in which MFC outputs the decoded frame */ pix_mp->pixelformat = ctx->dst_fmt->fourcc; diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c index b65e506665af..143d95fe2f89 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c @@ -92,7 +92,7 @@ static struct s5p_mfc_fmt formats[] = { .codec_mode = S5P_FIMV_CODEC_HEVC_ENC, .type = MFC_FMT_ENC, .num_planes = 1, - .versions = MFC_V10_BIT, + .versions = MFC_V10PLUS_BITS, }, }; @@ -1179,7 +1179,8 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx) if (FW_HAS_E_MIN_SCRATCH_BUF(dev)) { ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops, get_e_min_scratch_buf_size, dev); - ctx->bank1.size += ctx->scratch_buf_size; + if (!IS_MFCV12(dev)) + ctx->bank1.size += ctx->scratch_buf_size; } ctx->state = MFCINST_HEAD_PRODUCED; } diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h index b9831275f3ab..87ac56756a16 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h @@ -166,9 +166,9 @@ struct s5p_mfc_regs { void __iomem *d_decoded_third_addr;/* only v7 */ void __iomem *d_used_dpb_flag_upper;/* v7 and v8 */ void __iomem *d_used_dpb_flag_lower;/* v7 and v8 */ - void __iomem *d_min_scratch_buffer_size; /* v10 */ - void __iomem *d_static_buffer_addr; /* v10 */ - void __iomem *d_static_buffer_size; /* v10 */ + void __iomem *d_min_scratch_buffer_size; /* v10 and v12 */ + void __iomem *d_static_buffer_addr; /* v10 and v12 */ + void __iomem *d_static_buffer_size; /* v10 and v12 */ /* encoder registers */ void __iomem *e_frame_width; @@ -268,7 +268,7 @@ struct s5p_mfc_regs { void __iomem *e_vp8_hierarchical_qp_layer0;/* v7 and v8 */ void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */ void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */ - void __iomem *e_min_scratch_buffer_size; /* v10 */ + void __iomem *e_min_scratch_buffer_size; /* v10 and v12 */ void __iomem *e_num_t_layer; /* v10 */ void __iomem *e_hier_qp_layer0; /* v10 */ void __iomem *e_hier_bit_rate_layer0; /* v10 */ diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c index 728d255e65fc..5d14ccf8b4fe 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c @@ -60,12 +60,14 @@ static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx) static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) { struct s5p_mfc_dev *dev = ctx->dev; - unsigned int mb_width, mb_height; + unsigned int mb_width, mb_height, width64, height32; unsigned int lcu_width = 0, lcu_height = 0; int ret; mb_width = MB_WIDTH(ctx->img_width); mb_height = MB_HEIGHT(ctx->img_height); + width64 = ALIGN(ctx->img_width, 64); + height32 = ALIGN(ctx->img_height, 32); if (ctx->type == MFCINST_DECODER) { mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n", @@ -82,7 +84,44 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height), S5P_FIMV_TMV_BUFFER_ALIGN_V6); - if (IS_MFCV10_PLUS(dev)) { + if (IS_MFCV12(dev)) { + lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width); + lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height); + if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC && + ctx->is_10bit) { + ctx->luma_dpb_size = + width64 * height32 + + ALIGN(DIV_ROUND_UP(lcu_width * 32, 4), + 16) * height32 + 128; + if (ctx->is_422) + ctx->chroma_dpb_size = + ctx->luma_dpb_size; + else + ctx->chroma_dpb_size = + width64 * height32 / 2 + + ALIGN(DIV_ROUND_UP(lcu_width * + 32, 4), 16) * height32 / 2 + 128; + } else if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_ENC && + ctx->is_10bit) { + ctx->luma_dpb_size = + ALIGN(ctx->img_width * 2, 128) * + height32 + 64; + ctx->chroma_dpb_size = + ALIGN(ctx->img_width * 2, 128) * + height32 / 2 + 64; + } else { + ctx->luma_dpb_size = + width64 * height32 + 64; + if (ctx->is_422) + ctx->chroma_dpb_size = + ctx->luma_dpb_size; + else + ctx->chroma_dpb_size = + width64 * height32 / 2 + 64; + } + ctx->luma_dpb_size = ALIGN(ctx->luma_dpb_size + 256, SZ_2K); + ctx->chroma_dpb_size = ALIGN(ctx->chroma_dpb_size + 256, SZ_2K); + } else if (IS_MFCV10_PLUS(dev)) { lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width); lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height); if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) { @@ -230,7 +269,11 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) DEC_VP9_STATIC_BUFFER_SIZE; break; case S5P_MFC_CODEC_H264_ENC: - if (IS_MFCV10_PLUS(dev)) { + if (IS_MFCV12(dev)) { + mfc_debug(2, "Use min scratch buffer size\n"); + ctx->me_buffer_size = + ENC_V120_H264_ME_SIZE(mb_width, mb_height); + } else if (IS_MFCV10_PLUS(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); ctx->me_buffer_size = ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16); @@ -254,7 +297,11 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) break; case S5P_MFC_CODEC_MPEG4_ENC: case S5P_MFC_CODEC_H263_ENC: - if (IS_MFCV10_PLUS(dev)) { + if (IS_MFCV12(dev)) { + mfc_debug(2, "Use min scratch buffer size\n"); + ctx->me_buffer_size = + ENC_V120_MPEG4_ME_SIZE(mb_width, mb_height); + } else if (IS_MFCV10_PLUS(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); ctx->me_buffer_size = ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width, @@ -273,7 +320,11 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->bank2.size = 0; break; case S5P_MFC_CODEC_VP8_ENC: - if (IS_MFCV10_PLUS(dev)) { + if (IS_MFCV12(dev)) { + mfc_debug(2, "Use min scratch buffer size\n"); + ctx->me_buffer_size = + ENC_V120_VP8_ME_SIZE(mb_width, mb_height); + } else if (IS_MFCV10_PLUS(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); ctx->me_buffer_size = ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height), @@ -297,9 +348,14 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->bank2.size = 0; break; case S5P_MFC_CODEC_HEVC_ENC: + if (IS_MFCV12(dev)) + ctx->me_buffer_size = + ENC_V120_HEVC_ME_SIZE(lcu_width, lcu_height); + else + ctx->me_buffer_size = + ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, + lcu_height), 16); mfc_debug(2, "Use min scratch buffer size\n"); - ctx->me_buffer_size = - ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16); ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256); ctx->bank1.size = ctx->scratch_buf_size + ctx->tmv_buffer_size + @@ -452,12 +508,15 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx) if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) { - if (IS_MFCV10_PLUS(dev)) { - ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width, - ctx->img_height); + if (IS_MFCV12(dev)) { + ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, + ctx->img_height, 1024); + } else if (IS_MFCV10_PLUS(dev)) { + ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, + ctx->img_height, 512); } else { - ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width, - ctx->img_height); + ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, + ctx->img_height, 128); } } else if (ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) { ctx->mv_size = s5p_mfc_dec_hevc_mv_size(ctx->img_width, diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h index e4dd03c5454c..30269f3e68e8 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h @@ -19,10 +19,8 @@ #define MB_WIDTH(x_size) DIV_ROUND_UP(x_size, 16) #define MB_HEIGHT(y_size) DIV_ROUND_UP(y_size, 16) -#define S5P_MFC_DEC_MV_SIZE_V6(x, y) (MB_WIDTH(x) * \ - (((MB_HEIGHT(y)+1)/2)*2) * 64 + 128) -#define S5P_MFC_DEC_MV_SIZE_V10(x, y) (MB_WIDTH(x) * \ - (((MB_HEIGHT(y)+1)/2)*2) * 64 + 512) +#define S5P_MFC_DEC_MV_SIZE(x, y, offset) (MB_WIDTH(x) * \ + (((MB_HEIGHT(y)+1)/2)*2) * 64 + offset) #define S5P_MFC_LCU_WIDTH(x_size) DIV_ROUND_UP(x_size, 32) #define S5P_MFC_LCU_HEIGHT(y_size) DIV_ROUND_UP(y_size, 32) From patchwork Tue Oct 11 12:25:06 2022 Content-Type: text/plain; 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Wed, 12 Oct 2022 12:47:43 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20221011125155epcas5p1e47309b4dd767e81817c316aa0e8b7ca~dBMz2YuYK3098030980epcas5p1J; Tue, 11 Oct 2022 12:51:55 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20221011125155epsmtrp206f24d925e521a9ae8ce504b08b9f26b~dBMz1OKAT1820318203epsmtrp2_; Tue, 11 Oct 2022 12:51:55 +0000 (GMT) X-AuditID: b6c32a49-0c7ff70000016970-48-634638df547a Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id CD.0D.14392.BE665436; Tue, 11 Oct 2022 21:51:55 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125152epsmtip11fb87b5cc95cb155429249f50976d5a8~dBMwvzaTN2178621786epsmtip1s; Tue, 11 Oct 2022 12:51:52 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 05/15] Documention: v4l: Documentation for VP9 CIDs. Date: Tue, 11 Oct 2022 17:55:06 +0530 Message-Id: <20221011122516.32135-6-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTe1BUVRzHO/fevXdhBucGKEcmcOdO2kCw7sbDAwky5NgtGaGpsGya9bbc AWRf7C5mlAkqlgQqFcUriJc0IA+Xh5tC8ViglApEIdSFVWwAZzJlIwGh2uVC/ff5/c73+/vO /M45YtzdRnqLkzVGXq/hVAzpSrT1+PkFTqBdStlSxXr0m7lQhGylbSSqnJ/C0ESlnUDdza0U arlWjKOa/k4RKrP8LEIXuu4Q6Py043So0EqgqbIGgGaKxklkmhwRodv39qLhiyUkymlqFaF6 i5VC1aNDGDprWsJQReufFMrqsFDI2t4G0PETFiwKsudKzwHWbK0C7GjVLM5+W2Sl2Mr2GYw1 1Z4k2Vsj7STbXHWEzepdJNhTLbWA/fvoVxSbbRklWbvJl708Z6fi1u1L2Z7Ecwm8XsJrlNqE ZE1iBLP7VcULipBQmTxQHoa2MRINp+YjmJ0xcYG7klWONTCSg5wqzdGK4wwGZmvkdr02zchL krQGYwTD6xJUumCd1MCpDWmaRKmGN4bLZbLnQhzC/SlJOZcGSV2f7NAf5XmiDPDFM9nARQzp YPhRZiHIBq5id/oSgMWmWUooZgFsHZrDhOIvAOfsudiaZTpnGRcOOgA8lveAEIosDNY115BO FUkHwu+rO1fYk84EcPJjo1OE08cIaB147AgRiz3oF6GtOMqpIejN8Lv82yttNzoCPi5YDdsE 65o6cSe70JHwYXUf6RwD6U9c4ELHTUIQ7YSPzs6uGjzgvf4WSmBvaL/fQQqshJMVM7jAKtjY /vmqdwfsvFZCOHNx2g82XtwqtH1g/uWGlZE4vQ7mPr67Ot4NmkvXeAssuTUvEvgp2FNXDQRm 4dxC7eqC8gBcyhmnzgDfov8jvgagFmzkdQZ1Im8I0ck1/Lv/3ZpSqzaBlafu/5IZWG0PpN0A E4NuAMU44+kGyqKV7m4J3HvpvF6r0KepeEM3CHHsLw/3Xq/UOv6KxqiQB4fJgkNDQ4PDgkLl jJdbZYG/0p1O5Ix8Cs/reP2aDxO7eGdgMTpZbt4Vz83aD96xfjhWr3AxVrwWTsX+4jXx6YHU TJj8SNJvebMxoPcEpk0fON97/X6JcWxCGoX8Div+aao/ojKVD/gpbF3ZrtZkRUABtxxwKLqq 3LRINC88nZFactBu6Yre4Mkh23x8bu3rg2MbcZFPfOZPWza8X12+/Fnql9L9HgE1YaPbyq05 0TXRC+jZH3tm9lwxvTw8G/EEf+r3N76Jf7hoDpq8I9/r02L3LR1siv3V3AdGvLxGp2J+uC6B Qfvgslr6/FvdZ65q9FFqVz42rOHt3VVp0ydPux7IV+2JVOpv3jh69cl02SubwjOHGX6cO35D 1H7h7o4plj0cZeIYwpDEyf1xvYH7F9GaDFdzBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsWy7bCSnO7rNNdkg6U/JCye7pjJavFg3jY2 i8U/njNZ3F/8mcXi0Oat7BZbrsxmtlh+/ACrxfwj51gtth98xGKx8QVQ9uLMuywWz+evY7R4 Oesem8Wmx9dYLR6+Cre4vGsOm0XPhq2sFmuP3GW3WHr9IpPFsk1/mCwWbf3CbtG69wi7xd09 2xgtWtqOMDlIeKyZt4bRY8fdJYwe15d8YvbYOesuu8fiPS+ZPDat6mTzuHNtD5vH5iX1Hq1H f7F49G1Zxejxr2kuu0fXketsHp83yXmc+vqZPYAvissmJTUnsyy1SN8ugSujZ/cFtoJjBhXv F05kbWCcpt7FyMkhIWAi8aLnL3MXIxeHkMBuRolnfbtZIRIyEv/bjrFD2MISK/89Z4coamaS 6LuwGqyITUBXYv/SA2wgCRGBVkaJ6ys7mUAcZoHZLBI/Jh0AquLgEBZwl3gw2wGkgUVAVWLf 1IfsIGFeAVuJ3zOYIBbIS6zecIAZxOYUsJP4uPQYG4gtBFTS+H4q0wRGvgWMDKsYJVMLinPT c4sNCwzzUsv1ihNzi0vz0vWS83M3MYLjTktzB+P2VR/0DjEycTAeYpTgYFYS4WWc75QsxJuS WFmVWpQfX1Sak1p8iFGag0VJnPdC18l4IYH0xJLU7NTUgtQimCwTB6dUA5NLnII2p8v1+2u9 V5y/3GMT53Hm1G3/gLO/jMTvPbcM2H7Qe8MZ7qOiYjsF2HfWh5Ys8+uN0pl4Z/lTqbjG55v+ 7onelGnksnae+KLv068I3F55tr+Yn9N/1Z2cLy9z19QnXD/49rv1O8NTbQl3Hny0elZ0K3JG UFVFoUmG4eZVV3ZyyR31dJCWPvqu4crdaCGpwyFpGzwz3HW7vXJL235WL+2PN0hyPzld4KvO XpNOmwbXO41xXKUbhHXuidXebAqvj55woWCVrgvD3dAbs+ccmbB5fvJX7TfzQnpevP6WZ8Yz 6doRn+9X5vbOyDv/34ExcurMe0lntsqu3v52Z/jJNYkrQwzK2FI3hL24q/xCiaU4I9FQi7mo OBEAiDX9ZSoDAAA= X-CMS-MailID: 20221011125155epcas5p1e47309b4dd767e81817c316aa0e8b7ca X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125155epcas5p1e47309b4dd767e81817c316aa0e8b7ca References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy Adds V4l2 controls for VP9 encoder documention. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- .../media/v4l/ext-ctrls-codec.rst | 167 ++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst index 2a165ae063fb..2277d83a7cf0 100644 --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst @@ -2187,6 +2187,16 @@ enum v4l2_mpeg_video_vp8_profile - * - ``V4L2_MPEG_VIDEO_VP8_PROFILE_3`` - Profile 3 +VP9 Control Reference +--------------------- + +The VP9 controls include controls for encoding parameters of VP9 video +codec. + +.. _vp9-control-id: + +VP9 Control IDs + .. _v4l2-mpeg-video-vp9-profile: ``V4L2_CID_MPEG_VIDEO_VP9_PROFILE`` @@ -2253,6 +2263,163 @@ enum v4l2_mpeg_video_vp9_level - * - ``V4L2_MPEG_VIDEO_VP9_LEVEL_6_2`` - Level 6.2 +``V4L2_CID_CODEC_VP9_I_FRAME_QP`` + Quantization parameter for an I frame for VP9. Valid range: from 1 to 255. + +``V4L2_CID_CODEC_VP9_P_FRAME_QP`` + Quantization parameter for an P frame for VP9. Valid range: from 1 to 255. + +``V4L2_CID_CODEC_VP9_MAX_QP`` + Maximum quantization parameter for VP9. Valid range: from 1 to 255. + Recommended range for MFC is from 230 to 255. + +``V4L2_CID_CODEC_VP9_MIN_QP`` + Minimum quantization parameter for VP9. Valid range: from 1 to 255. + Recommended range for MFC is from 1 to 24. + +``V4L2_CID_CODEC_VP9_RC_FRAME_RATE`` + Indicates the number of evenly spaced subintervals, called ticks, within + one second. This is a 16 bit unsigned integer and has a maximum value up to + 0xffff and a minimum value of 1. + +``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` + Indicates the refresh period of the golden frame for VP9 encoder. + +.. _v4l2-vp9-golden-frame-sel: + +``V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL`` + (enum) + +enum v4l2_mpeg_vp9_golden_framesel - + Selects the golden frame for encoding. Valid when NUM_OF_REF is 2. + Possible values are: + +.. raw:: latex + + \footnotesize + +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}| + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV`` + - Use the (n-2)th frame as a golden frame, current frame index being + 'n'. + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD`` + - Use the previous specific frame indicated by + ``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` as a + golden frame. + +.. raw:: latex + + \normalsize + + +``V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE`` + Allows host to specify the quantization parameter values for each + temporal layer through HIERARCHICAL_QP_LAYER. This is valid only + if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the control + value to 1 enables setting of the QP values for the layers. + +.. _v4l2-vp9-ref-number-of-pframes: + +``V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES`` + (enum) + +enum v4l2_mpeg_vp9_ref_num_for_pframes - + Number of reference pictures for encoding P frames. + +.. raw:: latex + + \footnotesize + +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}| + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + * - ``V4L2_CID_CODEC_VP9_1_REF_PFRAME`` + - Indicates one reference frame, last encoded frame will be searched. + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD`` + - Indicates 2 reference frames, last encoded frame and golden frame + will be searched. + +.. raw:: latex + + \normalsize + + +``V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER`` + Indicates the number of hierarchial coding layer. + In normal encoding (non-hierarchial coding), it should be zero. + VP9 has upto 3 layer of encoder. + +``V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE`` + Indicates enabling of bit rate for hierarchical coding layers VP9 encoder. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR`` + Indicates bit rate for hierarchical coding layer 0 for VP9 encoder. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR`` + Indicates bit rate for hierarchical coding layer 1 for VP9 encoder. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR`` + Indicates bit rate for hierarchical coding layer 2 for VP9 encoder. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP`` + Indicates quantization parameter for hierarchical coding layer 0. + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP, + V4L2_CID_CODEC_VP9_MAX_QP]. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP`` + Indicates quantization parameter for hierarchical coding layer 1. + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP, + V4L2_CID_CODEC_VP9_MAX_QP]. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP`` + Indicates quantization parameter for hierarchical coding layer 2. + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP, + V4L2_CID_CODEC_VP9_MAX_QP]. + +.. _v4l2-vp9-max-partition-depth: + +``V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH`` + (enum) + +enum v4l2_mpeg_vp9_num_partitions - + Indicate maximum coding unit depth. + +.. raw:: latex + + \footnotesize + +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}| + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + * - ``V4L2_CID_CODEC_VP9_0_PARTITION`` + - No coding unit partition depth. + * - ``V4L2_CID_CODEC_VP9_1_PARTITION`` + - Allows one coding unit partition depth. + +.. raw:: latex + + \normalsize + + +``V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT`` + Zero indicates enable intra NxN PU split. + One indicates disable intra NxN PU split. + +``V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER`` + Indicates IVF header generation. Zero indicates enable IVF format. + One indicates disable IVF format. + High Efficiency Video Coding (HEVC/H.265) Control Reference =========================================================== From patchwork Tue Oct 11 12:25:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aakarsh Jain X-Patchwork-Id: 13004614 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B410C433FE for ; Wed, 12 Oct 2022 03:49:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229684AbiJLDtA (ORCPT ); Tue, 11 Oct 2022 23:49:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229695AbiJLDsR (ORCPT ); Tue, 11 Oct 2022 23:48:17 -0400 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1AABA287E for ; Tue, 11 Oct 2022 20:47:55 -0700 (PDT) Received: from epcas5p1.samsung.com (unknown [182.195.41.39]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20221012034753epoutp015a1c01a74752c129a53ca1d520c3f120~dNbFfzWmK2322523225epoutp01W for ; Wed, 12 Oct 2022 03:47:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20221012034753epoutp015a1c01a74752c129a53ca1d520c3f120~dNbFfzWmK2322523225epoutp01W DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1665546473; bh=NO3l/8N67+LRHCcmkiDY0z0XWJK5GVH8GrsUrIeLNuc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ub1RPf+SUFdKJNnc1OwHA0PUF5mOvLP4u9JXQrPSR7ReNgBylux/w3i3iTb7lLWck AZW+8DNn1vW2iSZWgRqGeKJQwTf2X6iYh/dZMjz2N/m0r7QX+uiUzk6tKfFTJnT35n 3lB+QFBm1dt/MJ9ICqUvDR2ndAVr8Fn3DGnG5PVo= Received: from epsnrtp3.localdomain (unknown [182.195.42.164]) by epcas5p2.samsung.com (KnoxPortal) with ESMTP id 20221012034751epcas5p211d6de964178e3112a95ea5b67f6fb95~dNbEZyFE00049100491epcas5p2O; Wed, 12 Oct 2022 03:47:51 +0000 (GMT) Received: from epsmges5p2new.samsung.com (unknown [182.195.38.182]) by epsnrtp3.localdomain (Postfix) with ESMTP id 4MnJWm3C2xz4x9Pr; Wed, 12 Oct 2022 03:47:48 +0000 (GMT) Received: from epcas5p4.samsung.com ( [182.195.41.42]) by epsmges5p2new.samsung.com (Symantec Messaging Gateway) with SMTP id 30.FB.39477.4E836436; Wed, 12 Oct 2022 12:47:48 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20221011125158epcas5p14f2b333fdb1eed793e9fbf85409f5a36~dBM3BCsZi0252702527epcas5p1F; Tue, 11 Oct 2022 12:51:58 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20221011125158epsmtrp18a6384d603d8c9f5358d089b53f80480~dBM2-4SZh2654526545epsmtrp1F; Tue, 11 Oct 2022 12:51:58 +0000 (GMT) X-AuditID: b6c32a4a-007ff70000019a35-74-634638e44bc9 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 5F.0D.14392.EE665436; Tue, 11 Oct 2022 21:51:58 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125155epsmtip19b75ee41d1f37c2f515ed8cc37e90ea4~dBMz5fms02178321783epsmtip15; Tue, 11 Oct 2022 12:51:55 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 06/15] media: v4l2: Add v4l2 control IDs for VP9 encoder. Date: Tue, 11 Oct 2022 17:55:07 +0530 Message-Id: <20221011122516.32135-7-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTf0xTVxTHva+vr4VQ91JgXmAINOwHXUAqpbsslOk05IlKiFtiGFFWy0uL 9Ff6Wsc02VCGdo3o3GQOZIAUZBQELT9EVgYURCELCZPRxFFWBMS66Rg/NjfQjVLc/vuce77n 3nO+914ui+8mQrm5GgOt18hUAsIfb++LEcZOo1R5fOe1YDTTUcpG7op2AlmezGLoZ8sCjhwt bRzUOnqRhepu9bBRZf8wG13vvYejaw9WsyOlLhzNVjYB5CmbIJBtaoyNJh/uR3c6ywl0+mob G13pd3FQrXMEQ5dtKxiqblvkoKKufg5y2dsB+uRkP7YNUo0VjYDqcNUAylkzz6JulLk4lMXu wSib9VOCGh+zE1RLzcdU0c2/cepMqxVQz058zaHM/U6CWrBtpoaWFjgZG9/LS1bSshxaH0lr 5NqcXI1CKtj9TvaO7ERJvChWlITeEERqZGpaKti5JyM2NVe1aoMg8ohMZVxdypAxjGBLSrJe azTQkUotY5AKaF2OSifWxTEyNWPUKOI0tOFNUXz81sRV4ft5yjOFjO6CJP/0wmO8AHRtMQM/ LiTFcOpGN2YG/lw++S2Alj9PAF8wD+DlwlHCF/wB4ODMMtsMuGsl8wXroi4A21wP1oMiDN4t nsS8+xJkLOyu7SG8HEQeB3DKZPCKWGQhDl3fL3O8iUByD/xl4ibuZZx8GTa769cKeKQUPip1 s30NRsCGqz0sL/uRKfD32oG1liB5yg86L7YQPtFOWFzm4fg4ED681brOodBz9uQ6y+FUtYfl YxVstp/HffwW7Bktx72jscgY2Ny5bkw4LBlqWhuGRW6ExcvTmG+dBzsqnvMrsHz8yXqfL8G+ hlrgYwpWlVRyfK6cA7DeYSM+A5vL/j+iCgArCKF1jFpBM4m6rRr6g/9uTa5V28DaUxemdYBJ 91ycA2Bc4ACQyxIE8UDl23I+L0f24VFar83WG1U04wCJqwaeY4UGy7Wrf0VjyBaJk+LFEolE nJQgEQk28SxfCeV8UiEz0Hk0raP1z+swrl9oAXZppTJC+uLtdIfVeKnPVBC2nfvb/btzE+Ek M7i39+ipNEnmAYtJJ82xfRG1Ia8l2l7TOJcdQN654txRtKsqIHgo4nF347Fji0ZVfqas5MAS 5PTWk3U/JYxJ8duvZ5k7kXyaHzic5cYTY4WZPebmmX2K0tm4qPwvD9U1NcUvOrPHe19IENbs imk4WO9RjvzIC03rDL6XHtt+vEoezW2MPG/6aCBhe4Dh/sqzduyHtqzdik1/DRbLZ5WkPeA1 8aPPnw5905pqDgkMS/5VY30anfldYUh6tend4aiUw5QnM2ze32FS9x4O36/e9+oFZnTbzKG9 A0GFKUcOnrXyN1xXL/2TK8AZpUwkZOkZ2b/rjBvMcwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsWy7bCSnO67NNdkg3f9BhZPd8xktXgwbxub xeIfz5ks7i/+zGJxaPNWdostV2YzWyw/foDVYv6Rc6wW2w8+YrHY+AIoe3HmXRaL5/PXMVq8 nHWPzWLT42usFg9fhVtc3jWHzaJnw1ZWi7VH7rJbLL1+kcli2aY/TBaLtn5ht2jde4Td4u6e bYwWLW1HmBwkPNbMW8PosePuEkaP60s+MXvsnHWX3WPxnpdMHptWdbJ53Lm2h81j85J6j9aj v1g8+rasYvT41zSX3aPryHU2j8+b5DxOff3MHsAXxWWTkpqTWZZapG+XwJXR11xcMN2soufz O5YGxr36XYwcHBICJhKfGhi7GLk4hAR2M0qcmPOFtYuREyguI/G/7Rg7hC0ssfLfc3aIomYm iQfXvjOCJNgEdCX2Lz3ABpIQEWhllLi+spMJxGEWmM0i8WPSAbBRwgI+Eq/vHWUBsVkEVCXW P1jJBmLzCthKvJ35AGqdvMTqDQeYQWxOATuJj0uPgdUIAdU0vp/KNIGRbwEjwypGydSC4tz0 3GLDAsO81HK94sTc4tK8dL3k/NxNjOC409Lcwbh91Qe9Q4xMHIyHGCU4mJVEeBnnOyUL8aYk VlalFuXHF5XmpBYfYpTmYFES573QdTJeSCA9sSQ1OzW1ILUIJsvEwSnVwLT0s7c0X443p1DQ CYvk7zwLRQ+9duJvSMzdP6cio1Ruw51PL1XWc6fWToz5wHpwouGUiRetDlz+Jv9B1Oh+QV7o myvWHxM2tUSmJ5wrOzzv9CR74frXt2WEmlVmppcadXHn9u9qC73NIr5aveFQ68fNttIJy5YE C7N8Un73MPxyGdcmabd6JimGclmPc+VSW2SNp9r47WQrrGi5t3C74ou9YlKvTbpSPy52XVhq vmWCcuQCQWPteSyaKxvVYqWOmz2RCfvAU/1a9EJ2Np/Y5jqxZWXFOwIOtJfcfRiedc5384NT 68trvrX1sLSYaE9aVHdu/stZ6ZeuLL4SnbXjpvQlBdX3GSGvf+RH/wr/rcRSnJFoqMVcVJwI ABJtdGYqAwAA X-CMS-MailID: 20221011125158epcas5p14f2b333fdb1eed793e9fbf85409f5a36 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125158epcas5p14f2b333fdb1eed793e9fbf85409f5a36 References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy Add V4l2 controls for VP9 encoder Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- drivers/media/v4l2-core/v4l2-ctrls-defs.c | 44 +++++++++++++++++++++++ include/uapi/linux/v4l2-controls.h | 33 +++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c index e22921e7ea61..2d92e93158bd 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c +++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c @@ -577,6 +577,21 @@ const char * const *v4l2_ctrl_get_menu(u32 id) "Cyclic", NULL, }; + static const char * const vp9_golden_framesel[] = { + "Use previous", + "Use refresh period", + NULL, + }; + static const char * const vp9_ref_num_for_pframes[] = { + "1", + "2", + NULL, + }; + static const char * const vp9_max_partition_depth[] = { + "No CU partition depth", + "Allow 1 CU partition depth", + NULL, + }; switch (id) { case V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ: @@ -708,6 +723,12 @@ const char * const *v4l2_ctrl_get_menu(u32 id) return hevc_decode_mode; case V4L2_CID_STATELESS_HEVC_START_CODE: return hevc_start_code; + case V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL: + return vp9_golden_framesel; + case V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES: + return vp9_ref_num_for_pframes; + case V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH: + return vp9_max_partition_depth; case V4L2_CID_CAMERA_ORIENTATION: return camera_orientation; case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE: @@ -950,6 +971,26 @@ const char *v4l2_ctrl_get_name(u32 id) case V4L2_CID_MPEG_VIDEO_VP8_PROFILE: return "VP8 Profile"; case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: return "VP9 Profile"; case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: return "VP9 Level"; + case V4L2_CID_CODEC_VP9_I_FRAME_QP: return "VP9 I Frame QP Value"; + case V4L2_CID_CODEC_VP9_P_FRAME_QP: return "VP9 P Frame QP Value"; + case V4L2_CID_CODEC_VP9_MAX_QP: return "VP9 Frame QP MAX Value"; + case V4L2_CID_CODEC_VP9_MIN_QP: return "VP9 Frame QP MIN Value"; + case V4L2_CID_CODEC_VP9_RC_FRAME_RATE: return "VP9 Frame Rate"; + case V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL: return "VP9 Indication of Golden Frame"; + case V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD: return "VP9 Golden Frame Refresh Period"; + case V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE: return "VP9 Hierarchical QP Enable"; + case V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES: return "VP9 Number of Reference Pictures"; + case V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER:return "VP9 Num of Hierarchical Layers"; + case V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH: return "VP9 Maximum Coding Unit Depth"; + case V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT: return "VP9 Disable Intra PU Split"; + case V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE: return "VP9 Hierarchical BitRate Enable"; + case V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR: return "VP9 Hierarchical Layer 0 BitRate"; + case V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR: return "VP9 Hierarchical Layer 1 BitRate"; + case V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR: return "VP9 Hierarchical Layer 2 BitRate"; + case V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP: return "VP9 Layer0 QP Value"; + case V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP: return "VP9 Layer1 QP Value"; + case V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP: return "VP9 Layer2 QP Value"; + case V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER: return "VP9 IVF header generation"; /* HEVC controls */ case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: return "HEVC I-Frame QP Value"; @@ -1366,6 +1407,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, case V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE: case V4L2_CID_STATELESS_HEVC_DECODE_MODE: case V4L2_CID_STATELESS_HEVC_START_CODE: + case V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL: + case V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES: + case V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH: case V4L2_CID_STATELESS_H264_DECODE_MODE: case V4L2_CID_STATELESS_H264_START_CODE: case V4L2_CID_CAMERA_ORIENTATION: diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index b5e7d082b8ad..a60b60bc4ad4 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -722,6 +722,38 @@ enum v4l2_mpeg_video_vp9_level { V4L2_MPEG_VIDEO_VP9_LEVEL_6_1 = 12, V4L2_MPEG_VIDEO_VP9_LEVEL_6_2 = 13, }; +#define V4L2_CID_CODEC_VP9_RC_FRAME_RATE (V4L2_CID_CODEC_BASE+514) +#define V4L2_CID_CODEC_VP9_MIN_QP (V4L2_CID_CODEC_BASE+515) +#define V4L2_CID_CODEC_VP9_MAX_QP (V4L2_CID_CODEC_BASE+516) +#define V4L2_CID_CODEC_VP9_I_FRAME_QP (V4L2_CID_CODEC_BASE+517) +#define V4L2_CID_CODEC_VP9_P_FRAME_QP (V4L2_CID_CODEC_BASE+518) +#define V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL (V4L2_CID_CODEC_BASE+519) +enum v4l2_mpeg_vp9_golden_framesel { + V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV = 0, + V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD = 1, +}; +#define V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD (V4L2_CID_CODEC_BASE+520) +#define V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE (V4L2_CID_CODEC_BASE+521) +#define V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES (V4L2_CID_CODEC_BASE+522) +enum v4l2_mpeg_vp9_ref_num_for_pframes { + V4L2_CID_CODEC_VP9_1_REF_PFRAME = 0, + V4L2_CID_CODEC_VP9_2_REF_PFRAME = 1, +}; +#define V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER (V4L2_CID_CODEC_BASE+523) +#define V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR (V4L2_CID_CODEC_BASE+524) +#define V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR (V4L2_CID_CODEC_BASE+525) +#define V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR (V4L2_CID_CODEC_BASE+526) +#define V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP (V4L2_CID_CODEC_BASE+527) +#define V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP (V4L2_CID_CODEC_BASE+528) +#define V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP (V4L2_CID_CODEC_BASE+529) +#define V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH (V4L2_CID_CODEC_BASE+530) +enum v4l2_mpeg_vp9_num_partitions { + V4L2_CID_CODEC_VP9_0_PARTITION = 0, + V4L2_CID_CODEC_VP9_1_PARTITION = 1, +}; +#define V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT (V4L2_CID_CODEC_BASE+531) +#define V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER (V4L2_CID_CODEC_BASE+532) +#define V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE (V4L2_CID_CODEC_BASE+533) /* CIDs for HEVC encoding. */ @@ -832,6 +864,7 @@ enum v4l2_mpeg_video_frame_skip_mode { #define V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY (V4L2_CID_CODEC_BASE + 653) #define V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE (V4L2_CID_CODEC_BASE + 654) + /* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */ #define V4L2_CID_CODEC_CX2341X_BASE (V4L2_CTRL_CLASS_CODEC | 0x1000) #define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_CODEC_CX2341X_BASE+0) From patchwork Tue Oct 11 12:25:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aakarsh Jain X-Patchwork-Id: 13004615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABFEEC4332F for ; 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Tue, 11 Oct 2022 12:52:02 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20221011125202epsmtrp2032248f9f2abbe404a84eef82ef4b712~dBM6Msbp91820318203epsmtrp2-; Tue, 11 Oct 2022 12:52:02 +0000 (GMT) X-AuditID: b6c32a4a-007ff70000019a35-86-634638e8e36b Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 21.1D.14392.2F665436; Tue, 11 Oct 2022 21:52:02 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125158epsmtip10bec6fea4bb1c315708813869379c2a2~dBM3C96452179321793epsmtip18; Tue, 11 Oct 2022 12:51:58 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 07/15] media: s5p-mfc: Add support for VP9 encoder. Date: Tue, 11 Oct 2022 17:55:08 +0530 Message-Id: <20221011122516.32135-8-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTf1DTZRzHe77f7bsNm34DPZ9IjZvCBQZsMuYDCXXK0TctQrjs0j/m98Y3 4Bjb3EZqZVIyTxE6ubCC+KUwlI2BTcBJ4yCYP5hkiFMO2EikFEZ4CEqcZrQxqP9e97w/78/n fZ/nebi4/wgRyM1UaBm1gpYLCD9WS1doaPgYSpQJ7w+J0R+WEja6W9FCoOq5Bxj6rXqGhTov NHNQk+MHHJ292sFGlbYbbHTx53ss9OOYR71Z4mKhB5UNAI2XDhPIPHqHjUbcH6JbrWUEKjjf zEYmm4uD9P03MVRr/htDZ5ofc5CuzcZBLmsLQHlHbdhbkKqvqAeUxVUDqP6aaZy6VOriUNXW cYwyG44TlPOOlaAu1BymdJefsqivmwyA+uercg6Vb+snqBnzOsr+ZIaTvHx31pYMhk5j1EGM QqZMy1Skxwl2pEq3SaMlQlG4KAZtFgQp6GwmTpDwbnJ4YqbcswZB0Ce0PMdzlExrNILI+C1q ZY6WCcpQarRxAkaVJleJVREaOluTo0iPUDDaWJFQuCnaU7g3K+OXwfts1UAhOOAcn8NzQYM2 H/C4kBRDU66ByAd+XH/yJwAvGp6zvII/OQ1gQc+iMAtg20AXZ8lxreUe8AltAP46WM/2OXQY HOohvUyQ4bBd30F4eSX5JYCjx7ReA04eYUFXz7OFTgFkInzSfhb3MosMhqemijEv88k46DBO sXzTXoXG8x0LNTwyHj7SX1mIBMkTPNj+p5XtK0qAvd/dxnwcAN1XmxajBsKZh22Ej2Vw9Mw4 7mM5bLQWLw54E3Y4yjzM9aQLhY2tkb7jtfCUvWGhJU4uh4XPfl9sz4eWiiUOgWXOucUIa2CX UQ98TMHq8gnMt6EiAKf6LoGTYF3p/yOqADCAlxmVJjud0USrNimY/f9dm0yZbQYLbz1suwWM 3J2K6AQYF3QCyMUFK/mgcqvMn59GH/yUUSul6hw5o+kE0Z4FFuGBq2RKz2dRaKUicYxQLJFI xDFREpFgNb/6+zCZP5lOa5kshlEx6iUfxuUF5mLK8h1doRsz6r5IGeaNkuvnLbX7tvGC7Ydb ox7JrGv2TJwLyNtpMsXax1asl/btPdbdnfBeX2xDFN007RS99MLnrxSeK3s4Ieg5EMmbdAyS ZQUh7lVCu9+RDrsqtCg1pbHqdmmjfjJlp2nZa3X803XB6hDqRPHb3Xuuv17wvhW+IZWM6WpT r6T1lxz8GI0sM26IsW4Gw1VrH0/yNsza/uo1Ois2Ci/XSD9w7HN/9o0fp1+/3eLWJfGTiCTz i4ahdw59m1t59FDV8d2nu4UO066pYZ1xa/Cs/GTrDWesfCD+RPqtXmzF85Ka+f3sp+5rA6v9 ylMT60pyRlo488a8XbMfBV0XsDQZtCgMV2vofwE/0WHAdAQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprFIsWRmVeSWpSXmKPExsWy7bCSnO6nNNdkg+dNPBZPd8xktXgwbxub xeIfz5ks7i/+zGJxaPNWdostV2YzWyw/foDVYv6Rc6wW2w8+YrHY+AIoe3HmXRaL5/PXMVq8 nHWPzWLT42usFg9fhVtc3jWHzaJnw1ZWi7VH7rJbLL1+kcli2aY/TBaLtn5ht2jde4Td4u6e bYwWLW1HmBwkPNbMW8PosePuEkaP60s+MXvsnHWX3WPxnpdMHptWdbJ53Lm2h81j85J6j9aj v1g8+rasYvT41zSX3aPryHU2j8+b5DxOff3MHsAXxWWTkpqTWZZapG+XwJVx9tYz1oKbvYwV d17+YG5gXFfSxcjJISFgInFi2yPGLkYuDiGB3YwSq361sEEkZCT+tx1jh7CFJVb+e84OUdTM JPH/5VWwBJuArsT+pQfYQBIiAq2MEtdXdjKBOMwCs1kkfkw6wApSJSzgJvF1/3JmEJtFQFVi 6ocpTCA2r4CtxJXVH1ggVshLrN5wAKyGU8BO4uPSY2BnCAHVNL6fyjSBkW8BI8MqRsnUguLc 9NxiwwLDvNRyveLE3OLSvHS95PzcTYzg6NPS3MG4fdUHvUOMTByMhxglOJiVRHgZ5zslC/Gm JFZWpRblxxeV5qQWH2KU5mBREue90HUyXkggPbEkNTs1tSC1CCbLxMEp1cCkP4+x9HqXa9+h GT3aD+wDe1ftXHUvyDuX49GXRbKNPjH7gqQc9nGuE9pW4Fdzd/KhvU09cwtD/rRuVfN1dXt8 9iLfg5Ou0VlPFi8JaDReOb1P8d3E36aG74rL29fxGT1jfzNd3+RrpdOMXTweup49t3dcuNO+ +R53k85XdmFDaf7Fvjzy22Z8q55lqft1s+vxhNr3X/kXKetf3qDvx2omz7TMM2b7nrN3RA12 M4alitfeWi+5W+2T16Ml3i/3Tz3RL/Z244r+dN79G+7+njSpSPOG/4Ws9Z+k30VlmiQ6O035 WL9SS1qza+Hj94fy3zdl2Bpo3Hy17U7v2QyWpmp7p9qbdUfLF2Rv2sGw//w5JZbijERDLeai 4kQAb6gLvS0DAAA= X-CMS-MailID: 20221011125202epcas5p4ef2d0dc9b6c434912b5c552c20bff4f5 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125202epcas5p4ef2d0dc9b6c434912b5c552c20bff4f5 References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy Add VP9 encoder support and necessary registers, V4L2 CIDs, vp9 encoder parameters. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- .../platform/samsung/s5p-mfc/regs-mfc-v12.h | 8 + .../platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c | 3 + .../platform/samsung/s5p-mfc/s5p_mfc_common.h | 27 +- .../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 273 ++++++++++++++++++ .../platform/samsung/s5p-mfc/s5p_mfc_opr.h | 2 + .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 121 ++++++++ 6 files changed, 433 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h index 6c68a45082d0..7cb74a9cb769 100644 --- a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h +++ b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h @@ -12,6 +12,10 @@ #include #include "regs-mfc-v10.h" +/* MFCv12 register definitions*/ +#define S5P_FIMV_E_VP9_OPTION_V12 0xFD90 +#define S5P_FIMV_E_VP9_GOLDEN_FRAME_OPTION_V12 0xFD98 + /* MFCv12 Context buffer sizes */ #define MFC_CTX_BUF_SIZE_V12 (30 * SZ_1K) #define MFC_H264_DEC_CTX_BUF_SIZE_V12 (2 * SZ_1M) @@ -47,4 +51,8 @@ ALIGN((((x + 3) * (y + 3) * 32) \ + (((y * 128) + 2304) * (x + 3) / 4)), 256) +#define ENC_V120_VP9_ME_SIZE(x, y) \ + ((((x * 2) + 3) * ((y * 2) + 3) * 128) \ + + (((y * 256) + 2304) * (x + 1) / 2)) + #endif /*_REGS_MFC_V12_H*/ diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c index f8588e52dfc8..d524815cd38a 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c @@ -121,6 +121,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx) case S5P_MFC_CODEC_HEVC_ENC: codec_type = S5P_FIMV_CODEC_HEVC_ENC; break; + case S5P_MFC_CODEC_VP9_ENC: + codec_type = S5P_FIMV_CODEC_VP9_ENC; + break; default: codec_type = S5P_FIMV_CODEC_NONE_V6; } diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h index dd2e9f7704ab..10abaa50d7db 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h @@ -57,7 +57,7 @@ #define MFC_ENC_CAP_PLANE_COUNT 1 #define MFC_ENC_OUT_PLANE_COUNT 2 #define STUFF_BYTE 4 -#define MFC_MAX_CTRLS 128 +#define MFC_MAX_CTRLS 147 #define S5P_MFC_CODEC_NONE -1 #define S5P_MFC_CODEC_H264_DEC 0 @@ -77,6 +77,7 @@ #define S5P_MFC_CODEC_H263_ENC 23 #define S5P_MFC_CODEC_VP8_ENC 24 #define S5P_MFC_CODEC_HEVC_ENC 26 +#define S5P_MFC_CODEC_VP9_ENC 27 #define S5P_MFC_R2H_CMD_EMPTY 0 #define S5P_MFC_R2H_CMD_SYS_INIT_RET 1 @@ -483,6 +484,29 @@ struct s5p_mfc_hevc_enc_params { u8 prepend_sps_pps_to_idr; }; +/** + * struct s5p_mfc_vp9_enc_params - encoding parameters for vp9 + */ +struct s5p_mfc_vp9_enc_params { + u32 rc_framerate; + u8 vp9_profile; + u8 rc_min_qp; + u8 rc_max_qp; + u8 rc_frame_qp; + u8 rc_p_frame_qp; + u8 vp9_goldenframesel; + u8 vp9_gfrefreshperiod; + u8 hier_qp_enable; + u8 hier_qp_layer[3]; + u8 hier_rc_enable; + u32 hier_bit_layer[3]; + u8 num_refs_for_p; + u8 num_hier_layer; + u8 max_partition_depth; + u8 intra_pu_split_disable; + u8 ivf_header; +}; + /* * struct s5p_mfc_enc_params - general encoding parameters */ @@ -521,6 +545,7 @@ struct s5p_mfc_enc_params { struct s5p_mfc_mpeg4_enc_params mpeg4; struct s5p_mfc_vp8_enc_params vp8; struct s5p_mfc_hevc_enc_params hevc; + struct s5p_mfc_vp9_enc_params vp9; } codec; }; diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c index 143d95fe2f89..197667ab1fbc 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c @@ -94,6 +94,14 @@ static struct s5p_mfc_fmt formats[] = { .num_planes = 1, .versions = MFC_V10PLUS_BITS, }, + { + .fourcc = V4L2_PIX_FMT_VP9, + .codec_mode = S5P_FIMV_CODEC_VP9_ENC, + .type = MFC_FMT_ENC, + .num_planes = 1, + .versions = MFC_V12_BIT, + }, + }; #define NUM_FORMATS ARRAY_SIZE(formats) @@ -1055,6 +1063,174 @@ static struct mfc_control controls[] = { .step = 1, .default_value = 0, }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE, + .type = V4L2_CTRL_TYPE_MENU, + .minimum = V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .maximum = V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_VP9_PROFILE_0, + }, + { + .id = V4L2_CID_CODEC_VP9_I_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 1, + .maximum = 255, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_CODEC_VP9_P_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 1, + .maximum = 255, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_CODEC_VP9_MAX_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 230, + .maximum = 255, + .step = 1, + .default_value = 255, + }, + { + .id = V4L2_CID_CODEC_VP9_MIN_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 1, + .maximum = 24, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_CODEC_VP9_RC_FRAME_RATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 1, + .maximum = (1 << 16) - 1, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL, + .type = V4L2_CTRL_TYPE_MENU, + .minimum = V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV, + .maximum = V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD, + .step = 1, + .default_value = V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV, + }, + { + .id = V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 0, + .maximum = ((1 << 16) - 1), + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES, + .type = V4L2_CTRL_TYPE_MENU, + .minimum = V4L2_CID_CODEC_VP9_1_REF_PFRAME, + .maximum = V4L2_CID_CODEC_VP9_2_REF_PFRAME, + .step = 1, + .default_value = V4L2_CID_CODEC_VP9_1_REF_PFRAME, + }, + { + .id = V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 0, + .maximum = 2, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH, + .type = V4L2_CTRL_TYPE_MENU, + .minimum = V4L2_CID_CODEC_VP9_0_PARTITION, + .maximum = V4L2_CID_CODEC_VP9_1_PARTITION, + .step = 1, + .default_value = V4L2_CID_CODEC_VP9_0_PARTITION, + }, + { + .id = V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, { .id = V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, .type = V4L2_CTRL_TYPE_INTEGER, @@ -1791,6 +1967,36 @@ static void __enc_update_hevc_qp_ctrls_range(struct s5p_mfc_ctx *ctx, } } +/* + * Update range of all VP9 quantization parameter controls that depend on the + * V4L2_CID_CODEC_VP9_MIN_QP, V4L2_CID_CODEC_VP9_MAX_QP controls. + */ +static void __enc_update_vp9_qp_ctrls_range(struct s5p_mfc_ctx *ctx, + int min, int max) +{ + static const int __vp9_qp_ctrls[] = { + V4L2_CID_CODEC_VP9_I_FRAME_QP, + V4L2_CID_CODEC_VP9_P_FRAME_QP, + V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP, + V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP, + V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP, + }; + struct v4l2_ctrl *ctrl = NULL; + int i, j; + + for (i = 0; i < ARRAY_SIZE(__vp9_qp_ctrls); i++) { + for (j = 0; j < ARRAY_SIZE(ctx->ctrls); j++) { + if (ctx->ctrls[j]->id == __vp9_qp_ctrls[i]) { + ctrl = ctx->ctrls[j]; + break; + } + } + if (WARN_ON(!ctrl)) + break; + __v4l2_ctrl_modify_range(ctrl, min, max, ctrl->step, min); + } +} + static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl) { struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl); @@ -2194,6 +2400,73 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: p->codec.hevc.prepend_sps_pps_to_idr = ctrl->val; break; + case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: + p->codec.vp9.vp9_profile = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_RC_FRAME_RATE: + p->codec.vp9.rc_framerate = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_MIN_QP: + p->codec.vp9.rc_min_qp = ctrl->val; + __enc_update_vp9_qp_ctrls_range(ctx, ctrl->val, + p->codec.vp9.rc_max_qp); + break; + case V4L2_CID_CODEC_VP9_MAX_QP: + p->codec.vp9.rc_max_qp = ctrl->val; + __enc_update_vp9_qp_ctrls_range(ctx, + p->codec.vp9.rc_min_qp, ctrl->val); + break; + case V4L2_CID_CODEC_VP9_I_FRAME_QP: + p->codec.vp9.rc_frame_qp = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_P_FRAME_QP: + p->codec.vp9.rc_p_frame_qp = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL: + p->codec.vp9.vp9_goldenframesel = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD: + p->codec.vp9.vp9_gfrefreshperiod = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE: + p->codec.vp9.hier_qp_enable = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE: + p->codec.vp9.hier_rc_enable = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP: + p->codec.vp9.hier_qp_layer[0] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP: + p->codec.vp9.hier_qp_layer[1] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP: + p->codec.vp9.hier_qp_layer[2] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR: + p->codec.vp9.hier_bit_layer[0] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR: + p->codec.vp9.hier_bit_layer[1] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR: + p->codec.vp9.hier_bit_layer[2] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES: + p->codec.vp9.num_refs_for_p = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER: + p->codec.vp9.num_hier_layer = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH: + p->codec.vp9.max_partition_depth = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT: + p->codec.vp9.intra_pu_split_disable = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER: + p->codec.vp9.ivf_header = ctrl->val; + break; default: v4l2_err(&dev->v4l2_dev, "Invalid control, id=%d, val=%d\n", ctrl->id, ctrl->val); diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h index 87ac56756a16..a005623e2daa 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h @@ -277,6 +277,8 @@ struct s5p_mfc_regs { void __iomem *e_hevc_lf_beta_offset_div2; /* v10 */ void __iomem *e_hevc_lf_tc_offset_div2; /* v10 */ void __iomem *e_hevc_nal_control; /* v10 */ + void __iomem *e_vp9_options; /* v12 */ + void __iomem *e_vp9_golden_frame_option; /* v12 */ }; struct s5p_mfc_hw_ops { diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c index 5d14ccf8b4fe..87bd10b34620 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c @@ -363,6 +363,17 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->chroma_dpb_size + ctx->me_buffer_size)); ctx->bank2.size = 0; break; + case S5P_FIMV_CODEC_VP9_ENC: + mfc_debug(2, "Use min scratch buffer size\n"); + ctx->me_buffer_size = + ALIGN(ENC_V120_VP9_ME_SIZE(lcu_width, lcu_height), 16); + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256); + ctx->bank1.size = + ctx->scratch_buf_size + ctx->tmv_buffer_size + + (ctx->pb_count * (ctx->luma_dpb_size + + ctx->chroma_dpb_size + ctx->me_buffer_size)); + ctx->bank2.size = 0; + break; default: break; } @@ -418,6 +429,7 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx) case S5P_MFC_CODEC_MPEG4_ENC: case S5P_MFC_CODEC_H263_ENC: case S5P_MFC_CODEC_VP8_ENC: + case S5P_FIMV_CODEC_VP9_ENC: ctx->ctx.size = buf_size->other_enc_ctx; break; default: @@ -1652,6 +1664,102 @@ static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) return 0; } +int s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx) +{ + struct s5p_mfc_dev *dev = ctx->dev; + const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; + struct s5p_mfc_enc_params *p = &ctx->enc_params; + struct s5p_mfc_vp9_enc_params *p_vp9 = &p->codec.vp9; + unsigned int reg = 0; + int i; + + mfc_debug_enter(); + + s5p_mfc_set_enc_params(ctx); + + /* profile*/ + reg = 0; + reg |= (p_vp9->vp9_profile); + writel(reg, mfc_regs->e_picture_profile); + + reg = 0; + reg |= ((p_vp9->ivf_header & 0x1) << 12); + reg |= ((p_vp9->hier_qp_enable & 0x1) << 11); + reg |= (p_vp9->max_partition_depth & 0x1) << 3; + reg |= (p_vp9->intra_pu_split_disable & 0x1) << 1; + reg |= (p_vp9->num_refs_for_p - 1) & 0x1; + writel(reg, mfc_regs->e_vp9_options); + + reg = 0; + reg |= (p_vp9->vp9_goldenframesel & 0x1); + reg |= (p_vp9->vp9_gfrefreshperiod & 0xffff) << 1; + writel(reg, mfc_regs->e_vp9_golden_frame_option); + + reg = 0; + if (p_vp9->num_hier_layer) { + reg |= p_vp9->num_hier_layer & 0x3; + writel(reg, mfc_regs->e_num_t_layer); + /* QP value for each layer */ + if (p_vp9->hier_qp_enable) { + for (i = 0; i < (p_vp9->num_hier_layer & 0x3); i++) + writel(p_vp9->hier_qp_layer[i], + mfc_regs->e_hier_qp_layer0 + + i * 4); + } + if (p_vp9->hier_rc_enable) { + for (i = 0; i < (p_vp9->num_hier_layer & 0x3); i++) + writel(p_vp9->hier_bit_layer[i], + mfc_regs->e_hier_bit_rate_layer0 + + i * 4); + } + } + /* number of coding layer should be zero when hierarchical is disable */ + reg |= p_vp9->num_hier_layer; + writel(reg, mfc_regs->e_num_t_layer); + + /* qp */ + writel(0x0, mfc_regs->e_fixed_picture_qp); + if (!p->rc_frame && !p->rc_mb) { + reg = 0; + reg &= ~(0xff << 8); + reg |= (p_vp9->rc_p_frame_qp << 8); + reg &= ~(0xff); + reg |= p_vp9->rc_frame_qp; + writel(reg, mfc_regs->e_fixed_picture_qp); + } + + /* frame rate */ + if (p->rc_frame) { + reg = 0; + reg &= ~(0xffff << 16); + reg |= ((p_vp9->rc_framerate * FRAME_DELTA_DEFAULT) << 16); + reg &= ~(0xffff); + reg |= FRAME_DELTA_DEFAULT; + writel(reg, mfc_regs->e_rc_frame_rate); + } + + /* rate control config. */ + reg = readl(mfc_regs->e_rc_config); + /** macroblock level rate control */ + reg &= ~(0x1 << 8); + reg |= ((p->rc_mb & 0x1) << 8); + writel(reg, mfc_regs->e_rc_config); + + /* max & min value of QP */ + reg = 0; + /** max QP */ + reg &= ~(0xFF << 8); + reg |= (p_vp9->rc_max_qp << 8); + /** min QP */ + reg &= ~(0xFF); + reg |= p_vp9->rc_min_qp; + writel(reg, mfc_regs->e_rc_qp_bound); + + mfc_debug_leave(); + + return 0; +} + /* Initialize decoding */ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx) { @@ -1773,6 +1881,8 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx) s5p_mfc_set_enc_params_vp8(ctx); else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC) s5p_mfc_set_enc_params_hevc(ctx); + else if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_ENC) + s5p_mfc_set_enc_params_vp9(ctx); else { mfc_err("Unknown codec for encoding (%x).\n", ctx->codec_mode); @@ -2536,6 +2646,17 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev) R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10); R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10); + if (!IS_MFCV12(dev)) + goto done; + + /* Initialize registers used in MFC v10 only. + * Also, over-write the registers which have + * a different offset for MFC v10. + */ + + R(e_vp9_options, S5P_FIMV_E_VP9_OPTION_V12); + R(e_vp9_golden_frame_option, S5P_FIMV_E_VP9_GOLDEN_FRAME_OPTION_V12); + done: return &mfc_regs; #undef S5P_MFC_REG_ADDR From patchwork Tue Oct 11 12:25:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aakarsh Jain X-Patchwork-Id: 13004616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1450DC43217 for ; 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Tue, 11 Oct 2022 12:52:05 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20221011125205epsmtrp2d0a54e12893dd3f0d54a02f8b5be490c~dBM9W2zsl1820318203epsmtrp2A; Tue, 11 Oct 2022 12:52:05 +0000 (GMT) X-AuditID: b6c32a4b-383ff7000001dc20-4c-634638eb9c51 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id A0.94.18644.5F665436; Tue, 11 Oct 2022 21:52:05 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125202epsmtip1cc4f660560d47d8b9acfab3899e43525~dBM6NcmhG2345023450epsmtip1g; Tue, 11 Oct 2022 12:52:02 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 08/15] media: s5p-mfc: Add YV12 and I420 multiplanar format support Date: Tue, 11 Oct 2022 17:55:09 +0530 Message-Id: <20221011122516.32135-9-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VTe0xTVxjfuff2thiLNyjzSCaym40FNqAF2h0IDyOid8Iim9kjbobV9o4y Stu1xTGM4yWb1I6HQ6fIwPAYGSLvR0fRdaWT4AwbzoADOhkwGBIftJoRMLrSlu2/3/f7ft/5 ft93zuHhPjOkHy9dqWM1SomCJjcQPQNBQSGLaI9U0G+PRn8Zz3HQVHUPieqW5zF0u85BIEtn Nxd13TyPo8ZBMwfVWIc5qPfHaQK1/+3MjpyzEWi+pgWghco/SNQxM8pBf955B/3WV0UiQ1s3 B12y2rioYWwEQ992PMZQbfdDLiq6bOUiW38PQMc/t2I7IdNc3QwYo60eMGP1dpz5vtLGZer6 FzCmo6mYZCZH+0mmsz6XKfpphWBKupoA86TgGy6jt46RjKPDn7n2yMFN8T6YESNnJTJWE8Aq pSpZujItlk46kJqQKhILhCHCKPQqHaCUZLKx9O7klJA96QrnGuiAIxJFlpNKkWi1dFhcjEaV pWMD5CqtLpZm1TKFOlIdqpVkarOUaaFKVhctFAjCRU7hBxny6t5eoNavgOzVblEeePor0AMv HqQioflhJ0cPNvB8KBOAhskl0h3YASzLK8XcgQPAcaONu15SdsKOuxN9AM4OFxPuoAiD9wss LhVJhcAfGszkGt5C5QM4c0K3JsKpQgLarq+6RJupd6Fj4meXiKBehBNnHC6eT8XC5ooHpLvd DnixzYyvYS8qDi41XHUZhFShF/zq0RzhFu2GwwMmz0ib4Z3BLo9XP+i4d9lzkBTO1C7gbqyA rf0Vntp4aL5Z5cQ8p7sg2NoX5qa3w9PXWrA1jFPe8MvVWczN86Gxeh0HwqrJZY4bPwcHLjZ4 LDBwrKHas9VyAJduHCfLgH/l/y0uANAEtrFqbWYaqxWpI5TsJ/9dnFSV2QFcrz04yQimpx6E WgDGAxYAeTi9hQ9qdkl9+DLJpzmsRpWqyVKwWgsQORdYjvv5SlXO76LUpQojowSRYrE4MipC LKS38uvOBkt9qDSJjs1gWTWrWa/DeF5+edgu4HgB3EKPzYKVl6JiumxXwpYGElqDXmtbjjZM TC7G78gvoNtkd68ubvWfx18+5CNKMbEm0xuLCyXnA9/bdjhDt/x+jClxouqV3LS5wtGWkuFT e0eI4lPZ+9CNtw2G9qN+c9bwvXL9UF2pbOOBbE187RFOedj+7c/7FnNWqxqZGZNVoF7sDpeT l57y5ywWu6Z9/uBO2bi+a1NBwoWhqe9Ubx6r3HcF/pNI1fZa7kqb92/Mafzl64io1uv3hhI6 3xo/m5V/Sz1NfSwfFG/iHD15WB+e83vuFxX3n/EuTY+YGi77MDk0MTmh8LPwJ9ixUZHw2bii wNnXw5KWD92OUGMf+SbShFYuEQbjGq3kX5P7sll2BAAA X-Brightmail-Tracker: H4sIAAAAAAAAAzWRfUzMcRzHfX/PHfFz2fq6LNthOJWHie+kssb6mYdYYcPkVr87TXedux48 P1/LCU1pXdL1yPRg53T1o0NyysPoGutmXISWaibu8hCKrvnv/fm83nt9/vgwuLiQkDBJ6lRe q5YnSykRUX9fGhg8qFiVsMA2OBN1C0YSvS2up1D5jx4MvSl3E6j5hpVGdS8u4uhKaxOJTPZn JGq4945A1z/+o+1GF4F6TNcA6i3spJDlfQeJuvq2oOe3iiiUbbaSqNbuolGlsx1Dly2/MVRm 9dBIf9tOI5etHqCTmXZsBeRqimsAJ7gqAOes+IpzNwtdNFdu68U4S9UpinvdYaO4GxVHOP2D IYI7W1cFuOHjl2jOYHdSnNsSyD0edNMbJm4VLU/kk5PSee38iJ2iXcUNDUBjGAJ7f1lDj4IR BzAAHwayi2FO1lfcAESMmBUAPPnoHDkGpsGRzBZ6LPvBq8M99FjpBAbfua34KKDYYHi3soka BVNYPYDOq6ew0QFnLxLwx/kmr8qP3QyLDCavimBnwVf5bm/2ZcNhTd4ANXZiOqw2N3mtPmwE /FLZ4t2L/3WOfb6A5YCJJWBcFZjKa3QqpUq3ULNIzWeE6OQqXZpaGZKQorIA7/tkMgHYqgZC mgHGgGYAGVw6xReYohLEvonyfft5bUq8Ni2Z1zWDAIaQ+vs6DI/ixaxSnsrv5nkNr/1PMcZH chTLe/4ktI1vPHgmKuxcnTkmRaTRKxWOO9+X9UtvN9a2fGCS//gNw1LAz/25cjXJfcvO1m2d /4mNnFTT1R9kFoiHe4jG1ty+b8oZ8WHi1BP6mMPVeEFQ+KtbUmlwOyN0GT+uB3GFvyo2Lv1T 2u5IwlUKxSrSOsfnZ2Rafot7SUBW9KEAdcSBjrSyDFHgMXncjOgDRqO+f4csnZ8XOVvgjheE eqK7R1a0xrZ15o0rGZ+7LChx28rZpaULdqx9v9vhCTls6srPWXdPWOKviJdNN+2fcHYgK10S 5Tn49NqA8N3fGUBOcsd2bAqXZK65PjWpHJnjtneeXjQUVtb2ctgzeYOU0O2SL5ThWp38L/3R jTQtAwAA X-CMS-MailID: 20221011125205epcas5p2ebee35403cadc0c1c455b6764d93341f X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125205epcas5p2ebee35403cadc0c1c455b6764d93341f References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy YV12 and I420 format (3-plane) support is added. Stride information is added to all formats and planes since it is necessary for YV12/I420 which are different from width. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- .../platform/samsung/s5p-mfc/regs-mfc-v12.h | 2 + .../platform/samsung/s5p-mfc/regs-mfc-v7.h | 1 + .../platform/samsung/s5p-mfc/regs-mfc-v8.h | 3 + .../platform/samsung/s5p-mfc/s5p_mfc_common.h | 4 + .../platform/samsung/s5p-mfc/s5p_mfc_dec.c | 45 ++++- .../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 86 +++++++-- .../platform/samsung/s5p-mfc/s5p_mfc_opr.h | 6 +- .../platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c | 12 +- .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 168 +++++++++++++++--- 9 files changed, 281 insertions(+), 46 deletions(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h index 7cb74a9cb769..07cb218c0179 100644 --- a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h +++ b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h @@ -30,6 +30,8 @@ #define MFC_VERSION_V12 0xC0 #define MFC_NUM_PORTS_V12 1 #define S5P_FIMV_CODEC_VP9_ENC 27 +#define MFC_CHROMA_PAD_BYTES_V12 256 +#define S5P_FIMV_D_ALIGN_PLANE_SIZE_V12 256 /* Encoder buffer size for MFCv12 */ #define ENC_V120_BASE_SIZE(x, y) \ diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h index 4a7adfdaa359..50f9bf0603c1 100644 --- a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h +++ b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v7.h @@ -24,6 +24,7 @@ #define S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7 0xfa70 #define S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7 0xfa74 +#define S5P_FIMV_E_ENCODED_SOURCE_THIRD_ADDR_V7 0xfa78 #define S5P_FIMV_E_VP8_OPTIONS_V7 0xfdb0 #define S5P_FIMV_E_VP8_FILTER_OPTIONS_V7 0xfdb4 diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h index 162e3c7e920f..0ef9eb2dff22 100644 --- a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h +++ b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v8.h @@ -17,13 +17,16 @@ #define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8 0xf108 #define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8 0xf144 #define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8 0xf148 +#define S5P_FIMV_D_THIRD_PLANE_DPB_SIZE_V8 0xf14C #define S5P_FIMV_D_MV_BUFFER_SIZE_V8 0xf150 #define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8 0xf138 #define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8 0xf13c +#define S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE_V8 0xf140 #define S5P_FIMV_D_FIRST_PLANE_DPB_V8 0xf160 #define S5P_FIMV_D_SECOND_PLANE_DPB_V8 0xf260 +#define S5P_FIMV_D_THIRD_PLANE_DPB_V8 0xf360 #define S5P_FIMV_D_MV_BUFFER_V8 0xf460 #define S5P_FIMV_D_NUM_MV_V8 0xf134 diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h index 10abaa50d7db..f6ed3eeda6ba 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h @@ -56,6 +56,7 @@ #define MFC_NO_INSTANCE_SET -1 #define MFC_ENC_CAP_PLANE_COUNT 1 #define MFC_ENC_OUT_PLANE_COUNT 2 +#define VB2_MAX_PLANE_COUNT 3 #define STUFF_BYTE 4 #define MFC_MAX_CTRLS 147 @@ -182,6 +183,7 @@ struct s5p_mfc_buf { struct { size_t luma; size_t chroma; + size_t chroma_1; } raw; size_t stream; } cookie; @@ -682,6 +684,7 @@ struct s5p_mfc_ctx { int luma_size; int chroma_size; + int chroma_size_1; int mv_size; unsigned long consumed_stream; @@ -747,6 +750,7 @@ struct s5p_mfc_ctx { size_t scratch_buf_size; int is_10bit; int is_422; + int stride[VB2_MAX_PLANE_COUNT]; }; /* diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c index e219cbcd86d5..317f796fffa1 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_dec.c @@ -56,6 +56,20 @@ static struct s5p_mfc_fmt formats[] = { .num_planes = 2, .versions = MFC_V6PLUS_BITS, }, + { + .fourcc = V4L2_PIX_FMT_YUV420M, + .codec_mode = S5P_MFC_CODEC_NONE, + .type = MFC_FMT_RAW, + .num_planes = 3, + .versions = MFC_V12_BIT, + }, + { + .fourcc = V4L2_PIX_FMT_YVU420M, + .codec_mode = S5P_MFC_CODEC_NONE, + .type = MFC_FMT_RAW, + .num_planes = 3, + .versions = MFC_V12_BIT + }, { .fourcc = V4L2_PIX_FMT_H264, .codec_mode = S5P_MFC_CODEC_H264_DEC, @@ -359,10 +373,15 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f) /* Set pixelformat to the format in which MFC outputs the decoded frame */ pix_mp->pixelformat = ctx->dst_fmt->fourcc; - pix_mp->plane_fmt[0].bytesperline = ctx->buf_width; + pix_mp->plane_fmt[0].bytesperline = ctx->stride[0]; pix_mp->plane_fmt[0].sizeimage = ctx->luma_size; - pix_mp->plane_fmt[1].bytesperline = ctx->buf_width; + pix_mp->plane_fmt[1].bytesperline = ctx->stride[1]; pix_mp->plane_fmt[1].sizeimage = ctx->chroma_size; + if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) { + pix_mp->plane_fmt[2].bytesperline = ctx->stride[2]; + pix_mp->plane_fmt[2].sizeimage = ctx->chroma_size_1; + } } else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { /* This is run on OUTPUT The buffer contains compressed image @@ -937,6 +956,9 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq, vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { /* Output plane count is 2 - one for Y and one for CbCr */ *plane_count = 2; + if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + *plane_count = 3; /* Setup buffer count */ if (*buf_count < ctx->pb_count) *buf_count = ctx->pb_count; @@ -955,12 +977,17 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq, vq->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { psize[0] = ctx->luma_size; psize[1] = ctx->chroma_size; - + if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + psize[2] = ctx->chroma_size_1; if (IS_MFCV6_PLUS(dev)) alloc_devs[0] = ctx->dev->mem_dev[BANK_L_CTX]; else alloc_devs[0] = ctx->dev->mem_dev[BANK_R_CTX]; alloc_devs[1] = ctx->dev->mem_dev[BANK_L_CTX]; + if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + alloc_devs[2] = ctx->dev->mem_dev[BANK_L_CTX]; } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE && ctx->state == MFCINST_INIT) { psize[0] = ctx->dec_src_buf_size; @@ -994,12 +1021,24 @@ static int s5p_mfc_buf_init(struct vb2_buffer *vb) mfc_err("Plane buffer (CAPTURE) is too small\n"); return -EINVAL; } + if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) { + if (vb2_plane_size(vb, 2) < ctx->chroma_size_1) { + mfc_err("Plane buffer (CAPTURE) is too small\n"); + return -EINVAL; + } + } i = vb->index; ctx->dst_bufs[i].b = vbuf; ctx->dst_bufs[i].cookie.raw.luma = vb2_dma_contig_plane_dma_addr(vb, 0); ctx->dst_bufs[i].cookie.raw.chroma = vb2_dma_contig_plane_dma_addr(vb, 1); + if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) { + ctx->dst_bufs[i].cookie.raw.chroma_1 = + vb2_dma_contig_plane_dma_addr(vb, 2); + } ctx->dst_bufs_cnt++; } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { if (IS_ERR_OR_NULL(ERR_PTR( diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c index 197667ab1fbc..b761b9a31383 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c @@ -59,6 +59,20 @@ static struct s5p_mfc_fmt formats[] = { .num_planes = 2, .versions = MFC_V6PLUS_BITS, }, + { + .fourcc = V4L2_PIX_FMT_YUV420M, + .codec_mode = S5P_MFC_CODEC_NONE, + .type = MFC_FMT_RAW, + .num_planes = 3, + .versions = MFC_V12_BIT, + }, + { + .fourcc = V4L2_PIX_FMT_YVU420M, + .codec_mode = S5P_MFC_CODEC_NONE, + .type = MFC_FMT_RAW, + .num_planes = 3, + .versions = MFC_V12_BIT, + }, { .fourcc = V4L2_PIX_FMT_H264, .codec_mode = S5P_MFC_CODEC_H264_ENC, @@ -1369,14 +1383,20 @@ static int enc_pre_frame_start(struct s5p_mfc_ctx *ctx) struct s5p_mfc_dev *dev = ctx->dev; struct s5p_mfc_buf *dst_mb; struct s5p_mfc_buf *src_mb; - unsigned long src_y_addr, src_c_addr, dst_addr; + unsigned long src_y_addr, src_c_addr, src_c_1_addr, dst_addr; unsigned int dst_size; src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); src_y_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 0); src_c_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 1); + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + src_c_1_addr = + vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 2); + else + src_c_1_addr = 0; s5p_mfc_hw_call(dev->mfc_ops, set_enc_frame_buffer, ctx, - src_y_addr, src_c_addr); + src_y_addr, src_c_addr, src_c_1_addr); dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0); @@ -1391,8 +1411,8 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx) { struct s5p_mfc_dev *dev = ctx->dev; struct s5p_mfc_buf *mb_entry; - unsigned long enc_y_addr = 0, enc_c_addr = 0; - unsigned long mb_y_addr, mb_c_addr; + unsigned long enc_y_addr = 0, enc_c_addr = 0, enc_c_1_addr = 0; + unsigned long mb_y_addr, mb_c_addr, mb_c_1_addr; int slice_type; unsigned int strm_size; @@ -1404,14 +1424,21 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx) mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT)); if (slice_type >= 0) { s5p_mfc_hw_call(dev->mfc_ops, get_enc_frame_buffer, ctx, - &enc_y_addr, &enc_c_addr); + &enc_y_addr, &enc_c_addr, &enc_c_1_addr); list_for_each_entry(mb_entry, &ctx->src_queue, list) { mb_y_addr = vb2_dma_contig_plane_dma_addr( &mb_entry->b->vb2_buf, 0); mb_c_addr = vb2_dma_contig_plane_dma_addr( &mb_entry->b->vb2_buf, 1); - if ((enc_y_addr == mb_y_addr) && - (enc_c_addr == mb_c_addr)) { + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + mb_c_1_addr = vb2_dma_contig_plane_dma_addr + (&mb_entry->b->vb2_buf, 2); + else + mb_c_1_addr = 0; + if ((enc_y_addr == mb_y_addr) + && (enc_c_addr == mb_c_addr) + && (enc_c_1_addr == mb_c_1_addr)) { list_del(&mb_entry->list); ctx->src_queue_cnt--; vb2_buffer_done(&mb_entry->b->vb2_buf, @@ -1424,8 +1451,15 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx) &mb_entry->b->vb2_buf, 0); mb_c_addr = vb2_dma_contig_plane_dma_addr( &mb_entry->b->vb2_buf, 1); - if ((enc_y_addr == mb_y_addr) && - (enc_c_addr == mb_c_addr)) { + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + mb_c_1_addr = vb2_dma_contig_plane_dma_addr( + &mb_entry->b->vb2_buf, 2); + else + mb_c_1_addr = 0; + if ((enc_y_addr == mb_y_addr) + && (enc_c_addr == mb_c_addr) + && (enc_c_1_addr == mb_c_1_addr)) { list_del(&mb_entry->list); ctx->ref_queue_cnt--; vb2_buffer_done(&mb_entry->b->vb2_buf, @@ -1549,10 +1583,15 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f) pix_fmt_mp->pixelformat = ctx->src_fmt->fourcc; pix_fmt_mp->num_planes = ctx->src_fmt->num_planes; - pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width; + pix_fmt_mp->plane_fmt[0].bytesperline = ctx->stride[0]; pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size; - pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width; + pix_fmt_mp->plane_fmt[1].bytesperline = ctx->stride[1]; pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size; + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) { + pix_fmt_mp->plane_fmt[2].bytesperline = ctx->stride[2]; + pix_fmt_mp->plane_fmt[2].sizeimage = ctx->chroma_size_1; + } } else { mfc_err("invalid buf type\n"); return -EINVAL; @@ -1636,9 +1675,14 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f) s5p_mfc_hw_call(dev->mfc_ops, enc_calc_src_size, ctx); pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size; - pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width; + pix_fmt_mp->plane_fmt[0].bytesperline = ctx->stride[0]; pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size; - pix_fmt_mp->plane_fmt[1].bytesperline = ctx->buf_width; + pix_fmt_mp->plane_fmt[1].bytesperline = ctx->stride[1]; + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) { + pix_fmt_mp->plane_fmt[2].bytesperline = ctx->stride[2]; + pix_fmt_mp->plane_fmt[2].sizeimage = ctx->chroma_size_1; + } ctx->src_bufs_cnt = 0; ctx->output_state = QUEUE_FREE; @@ -2679,10 +2723,16 @@ static int s5p_mfc_queue_setup(struct vb2_queue *vq, psize[0] = ctx->luma_size; psize[1] = ctx->chroma_size; + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + psize[2] = ctx->chroma_size_1; if (IS_MFCV6_PLUS(dev)) { alloc_devs[0] = ctx->dev->mem_dev[BANK_L_CTX]; alloc_devs[1] = ctx->dev->mem_dev[BANK_L_CTX]; + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + alloc_devs[2] = ctx->dev->mem_dev[BANK_L_CTX]; } else { alloc_devs[0] = ctx->dev->mem_dev[BANK_R_CTX]; alloc_devs[1] = ctx->dev->mem_dev[BANK_R_CTX]; @@ -2721,6 +2771,10 @@ static int s5p_mfc_buf_init(struct vb2_buffer *vb) vb2_dma_contig_plane_dma_addr(vb, 0); ctx->src_bufs[i].cookie.raw.chroma = vb2_dma_contig_plane_dma_addr(vb, 1); + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + ctx->src_bufs[i].cookie.raw.chroma_1 = + vb2_dma_contig_plane_dma_addr(vb, 2); ctx->src_bufs_cnt++; } else { mfc_err("invalid queue type: %d\n", vq->type); @@ -2758,6 +2812,12 @@ static int s5p_mfc_buf_prepare(struct vb2_buffer *vb) mfc_err("plane size is too small for output\n"); return -EINVAL; } + if ((ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) && + (vb2_plane_size(vb, 2) < ctx->chroma_size_1)) { + mfc_err("plane size is too small for output\n"); + return -EINVAL; + } } else { mfc_err("invalid queue type: %d\n", vq->type); return -EINVAL; diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h index a005623e2daa..700704985c26 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h @@ -295,9 +295,11 @@ struct s5p_mfc_hw_ops { int (*set_enc_stream_buffer)(struct s5p_mfc_ctx *ctx, unsigned long addr, unsigned int size); void (*set_enc_frame_buffer)(struct s5p_mfc_ctx *ctx, - unsigned long y_addr, unsigned long c_addr); + unsigned long y_addr, unsigned long c_addr, + unsigned long c_1_addr); void (*get_enc_frame_buffer)(struct s5p_mfc_ctx *ctx, - unsigned long *y_addr, unsigned long *c_addr); + unsigned long *y_addr, unsigned long *c_addr, + unsigned long *c_1_addr); void (*try_run)(struct s5p_mfc_dev *dev); void (*clear_int_flags)(struct s5p_mfc_dev *dev); int (*get_dspl_y_adr)(struct s5p_mfc_dev *dev); diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c index 28a06dc343fd..fcfaf125a5a1 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v5.c @@ -516,7 +516,8 @@ static int s5p_mfc_set_enc_stream_buffer_v5(struct s5p_mfc_ctx *ctx, } static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx, - unsigned long y_addr, unsigned long c_addr) + unsigned long y_addr, unsigned long c_addr, + unsigned long c_1_addr) { struct s5p_mfc_dev *dev = ctx->dev; @@ -525,7 +526,8 @@ static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx, } static void s5p_mfc_get_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx, - unsigned long *y_addr, unsigned long *c_addr) + unsigned long *y_addr, unsigned long *c_addr, + unsigned long *c_1_addr) { struct s5p_mfc_dev *dev = ctx->dev; @@ -1210,7 +1212,7 @@ static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) if (list_empty(&ctx->src_queue)) { /* send null frame */ s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->dma_base[BANK_R_CTX], - dev->dma_base[BANK_R_CTX]); + dev->dma_base[BANK_R_CTX], 0); src_mb = NULL; } else { src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, @@ -1220,7 +1222,7 @@ static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) /* send null frame */ s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->dma_base[BANK_R_CTX], - dev->dma_base[BANK_R_CTX]); + dev->dma_base[BANK_R_CTX], 0); ctx->state = MFCINST_FINISHING; } else { src_y_addr = vb2_dma_contig_plane_dma_addr( @@ -1228,7 +1230,7 @@ static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) src_c_addr = vb2_dma_contig_plane_dma_addr( &src_mb->b->vb2_buf, 1); s5p_mfc_set_enc_frame_buffer_v5(ctx, src_y_addr, - src_c_addr); + src_c_addr, 0); if (src_mb->flags & MFC_BUF_FLAG_EOS) ctx->state = MFCINST_FINISHING; } diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c index 87bd10b34620..27c2ada381ec 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c @@ -506,16 +506,43 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx) struct s5p_mfc_dev *dev = ctx->dev; ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6); ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6); + ctx->chroma_size_1 = 0; mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n" "buffer dimensions: %dx%d\n", ctx->img_width, ctx->img_height, ctx->buf_width, ctx->buf_height); - ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height); - ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1)); + switch (ctx->dst_fmt->fourcc) { + case V4L2_PIX_FMT_NV12M: + case V4L2_PIX_FMT_NV21M: + ctx->stride[0] = ALIGN(ctx->img_width, + S5P_FIMV_NV12MT_HALIGN_V6); + ctx->stride[1] = ALIGN(ctx->img_width, + S5P_FIMV_NV12MT_HALIGN_V6); + ctx->luma_size = calc_plane(ctx->stride[0], ctx->img_height); + ctx->chroma_size = calc_plane(ctx->stride[1], + (ctx->img_height / 2)); + break; + case V4L2_PIX_FMT_YUV420M: + case V4L2_PIX_FMT_YVU420M: + ctx->stride[0] = ALIGN(ctx->img_width, + S5P_FIMV_NV12MT_HALIGN_V6); + ctx->stride[1] = ALIGN(ctx->img_width / 2, + S5P_FIMV_NV12MT_HALIGN_V6); + ctx->stride[2] = ALIGN(ctx->img_width / 2, + S5P_FIMV_NV12MT_HALIGN_V6); + ctx->luma_size = calc_plane(ctx->stride[0], ctx->img_height); + ctx->chroma_size = calc_plane(ctx->stride[1], + (ctx->img_height / 2)); + ctx->chroma_size_1 = calc_plane(ctx->stride[2], + (ctx->img_height / 2)); + break; + } + if (IS_MFCV8_PLUS(ctx->dev)) { /* MFCv8 needs additional 64 bytes for luma,chroma dpb*/ ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8; ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8; + ctx->chroma_size_1 += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8; } if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || @@ -546,15 +573,53 @@ static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx) mb_width = MB_WIDTH(ctx->img_width); mb_height = MB_HEIGHT(ctx->img_height); - ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6); - ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256); - ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256); - - /* MFCv7 needs pad bytes for Luma and Chroma */ - if (IS_MFCV7_PLUS(ctx->dev)) { + if (IS_MFCV12(ctx->dev)) { + switch (ctx->src_fmt->fourcc) { + case V4L2_PIX_FMT_NV12M: + case V4L2_PIX_FMT_NV21M: + ctx->stride[0] = ALIGN(ctx->img_width, + S5P_FIMV_NV12M_HALIGN_V6); + ctx->stride[1] = ALIGN(ctx->img_width, + S5P_FIMV_NV12M_HALIGN_V6); + ctx->luma_size = ctx->stride[0] * + ALIGN(ctx->img_height, 16); + ctx->chroma_size = ctx->stride[0] * + ALIGN(ctx->img_height / 2, 16); + break; + case V4L2_PIX_FMT_YUV420M: + case V4L2_PIX_FMT_YVU420M: + ctx->stride[0] = ALIGN(ctx->img_width, + S5P_FIMV_NV12M_HALIGN_V6); + ctx->stride[1] = ALIGN(ctx->img_width / 2, + S5P_FIMV_NV12M_HALIGN_V6); + ctx->stride[2] = ALIGN(ctx->img_width / 2, + S5P_FIMV_NV12M_HALIGN_V6); + ctx->luma_size = ctx->stride[0] * + ALIGN(ctx->img_height, 16); + ctx->chroma_size = ctx->stride[1] * + ALIGN(ctx->img_height / 2, 16); + ctx->chroma_size_1 = ctx->stride[2] * + ALIGN(ctx->img_height / 2, 16); + break; + } ctx->luma_size += MFC_LUMA_PAD_BYTES_V7; - ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V7; + ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V12; + ctx->chroma_size_1 += MFC_CHROMA_PAD_BYTES_V12; + } else { + ctx->buf_width = ALIGN(ctx->img_width, + S5P_FIMV_NV12M_HALIGN_V6); + ctx->stride[0] = ctx->buf_width; + ctx->stride[1] = ctx->buf_width; + ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256); + ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256); + ctx->chroma_size_1 = 0; + /* MFCv7 needs pad bytes for Luma and Chroma */ + if (IS_MFCV7_PLUS(ctx->dev)) { + ctx->luma_size += MFC_LUMA_PAD_BYTES_V7; + ctx->chroma_size += MFC_LUMA_PAD_BYTES_V7; + } } + } /* Set registers for decoding stream buffer */ @@ -600,15 +665,21 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx) writel(ctx->total_dpb_count, mfc_regs->d_num_dpb); writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size); writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size); - + if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + writel(ctx->chroma_size_1, mfc_regs->d_third_plane_dpb_size); writel(buf_addr1, mfc_regs->d_scratch_buffer_addr); writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size); if (IS_MFCV8_PLUS(dev)) { - writel(ctx->img_width, + writel(ctx->stride[0], mfc_regs->d_first_plane_dpb_stride_size); - writel(ctx->img_width, + writel(ctx->stride[1], mfc_regs->d_second_plane_dpb_stride_size); + if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + writel(ctx->stride[2], + mfc_regs->d_third_plane_dpb_stride_size); } buf_addr1 += ctx->scratch_buf_size; @@ -637,6 +708,13 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx) ctx->dst_bufs[i].cookie.raw.chroma); writel(ctx->dst_bufs[i].cookie.raw.chroma, mfc_regs->d_second_plane_dpb + i * 4); + if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) { + mfc_debug(2, "\tChroma_1 %d: %zx\n", i, + ctx->dst_bufs[i].cookie.raw.chroma_1); + writel(ctx->dst_bufs[i].cookie.raw.chroma_1, + mfc_regs->d_third_plane_dpb + i * 4); + } } if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC || @@ -695,20 +773,24 @@ static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx, } static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx, - unsigned long y_addr, unsigned long c_addr) + unsigned long y_addr, unsigned long c_addr, + unsigned long c_1_addr) { struct s5p_mfc_dev *dev = ctx->dev; const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; writel(y_addr, mfc_regs->e_source_first_plane_addr); writel(c_addr, mfc_regs->e_source_second_plane_addr); + writel(c_1_addr, mfc_regs->e_source_third_plane_addr); mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr); mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr); + mfc_debug(2, "enc src cr buf addr: 0x%08lx\n", c_1_addr); } static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx, - unsigned long *y_addr, unsigned long *c_addr) + unsigned long *y_addr, unsigned long *c_addr, + unsigned long *c_1_addr) { struct s5p_mfc_dev *dev = ctx->dev; const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; @@ -716,12 +798,17 @@ static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx, *y_addr = readl(mfc_regs->e_encoded_source_first_plane_addr); *c_addr = readl(mfc_regs->e_encoded_source_second_plane_addr); + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + *c_1_addr = readl(mfc_regs->e_encoded_source_third_plane_addr); + else + *c_1_addr = 0; enc_recon_y_addr = readl(mfc_regs->e_recon_luma_dpb_addr); enc_recon_c_addr = readl(mfc_regs->e_recon_chroma_dpb_addr); mfc_debug(2, "recon y addr: 0x%08lx y_addr: 0x%08lx\n", enc_recon_y_addr, *y_addr); - mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr); + mfc_debug(2, "recon c addr: 0x%08lx c_addr: 0x%08lx\n", enc_recon_c_addr, *c_addr); } /* Set encoding ref & codec buffer */ @@ -898,6 +985,20 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) writel(reg, mfc_regs->e_enc_options); /* 0: NV12(CbCr), 1: NV21(CrCb) */ writel(0x0, mfc_regs->pixel_format); + } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) { + /* 0: Linear, 1: 2D tiled*/ + reg = readl(mfc_regs->e_enc_options); + reg &= ~(0x1 << 7); + writel(reg, mfc_regs->e_enc_options); + /* 2: YV12(CrCb), 3: I420(CrCb) */ + writel(0x2, mfc_regs->pixel_format); + } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M) { + /* 0: Linear, 1: 2D tiled*/ + reg = readl(mfc_regs->e_enc_options); + reg &= ~(0x1 << 7); + writel(reg, mfc_regs->e_enc_options); + /* 2: YV12(CrCb), 3: I420(CrCb) */ + writel(0x3, mfc_regs->pixel_format); } /* memory structure recon. frame */ @@ -1804,8 +1905,12 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx) else writel(reg, mfc_regs->d_dec_options); - /* 0: NV12(CbCr), 1: NV21(CrCb) */ - if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M) + /* 0: NV12(CbCr), 1: NV21(CrCb), 2: YV12(CrCb), 3: I420(CbCr) */ + if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M) + writel(0x3, mfc_regs->pixel_format); + else if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + writel(0x2, mfc_regs->pixel_format); + else if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M) writel(0x1, mfc_regs->pixel_format); else writel(0x0, mfc_regs->pixel_format); @@ -1891,8 +1996,12 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx) /* Set stride lengths for v7 & above */ if (IS_MFCV7_PLUS(dev)) { - writel(ctx->img_width, mfc_regs->e_source_first_plane_stride); - writel(ctx->img_width, mfc_regs->e_source_second_plane_stride); + writel(ctx->stride[0], mfc_regs->e_source_first_plane_stride); + writel(ctx->stride[1], mfc_regs->e_source_second_plane_stride); + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + writel(ctx->stride[2], + mfc_regs->e_source_third_plane_stride); } writel(ctx->inst_no, mfc_regs->instance_id); @@ -2001,7 +2110,7 @@ static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) struct s5p_mfc_dev *dev = ctx->dev; struct s5p_mfc_buf *dst_mb; struct s5p_mfc_buf *src_mb; - unsigned long src_y_addr, src_c_addr, dst_addr; + unsigned long src_y_addr, src_c_addr, src_c_1_addr, dst_addr; /* unsigned int src_y_size, src_c_size; */ @@ -2019,22 +2128,29 @@ static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) if (list_empty(&ctx->src_queue)) { /* send null frame */ - s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0); + s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0); src_mb = NULL; } else { src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); src_mb->flags |= MFC_BUF_FLAG_USED; if (src_mb->b->vb2_buf.planes[0].bytesused == 0) { - s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0); + s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0); ctx->state = MFCINST_FINISHING; } else { src_y_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 0); src_c_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 1); + if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || + ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) + src_c_1_addr = vb2_dma_contig_plane_dma_addr + (&src_mb->b->vb2_buf, 2); + else + src_c_1_addr = 0; mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr); mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr); - s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr); + s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, + src_c_addr, src_c_1_addr); if (src_mb->flags & MFC_BUF_FLAG_EOS) ctx->state = MFCINST_FINISHING; } @@ -2560,6 +2676,8 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev) S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7); R(e_encoded_source_second_plane_addr, S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7); + R(e_encoded_source_third_plane_addr, + S5P_FIMV_E_ENCODED_SOURCE_THIRD_ADDR_V7); R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7); if (!IS_MFCV8_PLUS(dev)) @@ -2574,16 +2692,20 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev) R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V8); R(d_first_plane_dpb_size, S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8); R(d_second_plane_dpb_size, S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8); + R(d_third_plane_dpb_size, S5P_FIMV_D_THIRD_PLANE_DPB_SIZE_V8); R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8); R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8); R(d_first_plane_dpb_stride_size, S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8); R(d_second_plane_dpb_stride_size, S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8); + R(d_third_plane_dpb_stride_size, + S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE_V8); R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V8); R(d_num_mv, S5P_FIMV_D_NUM_MV_V8); R(d_first_plane_dpb, S5P_FIMV_D_FIRST_PLANE_DPB_V8); R(d_second_plane_dpb, S5P_FIMV_D_SECOND_PLANE_DPB_V8); + R(d_third_plane_dpb, S5P_FIMV_D_THIRD_PLANE_DPB_V8); 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Tue, 11 Oct 2022 21:52:08 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125205epsmtip14547c1b5301cedcadd47448896d0f682~dBM9ZM6dk2178621786epsmtip1t; Tue, 11 Oct 2022 12:52:05 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 09/15] media: s5p-mfc: Add support for rate controls in MFCv12 Date: Tue, 11 Oct 2022 17:55:10 +0530 Message-Id: <20221011122516.32135-10-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTf0xbVRTHc/teX9vFkke3uSthwN6iMsKvOiiXCUiQsGeYBiXbdMaw2j4B Ka9NW5BtccAYAwpuEIQwREBKYfzYmAyQX0qBCgtR4uYoYdKxDQH5kf0ooEzItKWg/33Oud+T 8z3n3svHRFOECz+R1TJqVqqgiB14x+ABL5/HKErmXzqyB810Xuai+5UdBNKvzXHQlH4ZRwM3 2nmo7c5XGKofNnJRlWmUi77rf4ijb/+wnd66bMHRXNU1gObL7xGoddrMRQ8WjqNfuysIVHC9 nYuumiw8ZBi/xUF1rRscVNO+wkPZ35t4yNLbAdD5CyZOOKSbK5sB3WmpBfR4rRWju8otPFrf O8+hWxvzCHrS3EvQN2rT6ewf/8bpi22NgH5+7mserTONE/Ryqxs9srrMi3E6kRSSwEjljNqD YWVKeSIbH0pFx8a9GRco8Rf7iINREOXBSpOZUCrySIxPVKLCtgbKI1WqSLGlYqQaDeUXFqJW pmgZjwSlRhtKMSq5QhWg8tVIkzUpbLwvy2gPif39Xwu0CU8mJVhm0lVXnNP6C7qIDNDjpAMC PiQDYENdBqYDO/gisgfAm7/kE47ACmDP4gZXB/i2YBnAtk+2C/Q3K7gOTTeAxqfrW0E2B3Zn ZfHsKoL0gX0GI2HnXWQmgNO5WrsII7NwaPlpfVO0k4yF1tVnm4yTL8Pbxb8BOwvJMLg0PMpx tHOHTdeNmJ0FtvxTw9CmPUjmCGChsY9wiCKhId/AdfBOuDDcxnOwC5y/dGGLZXC6Zh5zsAK2 9H6JO/gNaLxTgdvHxMgDsKXbz5HeC0tGrm16wEgn+MX671t+hLCzcptfgRWTa1ttXeFgkwE4 mIaZ1T8Dx1aKABwbM/MKgVv5/y2qAWgELzEqTXI8owlUHWSZz/67NJkyuRVsvnSv6E7w8P4T 3wHA4YMBAPkYtUsIqiJkIqFceuo0o1bGqVMUjGYABNoWWIS57JYpbV+F1caJA4L9AyQSSUDw QYmY2iPUl3nJRGS8VMskMYyKUW/XcfgClwzO8Y1LXYv7PYnMR2Xo7tH43CDPs+n5g4c9V5QN i88/HjS6jw/lbuQg539O/akDaaNd9yhX53PfyM8UlfiZYt96tS7oblNHSHWNzu1EC5a6P3uo zpXNp1hq7FPXyqoPc/c1JJmLSoVls6dfr3t2MaL5UUvX29G3OydefEFgnipc/+CHEsXMyZwI Itx9JCjBeyLCvFpw9Z0a7+KjWPhfkWH1a/sk7qL38spSegfCZ8/zlUbrbN5K/7EHwoXS0isf 8Wfy3Tpi9XMTgqzaqUKXJTUr6i8+Etz4+SDeB3fPHMsOtry7EeYjf5yUGmVdq146E+VtSSPZ mr1ph6rfDwNnpU8my+opXJMgFXthao30XxaBCU9yBAAA X-Brightmail-Tracker: H4sIAAAAAAAAAzWRa0hTYRjHe8/OzjkKynEWvq2oWF7Aysoi3qjECuEoBSZlKEUNPfOSm7Jl 2kW00uVMorIkb008XpeWzUvTVumczm7qslxaS7uYZWKmFmaiNaVvv+f5/fk/Hx6KJ7iBC6ko 2XFWLhPHiAh7vL5FtGLdlMQvbIOpZhsa1OXw0cDNegJxU0MY6ucmcGSoqSNR7cs8HiozNfGR 2tjBR/eaP+Do7pd/1pxjxdGQ+jZAX3PfEUj7sYeP3g8fRN2N+QTKrK7joyqjlUQlFjOGSrUz GCqqmyRR2gMjiaz6eoBSlUbMFzKVNysBo7MWA8ZSPM5jGnKtJMPpv2KMVqMimLc9eoKpKU5m 0lqnceZSrQYws+cKSCbDaCGYCe0K5snPCTLQMdR+ezgbE3WCla/3OWofaR1Mjit3SmzObCBS wH3HDGBHQXoz5Nrz+RnAnhLQOgALJzp5C2I5nFO2kQvsDCtmh8iF0HkMGip750MEvQ4+Kmki bGIxnQagpUKF2QYenYfDqatNfFvKmd4H+8Z+z1fhtBt8kfUG2NiB9oEjpg5s4cRKeKu6ab7V 7t/+R0kbYWMBvQOe/X4duwwcC8EiDVjKximkEVLFxjhvGZvgpRBLFfGyCK+wWKkWzD/P01MH 9JoxLwPAKGAAkOKJFjsA9a4wgUO4+OQpVh57RB4fwyoMYBmFi1wcujIeHxHQEeLj7DGWjWPl /y1G2QlTMEn6p9nWU6+fmXtHx/V1S3JyhY8LvlBYb+7ZMn99AHT9XFj+KCjwjJNH61OXKnzv r2ivi2+chXMd+jTp5NiBCoHK9eEkiW9PLeJ2P/fNQ07uLVOgS7Lnifuhxt0hgZ4JYdyMaEap 3hkyh+83p2p7kpUBu7g7r1IMfTnBtcHX9m2JpxMjvZM6OA8/f1N7jMr0J0utCfX2k0WeTDrv mx6kcePUKl9V1OBwb3epZWt/QcnrC398hkdiWeroiMvq6TVr+82Sw4GT8k53y+npnsaBmkyx VJU98KvZ9UqfUhD9Q9c5XhrUPjoaf27TpwcoKVvoH3Q6ZYtE/l39rTRatkqEKyLFGz15coX4 L6Z0czkrAwAA X-CMS-MailID: 20221011125209epcas5p1518083b1a20d015021ec5f08c832fae3 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125209epcas5p1518083b1a20d015021ec5f08c832fae3 References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy In MFCv12, the rc configs are changed with support for CBR loose, CBR tight and Variable Bitrate (VBR) added. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 22 +++++++++++++++---- .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h | 1 + 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c index 27c2ada381ec..2194df7b6fbf 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c @@ -1037,10 +1037,24 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) /* reaction coefficient */ if (p->rc_frame) { - if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */ - writel(1, mfc_regs->e_rc_mode); - else /* loose CBR */ - writel(2, mfc_regs->e_rc_mode); + if (IS_MFCV12(dev)) { + /* loose CBR */ + if (p->rc_reaction_coeff < LOOSE_CBR_MAX) + writel(1, mfc_regs->e_rc_mode); + /* tight CBR */ + else if (p->rc_reaction_coeff < TIGHT_CBR_MAX) + writel(0, mfc_regs->e_rc_mode); + /* VBR */ + else + writel(2, mfc_regs->e_rc_mode); + } else { + /* tight CBR */ + if (p->rc_reaction_coeff < TIGHT_CBR_MAX) + writel(1, mfc_regs->e_rc_mode); + /* loose CBR */ + else + writel(2, mfc_regs->e_rc_mode); + } } /* seq header ctrl */ diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h index 30269f3e68e8..24752a712fbf 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h @@ -40,6 +40,7 @@ #define ENC_H264_LEVEL_MAX 42 #define ENC_MPEG4_VOP_TIME_RES_MAX ((1 << 16) - 1) #define FRAME_DELTA_H264_H263 1 +#define LOOSE_CBR_MAX 5 #define TIGHT_CBR_MAX 10 #define ENC_HEVC_RC_FRAME_RATE_MAX ((1 << 16) - 1) #define ENC_HEVC_QP_INDEX_MIN -12 From patchwork Tue Oct 11 12:25:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aakarsh Jain X-Patchwork-Id: 13004617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82A06C43217 for ; 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Tue, 11 Oct 2022 12:52:12 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20221011125212epsmtrp2a81dc7a3681b22dfe7a95392b9d30525~dBNDmwgc61820118201epsmtrp2L; Tue, 11 Oct 2022 12:52:12 +0000 (GMT) X-AuditID: b6c32a49-319fb70000016970-7d-634638f12efe Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id B4.94.18644.CF665436; Tue, 11 Oct 2022 21:52:12 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125209epsmtip1f5d69eb6332f326b9fbbd3bba1d8c70b~dBNAiJK5G2675426754epsmtip1K; Tue, 11 Oct 2022 12:52:09 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 10/15] media: s5p-mfc: Add support for UHD encoding. Date: Tue, 11 Oct 2022 17:55:11 +0530 Message-Id: <20221011122516.32135-11-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTf1STVRjHz33fd+876AxeQOnGScP3CEd3Ymw45qVALJVeT+nBQydOFq6d 7Q2Isc1tkD86ZSlYCKZhx/FDIAZqoGATkGDqHENOSKBCYOkSQflhBw0WHY5itDGo/z7P936f 57n3uffy8cBBMoSfrjFyeo1CzZC+RFPbamHEJEpQils6o9CD5iIeGixrIpF5ZhRDd80uAtnP N1Kooa8ER6c6bDxU7ujmoQtXhgj0w5h79UaRk0Cj5XUAjRf/TiLLcD8P3XuYjHpbSkmUf66R h846nBSqHriBoZOWWQxVNv5FoZyLDgo5rU0AHch1YOshe6bsDGCbnVWAHaiawtkfi50Ua7aO Y6yl5iuSvdNvJdnzVZ+xOe1PCPZwQw1g//niBMXmOQZI1mVZznZOu6hEv+0ZsWmcQsXpQzmN UqtK16TGMW8myTfIo2ViSYQkBq1lQjWKTC6O2fhWYkRCuto9BiY0W6HOckuJCoOBiVwXq9dm GbnQNK3BGMdwOpVaJ9WJDIpMQ5YmVaThjK9IxOKoaLfxg4w0W1c/ppsJ2DV338TbBw765wE+ H9JSWGuLzgO+/EC6FcCTX3eS3mAKwCPmEsobuACsKbGCxQzbk2Cv3gLgqbpbuDfIwWDhzV/c gQ+fpCPg5Wob6eEl9OcADn9p9Jhwej8BnV1PKc9CEP0GnJzrAx4m6DD484PHhIcF9DroaDLN J0P6JVh7zjZf1MetT1Zfnd8fpA/5wLPfFWBe00Z48FEJ4eUg+LCjgfJyCHQ9urhQSAmHK8dx L6thvfXYgj8e2vpKCc/RcHo1rG+J9MrL4LeddfPlcdoPFjy9v9BKAJvLFjkclt6Z4Xn5RdhW Ww28zMKO2YqFqRwFsPK3bnAELC/+v0UFADXgBU5nyEzlDNE6iYb7+L9bU2ozLWD+qQs3NwPn 4J8iO8D4wA4gH2eWCED568pAgUqxew+n18r1WWrOYAfR7gEexUOWKrXuv6IxyiXSGLFUJpNJ Y9bIJMzzArNJqAykUxVGLoPjdJx+MQ/j+4Tsw1LCLjfGDiclPvObxK5tVk1c+PXV4Lj4gC35 bZuUKHtXQkerZizKtDY/s+fd8Eu54SPXXBsmkuPy946KWnfsXWWWBqT8ZDfXGl7eNlthufuY /mRZ8Yh1OmcaHOsR4Tbh+3OFal1C6jdjfwjkh+yOKyaKk5Xr5TvE8ehA0nH9UH1b3c6V3XsI 6crICY3pvbrdg5fW7ARFwunxrYf811NbPhT63jyRH2wNuh7WI5yKPc4EFQS8s39F1qcfvV2S q5gqG7n3/eT1lCH17RWvJf9dtS3xOVOpP90enKTCbm/SpTsiAk8HLe2tvDrWO7a9pt1Fbs1O aO5qOD1AriJuZWSLfAqVzxjCkKaQCHG9QfEvNeWC1XMEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBIsWRmVeSWpSXmKPExsWy7bCSnO6fNNdkg2MfRSye7pjJavFg3jY2 i8U/njNZ3F/8mcXi0Oat7BZbrsxmtlh+/ACrxfwj51gtth98xGKx8QVQ9uLMuywWz+evY7R4 Oesem8Wmx9dYLR6+Cre4vGsOm0XPhq2sFmuP3GW3WHr9IpPFsk1/mCwWbf3CbtG69wi7xd09 2xgtWtqOMDlIeKyZt4bRY8fdJYwe15d8YvbYOesuu8fiPS+ZPDat6mTzuHNtD5vH5iX1Hq1H f7F49G1Zxejxr2kuu0fXketsHp83yXmc+vqZPYAvissmJTUnsyy1SN8ugSvjwJlrTAU/BCv+ P5nB2sDYzt/FyMEhIWAiceCXWBcjF4eQwA5Gid33pzJ3MXICxWUk/rcdY4ewhSVW/nvODlHU zCTx/uhUNpAEm4CuxP6lB9hAEiICrYwS11d2MoE4zAKzWSR+TDrAClIlLOAu8fH/FUYQm0VA VeLs0/csIDavgJ3EkW0z2CBWyEus3nAAbDUnUPzj0mNgcSEBW4nG91OZJjDyLWBkWMUomVpQ nJueW2xYYJSXWq5XnJhbXJqXrpecn7uJERx5Wlo7GPes+qB3iJGJg/EQowQHs5IIL+N8p2Qh 3pTEyqrUovz4otKc1OJDjNIcLErivBe6TsYLCaQnlqRmp6YWpBbBZJk4OKUamAzktVfPEfxy 4/EFt87Ofxv01V/X8fvIiZ1QSJ2ofodzkuEdkVcNn1i+rcgKY21P/f75WmL72kWTlnGbfioJ +sX60lDKYla21T/XCatDF85t2aLiw2V2Y2HD+kiztveLr3+VrGLIspeb/W3FecEGuze9TCIy qzaFaKs6Vs7LVVItNFi3xCOQ1eLYBtP/E673nE/N6uzl27svKm+5/Idr/xbHFLrJaHa//v/s wkahh59mvH1mV7ngdJ/M6a75ZqLedryhnGezvewWTQ6SjN2sG/M4tzdhvnLN/+l7y40c5cJ5 HQ/a7CoIZ3ntp8Q39Xr0HI3lb4O47p++2e206kmo3FTZ1X4S3GcPtF4Nf9G+XImlOCPRUIu5 qDgRABFHIC8rAwAA X-CMS-MailID: 20221011125212epcas5p2b39bc34805f63de7da5b4a098f10689f X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125212epcas5p2b39bc34805f63de7da5b4a098f10689f References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy MFC driver had restriction on max resolution of 1080p, updated it for UHD. Added corresponding support to set recommended profile and level for H264 in UHD scenario. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c | 9 ++++++--- .../media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 12 ++++++++++++ 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c index b761b9a31383..f953a3ed7f20 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c @@ -1628,9 +1628,12 @@ static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f) mfc_err("Unsupported format by this MFC version.\n"); return -EINVAL; } - - v4l_bound_align_image(&pix_fmt_mp->width, 8, 1920, 1, - &pix_fmt_mp->height, 4, 1080, 1, 0); + if (IS_MFCV12(dev)) + v4l_bound_align_image(&pix_fmt_mp->width, 8, 3840, 1, + &pix_fmt_mp->height, 4, 2160, 1, 0); + else + v4l_bound_align_image(&pix_fmt_mp->width, 8, 1920, 1, + &pix_fmt_mp->height, 4, 1080, 1, 0); } else { mfc_err("invalid buf type\n"); return -EINVAL; diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c index 2194df7b6fbf..c4953419be0e 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c @@ -1116,6 +1116,18 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) reg |= ((p->num_b_frame & 0x3) << 16); writel(reg, mfc_regs->e_gop_config); + /* UHD encoding case */ + if ((ctx->img_width == 3840) && ctx->img_height == 2160) { + if (p_h264->level < 51) { + mfc_debug(2, "Set Level 5.1 for UHD\n"); + p_h264->level = 51; + } + if (p_h264->profile != 0x2) { + mfc_debug(2, "Set High profile for UHD\n"); + p_h264->profile = 0x2; + } + } + /* profile & level */ reg = 0; /** level */ From patchwork Tue Oct 11 12:25:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125212epsmtip10ce56d162cae548afeecd030a875f51d~dBNDrDPlt2145321453epsmtip1M; Tue, 11 Oct 2022 12:52:12 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 11/15] media: s5p-mfc: Add support for DMABUF for encoder Date: Tue, 11 Oct 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REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125215epcas5p1021a37aff1bc8956191ff435474e1503 References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy Add dmabuf support for mfc encoder Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- .../media/platform/samsung/s5p-mfc/s5p_mfc.c | 4 ++-- .../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 21 +++++++++++-------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c index fe07112f013f..ad04ec68921b 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c @@ -850,7 +850,7 @@ static int s5p_mfc_open(struct file *file) q->io_modes = VB2_MMAP; q->ops = get_dec_queue_ops(); } else if (vdev == dev->vfd_enc) { - q->io_modes = VB2_MMAP | VB2_USERPTR; + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; q->ops = get_enc_queue_ops(); } else { ret = -ENOENT; @@ -877,7 +877,7 @@ static int s5p_mfc_open(struct file *file) q->io_modes = VB2_MMAP; q->ops = get_dec_queue_ops(); } else if (vdev == dev->vfd_enc) { - q->io_modes = VB2_MMAP | VB2_USERPTR; + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; q->ops = get_enc_queue_ops(); } else { ret = -ENOENT; diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c index f953a3ed7f20..22f6ebc28e40 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c @@ -1705,9 +1705,10 @@ static int vidioc_reqbufs(struct file *file, void *priv, struct s5p_mfc_ctx *ctx = fh_to_ctx(priv); int ret = 0; - /* if memory is not mmp or userptr return error */ + /* if memory is not mmp or userptr or dmabuf return error */ if ((reqbufs->memory != V4L2_MEMORY_MMAP) && - (reqbufs->memory != V4L2_MEMORY_USERPTR)) + (reqbufs->memory != V4L2_MEMORY_USERPTR) && + (reqbufs->memory != V4L2_MEMORY_DMABUF)) return -EINVAL; if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { if (reqbufs->count == 0) { @@ -1784,9 +1785,10 @@ static int vidioc_querybuf(struct file *file, void *priv, struct s5p_mfc_ctx *ctx = fh_to_ctx(priv); int ret = 0; - /* if memory is not mmp or userptr return error */ + /* if memory is not mmp or userptr or dmabuf return error */ if ((buf->memory != V4L2_MEMORY_MMAP) && - (buf->memory != V4L2_MEMORY_USERPTR)) + (buf->memory != V4L2_MEMORY_USERPTR) && + (buf->memory != V4L2_MEMORY_DMABUF)) return -EINVAL; if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { if (ctx->state != MFCINST_GOT_INST) { @@ -2842,11 +2844,12 @@ static int s5p_mfc_start_streaming(struct vb2_queue *q, unsigned int count) S5P_MFC_R2H_CMD_SEQ_DONE_RET, 0); } - - if (ctx->src_bufs_cnt < ctx->pb_count) { - mfc_err("Need minimum %d OUTPUT buffers\n", - ctx->pb_count); - return -ENOBUFS; + if (q->memory != V4L2_MEMORY_DMABUF) { + if (ctx->src_bufs_cnt < ctx->pb_count) { + mfc_err("Need minimum %d OUTPUT buffers\n", + ctx->pb_count); + return -ENOBUFS; + } } } From patchwork Tue Oct 11 12:25:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aakarsh Jain X-Patchwork-Id: 13004621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01854C433FE for ; Wed, 12 Oct 2022 03:50:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229818AbiJLDup (ORCPT ); Tue, 11 Oct 2022 23:50:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with 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20221011125219epsmtrp20c14976087be1872d76070ecea0558fa~dBNJ3uBTZ1820318203epsmtrp2H; Tue, 11 Oct 2022 12:52:19 +0000 (GMT) X-AuditID: b6c32a4a-007ff70000019a35-c8-634638fc3251 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 09.94.18644.30765436; Tue, 11 Oct 2022 21:52:19 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125215epsmtip1500fb54b3a3c857d9d68ed8a049b593b~dBNGz2ZbB2675826758epsmtip1J; Tue, 11 Oct 2022 12:52:15 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 12/15] media: s5p-mfc: Set context for valid case before calling try_run Date: Tue, 11 Oct 2022 17:55:13 +0530 Message-Id: <20221011122516.32135-13-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTf0xTVxTHc/va15YM81JZdmmQsadzAlKpa7uLAUYE3WOIkhF1bhmsK48f 0l/2h7KZOCaCYnSMBQQ6BAYUJ6Bg+WEtGArU4cziRiVgkDoYIiCLGxQdCixrKWz/fc4533O/ J+fey8F4Yzifk6HU0RqlVE7iXsz23sAtIUtotyx0aiIQTZjLWGi0oh1HNQuTDPRbjZOJelra 2Kh14DsMXeqzslCl7S4LXe/+nYmuTbmq/WUOJpqsvArQtOEhjkzjgyw09uQgumcpx9G55jYW umJzsJFxqJ+B6kxLDFTdNs9GuTdtbOTobAfoVJ6NEQWpxopGQJkdtYAaqp3DqBsGB5uq6Zxm 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Now there will be a new context created and hardware will be invoked for the buffer queued instead of waiting for another buffer to be queued from userspace to set this context bit for hw execution. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c index ad04ec68921b..7e6fd130f7d4 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c @@ -589,6 +589,8 @@ static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, s5p_mfc_clock_off(); wake_up(&ctx->queue); + if (ctx->src_queue_cnt >= 1 && ctx->dst_queue_cnt >= 1) + set_work_bit_irqsave(ctx); s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); } else { WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); From patchwork Tue Oct 11 12:25:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aakarsh Jain X-Patchwork-Id: 13004620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 277D1C433FE for ; Wed, 12 Oct 2022 03:50:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229711AbiJLDun (ORCPT ); Tue, 11 Oct 2022 23:50:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229717AbiJLDta (ORCPT ); Tue, 11 Oct 2022 23:49:30 -0400 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C845ABD55 for ; Tue, 11 Oct 2022 20:48:23 -0700 (PDT) Received: from epcas5p2.samsung.com (unknown [182.195.41.40]) by mailout1.samsung.com (KnoxPortal) with ESMTP id 20221012034821epoutp016b96dde55f075f01bca593eda454f2d1~dNbfoAYEi2322523225epoutp01l for ; Wed, 12 Oct 2022 03:48:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout1.samsung.com 20221012034821epoutp016b96dde55f075f01bca593eda454f2d1~dNbfoAYEi2322523225epoutp01l DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1665546501; bh=VU96B+4AmTLSo76S7TlPprnB1dXScdmwt5AHyPX25pM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lgDVCQcrhCqYV8q9zVhEGSRDdtaD0emcNODozZ2TyzCGOURDy9YQgvRGl3tjf09g/ EG63YaVp6MwiOX50m9+FQStG7cddnDuIY7Q3lye3FlTgw5GkaCM4TdjviKUgIb91Xk UnynSfnENITcmHRDe/odpTpknF9buoblia4MjKu4= Received: from epsnrtp3.localdomain (unknown [182.195.42.164]) by epcas5p4.samsung.com (KnoxPortal) with ESMTP id 20221012034820epcas5p4ea59d009f3ff9cd18237e0aa9c54ba01~dNbe04Dug0309103091epcas5p47; Wed, 12 Oct 2022 03:48:20 +0000 (GMT) Received: from epsmges5p2new.samsung.com (unknown [182.195.38.175]) by epsnrtp3.localdomain (Postfix) with ESMTP id 4MnJXK6443z4x9Pt; Wed, 12 Oct 2022 03:48:17 +0000 (GMT) Received: from epcas5p2.samsung.com ( [182.195.41.40]) by epsmges5p2new.samsung.com (Symantec Messaging Gateway) with SMTP id F6.1C.39477.10936436; Wed, 12 Oct 2022 12:48:17 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20221011125222epcas5p1599424c2b8fe888dd9f9d04c76909c07~dBNNAVtNn1056110561epcas5p1F; Tue, 11 Oct 2022 12:52:22 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20221011125222epsmtrp165015956329610abae2d84a3f82bde22~dBNM-AA5-2654526545epsmtrp1O; Tue, 11 Oct 2022 12:52:22 +0000 (GMT) X-AuditID: b6c32a4a-259fb70000019a35-dd-63463901eba4 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id E4.1D.14392.60765436; Tue, 11 Oct 2022 21:52:22 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125219epsmtip1fd42a1817ee88692a7c8dc315b836089~dBNJ8oHtt2178621786epsmtip1u; Tue, 11 Oct 2022 12:52:19 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 13/15] media: s5p-mfc: Load firmware for each run in MFCv12. Date: Tue, 11 Oct 2022 17:55:14 +0530 Message-Id: <20221011122516.32135-14-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTe0xTVxzHc+5tbwuu5FrRHYgiKxsqGdhiCwcGuqDWOyUTYpzRbcGmvQFC X+ktzPkH62AwxkRkuImMAaEUE95vkEfAijMD58QRSJwtApO3TnkNwcFKW7b/Pr/v7/c7v8c5 h4vzRwhPbrxaT+vUMqWAcGU139631x+ESOXC4ZZd6GnrdTZ6UthMIOPyBIaGjfMsZG5o4qDG gR9xdONuNxsV9dxno5ZboyxUN2nz9l+3sNBEUTVAU/lWAtWPDbLRyPQZ9HtbAYEu1TaxUVWP hYNMQ/0YKqt/jaGSpgUOSuvs4SBLRzNAX6X3YO9DqrKwElCtllJADZXO4dTNfAuHMnZMYVR9 +TcE9Xiwg6AaSr+g0u6ssKjLjeWAWkv5iUNl9gwR1Hy9F9W7OM+JcjuXEBZHyxS0zptWyzWK eHVsuODEqZjDMZIgochfFIKCBd5qmYoOFxyJjPKXxittaxB4J8mUiTYpSsYwgv0Hw3SaRD3t Hadh9OECWqtQasXaAEamYhLVsQFqWh8qEgoDJbbA8wlx6/+YMK2Re8FUl80xAAMnE7hwISmG ZaODxAbzyXYAp6uwTOBq4zkA2/N/JRzGEoDp833EZkZvUS7b4egEsOXyJdxhpGGw6o8UsBFF kP6wy9Rtz3AnvwRwLEO/EYSTqSxoubdqL76NjIYTD4vxDWaR78BfCsvtOo88CGcfvcAd5XbD itpuO7vY9Jemn+09QXKdC4cNr509HYFXclOdvA1O3210TucJp7LTnSyHYyVTzkOVsKbjKsvB h2D3QIGNubbu9sGatv0OeRf8vrca22CcdINZq39iDp0HWws32RcWPF5mO3gnvF1hAg6m4LWi dueKcgCsMDwDV4BX/v8ligEoBx60llHF0oxEG6imP/vv2uQaVT2wv3W/461g5MmLADPAuMAM IBcXuPNAUYScz1PIPr9I6zQxukQlzZiBxLbAHNxzu1xj+yxqfYxIHCIUBwUFiUMOBIkEb/KM eX5yPhkr09MJNK2ldZt5GNfF04BV56vdqlaPnbk2WTG+Mh9p8HZ/IB2qnD2W538vwycV40iv Ng3tGW+OhaI3VnzWQ59aPti9g/H9zSM0KbsvInnmw94dyWXJeS9PWueWR63o5iuwZWtJTtLb r9JOqwYUC5/OZEqSO6MXUnjo1lFV7pY7WIbrzprlb0f2jvv9db7voY7hpXYZjj6P0GofnDw3 uS49cPa0aWC2jlhL128nrXuKT7jrrYuqHy4cEvDOcqvy7i+ZUe1x6NHCD37P593vrJK15qyt 4oHDtV5/G5eynp/y9fhI6ccPC//kRobi2dfYojovcFw6EdxQp+oKjXxrZfiR+WKlsKMfZ2G+ M6q26I+VlIDFxMlEfriOkf0La9gOzHQEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAAzWRa0hTYRjHe8/OzcXsOBedNCxOmKQ4szTfbpJCcQi6EJhUlC47WLnNsZOV QaSZoSa1TKOpbeI2ZetCzry2aNnR0A9iF1wX10UxL7kytZJYWrP69nue35/n/+EhRVI9GkQe VR/ntGqFksHFaONjJiQST9+StsrwNhgONusx+N7QiEPT9BAC35kmUdhW30DAey8qRLD2iROD RqEbg02P+lFYN/zHPtW7UThkvAPgSPlbHNoHejH4YTQZPm+txGHx3QYM3hbcBLS4niKwxu5F YHXDFAHzHwgEdDsaATx/QUA20+wtwy3ANrvNgHWZJ0RsS7mbYE2OEYS12wpxtq/XgbP15rNs fvtPlL10zwbYmXM3CLZIcOHspD2E7fo2Sezy3yfeeJhTHj3BaaPiU8VHZn9ZEI2JPGWpu0zk gByiCPiRNBVDdxmvYkVATEqp+4D+8Wnqn1hCz17o+MeBtHVmiPgbykPoqsFruE/gVCT90OLE fUJG5QPaZS1EfIOIqkDp6RIn5ksFUjvp0pka1McoFUp3GmxzZyVUPD32elz0t2IpffOuc479 /uy/WjrmGqTUJjr3SxmiA/5VYJ4NLOY0vCpdxUdrotXcSTmvUPFZ6nR5WqbKDua+F76yGTTZ xuVtACFBG6BJESOTAGNimlRyWJF9mtNmpmizlBzfBoJJlFkk6SnqTJFS6YrjXAbHaTjtf4uQ fkE5SHdxZ31i6XSL9X7ABpI5s9cSp+/rOVewq8xtsm8M027XrR2OiHtvrtpRMFRZXrYvKubK mEfaHyANYGK3t7Zcq1UTy56t0QU6heev9qLrNgRQ75Tfl2Cr5d5VGvPBvoGMCe1yV09W/8tE dWqe91m1Gg1LVS74ltx5CcvNXG5kk3TJDO+sGIgdr7k+O1Ls9QQdijxQ4LB+lvu9Mcewo1b9 Zc/CPevrVCtLyhNCqiuro+IF2eaL28QGIZuJnTKLmrszPRFds/tLxZLS3fEa7FdoD+NKeKG7 mm2d/7HJJswcq+h26Be0wwc6WWN2YbuXb09wbl2R1DHoscp0OxkG5Y8oosNFWl7xG1d+CPws AwAA X-CMS-MailID: 20221011125222epcas5p1599424c2b8fe888dd9f9d04c76909c07 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125222epcas5p1599424c2b8fe888dd9f9d04c76909c07 References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy In MFCv12, some section of firmware gets updated at each MFC run. Hence we need to reload original firmware for each run at the start. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c index 877e5bceb75b..a70283d4c519 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c @@ -51,8 +51,9 @@ int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev) * into kernel. */ mfc_debug_enter(); - if (dev->fw_get_done) - return 0; + if (!IS_MFCV12(dev)) + if (dev->fw_get_done) + return 0; for (i = MFC_FW_MAX_VERSIONS - 1; i >= 0; i--) { if (!dev->variant->fw_name[i]) From patchwork Tue Oct 11 12:25:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aakarsh Jain X-Patchwork-Id: 13004623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3392BC43217 for ; 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Tue, 11 Oct 2022 12:52:25 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20221011125225epsmtrp124d33f618f76af0101417aa27f082076~dBNQL8jdM2656926569epsmtrp1G; Tue, 11 Oct 2022 12:52:25 +0000 (GMT) X-AuditID: b6c32a4a-259fb70000019a35-34-63463920aa7d Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id F6.1D.14392.90765436; Tue, 11 Oct 2022 21:52:25 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125222epsmtip13cf750c0ca431f1594dffaf426c9d395~dBNNFkVMh2344423444epsmtip1Y; Tue, 11 Oct 2022 12:52:22 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 14/15] media: s5p-mfc: DPB Count Independent of VIDIOC_REQBUF Date: Tue, 11 Oct 2022 17:55:15 +0530 Message-Id: <20221011122516.32135-15-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VTfUxTVxzNfX3tKybgC/hxYQ6wywCJYNuV8kCoTj58mSwjcwa3RVhXnoVQ 2q4tMoyJCJYp20RgM8IQECgMUMHyVaEolBYcoMyMgDqKFLawKhuDOmeA4VoK23/nd37n3HPv 797LpLlbGF7MVKmKUkiFEhZjE9ret8s/yDcsVsQ2rULiV10JnZgqb2cQ1S9nEeJJtQ0lDC1t GNE6+h2NqBvooRMVxvt0oqN3GiVu/mbvPigxo8RsxQ1AWEsnGYR2ZoxOWJ4mED91ljGIr5rb 6MR1oxkjNOMPEKJWu4IQVW3PMULdbcQIs74dEGfzjMh+SF4rvwZInbkGkOM1izTyVqkZI6v1 VoTUNpxnkBNjegbZUnOaVJuWUPJCawMgV3OuYGS+cZxB2rTe5OBfNize7aO0iBRKmEwpfCmp SJacKhVHsg4dTopKCuGzOUGcMCKU5SsVplORrOi4+KDYVIl9DCzfE0JJhp2KFyqVrD2CCIUs Q0X5psiUqkgWJU+WyHnyYKUwXZkhFQdLKVU4h83mhtiFn6SllLf20eW53p8PPdOg2WAR5gMX JsR5sOIHG5oPNjHd8S4A5+u6EGexCOC0pYfmLF4AaHlYz9iwvFDfwZyNbrtlsWXdokagZrYe cagYeBC8o+lZc2zBzwA4c07lENHwXBSah5cxR8MDfx9mj39vz2AyUfxNaMoLcNCuuADmzjui HWk+sLHZiV3s/IKmn+FYB+K5LnDVtIw6RdGwVH95HXvApwOtmBN7QWtB3joWwZkq6/qiEtik /2Zdvw/2jJahjj3Q8F2wqXOPk34dfjt4Y+0sNNwNfr38C+LkXaGufAP7wbKJl3Qn3gH7GjXA iUk49kUR3TmUQgCL7uZiF4F36f8RlQA0AE9KrkwXU8oQOVdKZf53bSJZuhasvfXAd3TAMvVn sAEgTGAAkEljbXEFFQdE7q7JwqyTlEKWpMiQUEoDCLHPr5DmtVUks38WqSqJwwtj8/h8Pi/s LT6Htd21+nKgyB0XC1VUGkXJKcWGD2G6eGUjfqyDscUjR2pOmazv3bziVtvfz/UOX7g3dKr4 fnfmkbgdV1/zWNKLTuwXPDoUN5zQFfpsjsefY0YExxjEQ36dtuM2/1e399VLzhW9+ngv9mVf L+J3ceRxb8KBY8sxuw+rK984ujC1FO2Z6W7YHJu+2PT7XR/BY61g+uj13cb+S1FnZ1wSz4SH NSe+jevnVtpbj8/8EXCsY+7dpaqroQHRO7dZPT9NHH649Lf85ObaUUFB1untPiCrr6iMbWHr SsSdBq4h53mj6VZd6Mr8ZMvWyn8GDvqvPNnZMX/JXMAt9FFzb3+4jbNXNhHlnpzRW3y+KecD g6zu56CewZqRxHuPYrDPftRNslBlipATSFMohf8CYe9fwHQEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprOIsWRmVeSWpSXmKPExsWy7bCSnC5numuywbsXRhZPd8xktXgwbxub xeIfz5ks7i/+zGJxaPNWdostV2YzWyw/foDVYv6Rc6wW2w8+YrHY+AIoe3HmXRaL5/PXMVq8 nHWPzWLT42usFg9fhVtc3jWHzaJnw1ZWi7VH7rJbLL1+kcli2aY/TBaLtn5ht2jde4Td4u6e bYwWLW1HmBwkPNbMW8PosePuEkaP60s+MXvsnHWX3WPxnpdMHptWdbJ53Lm2h81j85J6j9aj v1g8+rasYvT41zSX3aPryHU2j8+b5DxOff3MHsAXxWWTkpqTWZZapG+XwJUxb8th1oJmuYrT r5eyNDB+kuhi5OSQEDCR+Na6n72LkYtDSGA3o8ShmQ2sEAkZif9tx9ghbGGJlf+eg9lCAs1M Ei+3WoLYbAK6EvuXHmADaRYRaGWUuL6ykwnEYRaYzSLxY9IBsEnCAgESKyc+BOrm4GARUJU4 2qYBEuYVsJNofn+AGWKBvMTqDRA2J1D849JjbBDLbCUa309lmsDIt4CRYRWjZGpBcW56brFh gWFearlecWJucWleul5yfu4mRnDcaWnuYNy+6oPeIUYmDsZDjBIczEoivIzznZKFeFMSK6tS i/Lji0pzUosPMUpzsCiJ817oOhkvJJCeWJKanZpakFoEk2Xi4JRqYOqaNJVJ6+OR+bpnb4l3 tvn7tSRYOJvEbe7MVpUr+84pK3+4r3Lnwycq3Bteb+hqt3ab684aGnq7LuTwgq28jeu3t22d osJlWJk9vXGxebBgnpXjG3GtJZ6CByxdlHuzZx2S+6fzWCRXv0Sm4e+sRRUpXK7GP93YTLdZ qYso7+15kJ6gNF32F2MQ52vNvX9azyUvu7CDyXTLN4HeQ9rq3684bXyeevaTyjXT7TefW89L dPhy9nDJtLdzT52uuSncv/UT26YirlLL7HaJCpn6S+fvXdNQ1pRZapa16N4uDy6Zle+fZDHs zzg3h9dgghznkx1h6ft2iZ9c5bLjAK9R1LvpJ8MrNR4tE1kqd0DWSomlOCPRUIu5qDgRAAxo 3yEqAwAA X-CMS-MailID: 20221011125225epcas5p1b3504009ef4519a24dd44ba205606fe4 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125225epcas5p1b3504009ef4519a24dd44ba205606fe4 References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy This patch allows allocation of DPB buffers based on MFC requirement so codec buffers allocations has been moved after state MFCINST_HEAD_PRODUCED. It is taken care that codec buffer allocation is performed in process context from userspace IOCTL call. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- .../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 17 ++--------------- .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 9 ++++++++- 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c index 22f6ebc28e40..425dcab0cd1c 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c @@ -1340,7 +1340,6 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx) struct s5p_mfc_dev *dev = ctx->dev; struct s5p_mfc_enc_params *p = &ctx->enc_params; struct s5p_mfc_buf *dst_mb; - unsigned int enc_pb_count; if (p->seq_hdr_mode == V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) { if (!list_empty(&ctx->dst_queue)) { @@ -1362,10 +1361,8 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx) set_work_bit_irqsave(ctx); s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); } else { - enc_pb_count = s5p_mfc_hw_call(dev->mfc_ops, + ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_enc_dpb_count, dev); - if (ctx->pb_count < enc_pb_count) - ctx->pb_count = enc_pb_count; if (FW_HAS_E_MIN_SCRATCH_BUF(dev)) { ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops, get_e_min_scratch_buf_size, dev); @@ -1731,14 +1728,6 @@ static int vidioc_reqbufs(struct file *file, void *priv, } ctx->capture_state = QUEUE_BUFS_REQUESTED; - ret = s5p_mfc_hw_call(ctx->dev->mfc_ops, - alloc_codec_buffers, ctx); - if (ret) { - mfc_err("Failed to allocate encoding buffers\n"); - reqbufs->count = 0; - ret = vb2_reqbufs(&ctx->vq_dst, reqbufs); - return -ENOMEM; - } } else if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { if (reqbufs->count == 0) { mfc_debug(2, "Freeing buffers\n"); @@ -1754,15 +1743,13 @@ static int vidioc_reqbufs(struct file *file, void *priv, return -EINVAL; } - if (IS_MFCV6_PLUS(dev)) { + if (IS_MFCV6_PLUS(dev) && (!IS_MFCV12(dev))) { /* Check for min encoder buffers */ if (ctx->pb_count && (reqbufs->count < ctx->pb_count)) { reqbufs->count = ctx->pb_count; mfc_debug(2, "Minimum %d output buffers needed\n", ctx->pb_count); - } else { - ctx->pb_count = reqbufs->count; } } diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c index c4953419be0e..c00debe5db76 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c @@ -377,7 +377,6 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) default: break; } - /* Allocate only if memory from bank 1 is necessary */ if (ctx->bank1.size > 0) { ret = s5p_mfc_alloc_generic_buf(dev, BANK_L_CTX, &ctx->bank1); @@ -2255,6 +2254,14 @@ static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx) struct s5p_mfc_dev *dev = ctx->dev; int ret; + ret = s5p_mfc_hw_call(ctx->dev->mfc_ops, + alloc_codec_buffers, ctx); + if (ret) { + mfc_err("Failed to allocate encoding buffers\n"); + return -ENOMEM; + } + mfc_debug(2, "Allocated Internal Encoding Buffers\n"); + dev->curr_ctx = ctx->num; ret = s5p_mfc_set_enc_ref_buffer_v6(ctx); if (ret) { From patchwork Tue Oct 11 12:25:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aakarsh Jain X-Patchwork-Id: 13004622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC94AC43217 for ; Wed, 12 Oct 2022 03:51:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229831AbiJLDv2 (ORCPT ); Tue, 11 Oct 2022 23:51:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229650AbiJLDur (ORCPT ); Tue, 11 Oct 2022 23:50:47 -0400 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7158CABF24 for ; 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Tue, 11 Oct 2022 21:52:29 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20221011125226epsmtip11bf61fb7e73799627eae74100ac2bdba~dBNQO9w_Y2675826758epsmtip1K; Tue, 11 Oct 2022 12:52:25 +0000 (GMT) From: aakarsh jain To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v3 15/15] arm64: dts: fsd: Add MFC related DT enteries Date: Tue, 11 Oct 2022 17:55:16 +0530 Message-Id: <20221011122516.32135-16-aakarsh.jain@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011122516.32135-1-aakarsh.jain@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTe0xTdxTH87u37W0JZXeI8ScBZI26iQLtLN0PI8whY9eJhumMhmzD2t4A Utra2w4H2YDxyGRixM0HCNQIDMfbAh1jMLtSZGPI0oxJIBYr+IJ1DikyxI2sD9z++5xzvueR c34/Lu5v5wRy05VaWqOUKgQcH5axb9PL4eujE2TCxtnN6F5XORvZq40cVLP4AEO3a5wsZG7v JFDHyEUc1Q+Y2EhvGWajb36YZKGrD11Ra7mNhR7oWwCarpjgIMPUTTa6M3MQ/dpdyUEn2zrZ qNliI1DdqBVDXxn+xtDlznkCFfVaCGTrMQJUWGzBdkCqqboJUF22WkCN1s7h1LcVNoKq6ZnG KEPDCQ5162YPh2qvzaWK+pdY1KmOBkAtf1pFUCWWUQ7lNIRQg0+cRJJfcsb2NFoqpzWhtFKm kqcrU2MEu/en7EyJkghF4aJo9JogVCnNpGME8YlJ4QnpCtcaBKEfShU6lytJyjCCyNjtGpVO S4emqRhtjIBWyxVqsTqCkWYyOmVqhJLWbhMJha9GuYSHM9LMPzWz1Q6f44v5y0QeuMEtAVwu JMXQ+ufhEuDD9Se/A7B16RfgNeYAzLf2YV5jAcCZaxOcEsDzZBj/cawEegE8Oz9FeI0iDF4f +sOj4pDh8FqdycMBZD6AU59p3SKcLGBB29Azwh1YRSbAovEhtptZ5AZYP3zGk8AnY+HE8CLm bbcONraZcDfzXP7Hddc57kKQLODBgrlmwiuKh0uFP6/wKjgz0LHCgdD5qHdlbhmcujyNe1kB W3u+ZHn5dWgaqWS5t4GTm2Brd6TXHQzPDrZ4ZsBJP1j67O7KPHzYVf2cN8LKW4tsLwfBvsY6 4GUKmhzdnvL+ZBmAg/o9p0FIxf8dLgHQANbSaiYzlWai1CIlnfXf1WSqTAPwPPWwXV3AZp+N MAOMC8wAcnFBAB/o42T+fLn0o2xao0rR6BQ0YwZRrv2V4YGrZSrXX1FqU0TiaKFYIpGIo7dK RII1/JoLYTJ/MlWqpTNoWk1rnudhXF5gHtYyvnXL/Q+M5fmnX7FrdtVeOtCf57hRejt4X35S 5VW/vUfwY8fi5zdP1sUeMQVI9xIPtXmfBBteuDiWc/5t3+LSUsJvT+v6A/0NtnfurT4TuS7h /RjhE+5Czu+tPn9Fdk5INlq2XDgPftwXsuHzF7+vhecetWsLHMd5I7p4YwayW3u+NmV1+0ri jlLFL3083par/E2//JZ5hD+9cJRrW6ST03hZE7sdawfEY8ybp+6cY/S2bsWhWXtQ0BpQltg0 95RqaZ6sOpiTfGUEe2+H7u7s/ceUX5VvjHM26oTIp1Av18j7Gt8odpZnxSVmZ5Ud0g4/fXem pH5nrq7ddyy78so2xf4vBCwmTSoKwzWM9F+rL0NMcwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAAzWRa0hTYRiA/c7OzcXkNIW+LroYXSjLNAs+rSyj4lQWUXSTbic9TGubc5ut AsnlpVq3OSjyNiunlWnqzGVlZGu1rJTEaJDNS6NMk25qmdQqJ/17eJ+H9/3x0gJxHj6JTlZq ebWSk0tJIW57KA2ZK5KtTAgf/D0OvavPI1CX2UaikuEeDHWWDODIXltHoZsvCwToirORQMWO FgLdevAWRzUf/tnWPDeOeopvANSb30Eiq+cVgbr7tqK2O4UkOlVdR6BKh5tCpa5WDJVZf2Ho ct0ghbLvOSjkbrABlJXjwJZBtsJcAdh6twWwLss3AXs7302xJQ29GGstP0Gyb141kGyt5Qib /WgEZ8/cLAes92gRxRocLpIdsIawT4cGqA0B8cLFibw8+QCvnhezR5hkb6okVP3Cg8N6L5UB mmkD8KchswDafvdjBiCkxcxdAFvdz/AxMQX+yXlMjXEgvObtocaiTAx67t4hRgXJzIX3SxvJ URHEZAPounbCt0rAFOBw2NToqwKZVTD79XMf48x0eKXFRI6yiImBHS3D2NgJCbxe3SgYZf9/ 86+lj32NmFkC9Z/PYUYQcBH4lYOJvEqjkCk0EaoIJa8L03AKTZpSFpaQorAC3/dmz6oHt8q/ hNkBRgM7gLRAGiQCxcsTxKJE7tBhXp2yW50m5zV2MJnGpRNELwxNu8WMjNPy+3lexav/W4z2 n5SBPasuUhxJ3CsxpYdPy1y/Iy0J7Y+c0IXNbOnq6zNTOTLzSOcuVPlk573VvQuzMr5e0ktM zsH0zbrm0FRF9M9QSunXRHwZ5BhnkyuLu7rFPl50SLd98+I0Y6ynrRLWLjrldx6vnyG2nNTa CkYkp4mapcZpxqfSmJCjO1IlG7+ZL0/dZNoXfz1dZ3shOWM0CPu4Y/rlZ9dVRJUpt2Z5Olas lfBBtvhg2cA8vT3Kq4tSOKIXOU+H0V3RNbkfStZ4l2YmtFeF9EemztkYF/snXOsJdBbLtUFV Qx9zY398/zQ/19Iul5TFBWM6bV6y8XhboVOzK/bCnoCzqm0N3YXvjVJck8RFzBaoNdxf4MS1 ViwDAAA= X-CMS-MailID: 20221011125229epcas5p434cecc44beb02450c876de71c0f06011 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221011125229epcas5p434cecc44beb02450c876de71c0f06011 References: <20221011122516.32135-1-aakarsh.jain@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Smitha T Murthy Add MFC DT node and reserve memory node for MFC usage. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy Signed-off-by: Aakarsh Jain --- arch/arm64/boot/dts/tesla/fsd.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index f35bc5a288c2..b2f7345d2cba 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -340,6 +340,18 @@ #clock-cells = <0>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mfc_left: region@84000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x84000000 0 0x8000000>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <2>; @@ -832,6 +844,15 @@ clock-names = "fin_pll", "mct"; }; + mfc: mfc@12880000 { + compatible = "tesla,fsd-mfc"; + reg = <0x0 0x12880000 0x0 0x10000>; + interrupts = ; + clock-names = "mfc"; + clocks = <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>; + memory-region = <&mfc_left>; + }; + ufs: ufs@15120000 { compatible = "tesla,fsd-ufs"; reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */