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Thu, 13 Oct 2022 11:39:10 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:39:10 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:39:06 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 01/21] PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select" Date: Fri, 14 Oct 2022 00:08:34 +0530 Message-ID: <20221013183854.21087-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT010:EE_|SA1PR12MB7320:EE_ X-MS-Office365-Filtering-Correlation-Id: 5caef5e4-3b86-4085-f550-08daad4a3ded X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:20.2974 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5caef5e4-3b86-4085-f550-08daad4a3ded X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT010.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7320 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The GPIO DT property "nvidia,refclk-select" to select the PCIe reference clock is optional. Use devm_gpiod_get_optional() to get it. Signed-off-by: Vidya Sagar --- V3: * None V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 9e64b948f999..d7ab33931de4 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1233,9 +1233,9 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) return err; } - pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, - "nvidia,refclk-select", - GPIOD_OUT_HIGH); + pcie->pex_refclk_sel_gpiod = devm_gpiod_get_optional(pcie->dev, + "nvidia,refclk-select", + GPIOD_OUT_HIGH); if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); const char *level = KERN_ERR; From patchwork Thu Oct 13 18:38:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006313 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0122EC4321E for ; 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Thu, 13 Oct 2022 11:39:12 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 02/21] PCI: tegra194: Drive CLKREQ signal low explicitly Date: Fri, 14 Oct 2022 00:08:35 +0530 Message-ID: <20221013183854.21087-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT050:EE_|SN7PR12MB7021:EE_ X-MS-Office365-Filtering-Correlation-Id: 0beea1e1-012d-4ef4-7da8-08daad4a42c8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bYnTU4AOp5SjlRpP4zGKYR5K/3yvhAmHL3BC6v07IOWzQYXoehKWPvz1+SHe/3KoUTZcD0QwA8XzuT7KqT5dK2JIm31QG7lvUrJFvio4Jb11FMtiIUgzPRhJDHMehXw2QBfcx7c2lViNJPr5GkNnjPmlHdCXnsZWyPvHkQnfccpcIe36zbWAuE8Netnie9heznEyQ7p53lbH/I4rRwbByHgbJXHNvKg6166H5emy45zHUDxruXdpCPkAWumDFCpvhSMLLoojaR+AOeSEOnp0sITJ4rA8l+IPT3C1T1C5nsGLpwKOa7WXunldwFJ8RgpAqmcLtFCh9VzgI6tFoZcq6t8rUvahw2xUtp0iVxIbpbWqirqMwlox5+sq33fd9KTDHPjgp+o46TSnjw8a5ap+JmkBw+xbgZ8tAVxPcF9VR5cE0uVgv6gxtVpkpiTG5M08F/GfN8Zcbh6FtUT+XKBtSY/7HrPTEseNaOpMLQS/g8iTZ6QOQaRZtAUOT5VGC6BSdSh7SCgn9xghiB4cGTO9ZxZpSfz0nQBEy05k5Zkk5DZPkqqHo5NvI9SedFGrlntq9F+qv1lYsLJmcO+bTr+QxMTDp7V8sb5TgstjVHy8W+gqbaWpEx//zBtUHC30NeUEQnKYgQF+DvYVOmNvSKKT7kRLD8YnUh5nrRDZdS87QFe0mALm+7yZeKyrIOFS7UtokTqoUDCj22SFmAjgK+ZQQbDB4oiAKqrzPa41S+fR5pfQm4t5NpAvjDVgYybBVYNL7yrKMklgAR47KzsKDSQOcZf+sLkRKYQDShRDTL2Tdp0= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(346002)(396003)(376002)(451199015)(46966006)(40470700004)(36840700001)(316002)(110136005)(82740400003)(40480700001)(426003)(921005)(36860700001)(54906003)(47076005)(8936002)(1076003)(7416002)(7636003)(26005)(186003)(5660300002)(6666004)(2616005)(2906002)(8676002)(4326008)(70206006)(70586007)(82310400005)(7696005)(336012)(36756003)(356005)(41300700001)(40460700003)(83380400001)(86362001)(478600001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:28.3936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0beea1e1-012d-4ef4-7da8-08daad4a42c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7021 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Currently, the default setting is that CLKREQ signal of a Root Port is internally overridden to '0' to enable REFCLK to flow out to the slot. It is observed that one of the PCIe switches (case in point Broadcom PCIe Gen4 switch) is propagating the CLKREQ signal of the root port to the downstream side of the switch and expecting the endpoints to pull it low so that it (PCIe switch) can give out the REFCLK although the Switch as such doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this patch drives the CLKREQ of the Root Port itself low to avoid link up issues between PCIe switch downstream port and endpoints. This is not a wrong thing to do after all the CLKREQ is anyway being overridden to '0' internally and now it is just that the same is being propagated outside also. Signed-off-by: Vidya Sagar --- V3: * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index d7ab33931de4..a33c86e3de9d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -47,6 +47,7 @@ #define APPL_PINMUX_CLKREQ_OVERRIDE BIT(3) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) +#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE BIT(13) #define APPL_CTRL 0x4 #define APPL_CTRL_SYS_PRE_DET_STATE BIT(6) @@ -1510,6 +1511,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, val = appl_readl(pcie, APPL_PINMUX); val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN; val &= ~APPL_PINMUX_CLKREQ_OVERRIDE; + val &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE; appl_writel(pcie, val, APPL_PINMUX); } From patchwork Thu Oct 13 18:38:36 2022 Content-Type: text/plain; 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Thu, 13 Oct 2022 11:39:23 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:39:23 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:39:18 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 03/21] PCI: tegra194: Fix polling delay for L2 state Date: Fri, 14 Oct 2022 00:08:36 +0530 Message-ID: <20221013183854.21087-4-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT074:EE_|PH0PR12MB5605:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f8260e9-1b4f-43d6-cec7-08daad4a45a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:33.2554 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f8260e9-1b4f-43d6-cec7-08daad4a45a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT074.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5605 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org As per PCIe spec r6.0, sec 5.3.3.2.1, after sending PME_Turn_Off message, Root port should wait for 1~10 msec for PME_TO_Ack message. Currently, driver is polling for 10 msec with 1 usec delay which is aggressive. Change it to 10 msec polling with 100 usec delay. Since this function is used in non-atomic context only, use non-atomic poll function. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar --- V3: * Changed atomic call to non-atomic call * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index a33c86e3de9d..685aee378c93 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -207,7 +207,8 @@ #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8) #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8 -#define PME_ACK_TIMEOUT 10000 +#define PME_ACK_DELAY 100 /* 100 us */ +#define PME_ACK_TIMEOUT 10000 /* 10 ms */ #define LTSSM_TIMEOUT 50000 /* 50ms */ @@ -1611,9 +1612,9 @@ static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) val |= APPL_PM_XMT_TURNOFF_STATE; appl_writel(pcie, val, APPL_RADM_STATUS); - return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, - val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, - 1, PME_ACK_TIMEOUT); + return readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, + val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, + PME_ACK_DELAY, PME_ACK_TIMEOUT); } static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) From patchwork Thu Oct 13 18:38:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006319 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AFD8C43219 for ; Thu, 13 Oct 2022 18:43:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231351AbiJMSnB (ORCPT ); Thu, 13 Oct 2022 14:43:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232127AbiJMSmZ (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:39.4761 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c78b02d0-fba4-4c59-efd2-08daad4a4965 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT111.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7493 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The return value from tegra_bpmp_transfer indicates the success or failure of the IPC transaction with BPMP. If the transaction succeeded, we also need to check the actual command's result code. Add code to do this. Signed-off-by: Vidya Sagar --- V3: * None V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 685aee378c93..ae7e0d8f693b 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1260,6 +1260,7 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie, struct mrq_uphy_response resp; struct tegra_bpmp_message msg; struct mrq_uphy_request req; + int err; /* * Controller-5 doesn't need to have its state set by BPMP-FW in @@ -1282,7 +1283,13 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie, msg.rx.data = &resp; msg.rx.size = sizeof(resp); - return tegra_bpmp_transfer(pcie->bpmp, &msg); + err = tegra_bpmp_transfer(pcie->bpmp, &msg); + if (err) + return err; + if (msg.rx.ret) + return -EINVAL; + + return 0; } static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, @@ -1291,6 +1298,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, struct mrq_uphy_response resp; struct tegra_bpmp_message msg; struct mrq_uphy_request req; + int err; memset(&req, 0, sizeof(req)); memset(&resp, 0, sizeof(resp)); @@ -1310,7 +1318,13 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, msg.rx.data = &resp; msg.rx.size = sizeof(resp); - return tegra_bpmp_transfer(pcie->bpmp, &msg); + err = tegra_bpmp_transfer(pcie->bpmp, &msg); + if (err) + return err; + if (msg.rx.ret) + return -EINVAL; + + return 0; } static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) From patchwork Thu Oct 13 18:38:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006316 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EAF8C433FE for ; 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Thu, 13 Oct 2022 11:39:31 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 05/21] PCI: tegra194: Apply pinctrl settings for both PCIe RP and EP Date: Fri, 14 Oct 2022 00:08:38 +0530 Message-ID: <20221013183854.21087-6-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT072:EE_|CY5PR12MB6549:EE_ X-MS-Office365-Filtering-Correlation-Id: ccc82c90-7468-4685-9097-08daad4a4ba5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qAaIYqXgsXfnp4zge9NqFPRPIykDdXDxa+15TaY/gbqnPnH4iOH3w7IvzG5GjdWgwjeuLxQ8S+qJ5UMuwDyLLNSzqS7O4g4iLDOSatsEG+d5cndogPkjaDkxPAP7xRMddKUBchT/JG7192LfBg/Sfj7gcYf4v3eh0qPycYtiG+A2OG138SLrFBcNoqgIzygq0P73faWW65aVjWxl12gBVQcAoa8gVrBbvx6FTXkOe3G8r7vlQZHZVPJndWSfnWbJ9wv1uKycvvSC0bBZyEFkSDifsxzNrCkCUacow76feWYyw7ArOiGEbWIB4h9brhgZBBwNaHqAwJHyuYs/+bp1xMjC7z51qZCalJWAbQzAz3FVkE84MezKLQ3fIB7EKBI1D7lOAWvKdEgM/fDrOKukjOA3K8995pAOqagK0IOsFq5GB6zUKfIh8gnFp5BnWC+KoFFtXf2WkjAaPug/PfL28YdW6t0wGQDHzjympx1sFp7YTEqS3Dz7KRxxjOGBAGaIYfnBqlv6Mrsh2ZJ6Rr710ntPOkwfPQ2nrCg94FvyVCZHooSbcNxNZXNcU1kEp9pH0ATIsv5cu9u2PtXKldFbp6sgP0tsb+7x8B7EHgWUbK3MJ17WQYqlImYAzqdDKA+9d8epOueTxA8RP3LwS41gvYPv86q9a9uN3Uhdk1kuwVy8kCETq4DJoWKHYssmbd0joa4i49JJHdzd2oUtJECOjQeOgZ8EMfrchpGoiPVQ1b5dIVJCQdj7qqDCvyo68fYuaFvGtGsCSogqtqmmTC30AZXj1r0wznMPx0UJTFN2e9Q= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(376002)(39860400002)(346002)(451199015)(46966006)(40470700004)(36840700001)(7636003)(26005)(7696005)(36860700001)(110136005)(54906003)(8676002)(316002)(36756003)(356005)(82740400003)(40460700003)(40480700001)(86362001)(478600001)(2616005)(921005)(83380400001)(5660300002)(1076003)(426003)(7416002)(47076005)(336012)(70586007)(8936002)(2906002)(4326008)(70206006)(186003)(41300700001)(82310400005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:43.3267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ccc82c90-7468-4685-9097-08daad4a4ba5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT072.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6549 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org PERST# and CLKREQ# pinctrl settings should be applied for both root port and endpoint mode. Move pinctrl_pm_select_default_state() function call from root port specific configuration function to probe(). Signed-off-by: Vidya Sagar --- V3: * None V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index ae7e0d8f693b..69e11a74a0d7 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1716,12 +1716,6 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) goto fail_pm_get_sync; } - ret = pinctrl_pm_select_default_state(dev); - if (ret < 0) { - dev_err(dev, "Failed to configure sideband pins: %d\n", ret); - goto fail_pm_get_sync; - } - ret = tegra_pcie_init_controller(pcie); if (ret < 0) { dev_err(dev, "Failed to initialize controller: %d\n", ret); @@ -2191,6 +2185,19 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) pp = &pci->pp; pp->num_vectors = MAX_MSI_IRQS; + ret = pinctrl_pm_select_default_state(dev); + if (ret < 0) { + const char *level = KERN_ERR; + + if (ret == -EPROBE_DEFER) + level = KERN_DEBUG; + + dev_printk(level, dev, + "Failed to configure sideband pins: %d\n", + ret); + return ret; + } + ret = tegra_pcie_dw_parse_dt(pcie); if (ret < 0) { const char *level = KERN_ERR; From patchwork Thu Oct 13 18:38:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006315 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C43BC43217 for ; Thu, 13 Oct 2022 18:42:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232073AbiJMSmc (ORCPT ); Thu, 13 Oct 2022 14:42:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232079AbiJMSmV (ORCPT ); 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Thu, 13 Oct 2022 11:39:42 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:39:42 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:39:38 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 06/21] PCI: tegra194: Refactor LTSSM state polling on surprise down Date: Fri, 14 Oct 2022 00:08:39 +0530 Message-ID: <20221013183854.21087-7-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT040:EE_|MW4PR12MB6827:EE_ X-MS-Office365-Filtering-Correlation-Id: 0ef0a5bf-ff76-43b6-ecb9-08daad4a4ebd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:48.5195 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ef0a5bf-ff76-43b6-ecb9-08daad4a4ebd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6827 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On surprise down, LTSSM state transits from L0 -> Recovery.RcvrLock -> Recovery.RcvrSpeed -> Gen1 Recovery.RcvrLock -> Detect. Recovery.RcvrLock and Recovery.RcvrSpeed transit times are 24 msec and 48 msec respectively. So, the total time taken to transit from L0 to detect state is ~96 msec. Hence, increase the poll time to 120 msec. Disable the LTSSM state after it transits to detect to avoid LTSSM toggling between polling and detect states. tegra_pcie_dw_pme_turnoff() function is called in non-atomic context only, so use the non-atomic poll function. Signed-off-by: Vidya Sagar --- V3: * Addressed review comments from Bjorn * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 55 +++++++++++++--------- 1 file changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 69e11a74a0d7..897e2a22bcd3 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -141,7 +141,11 @@ #define APPL_DEBUG_PM_LINKST_IN_L0 0x11 #define APPL_DEBUG_LTSSM_STATE_MASK GENMASK(8, 3) #define APPL_DEBUG_LTSSM_STATE_SHIFT 3 -#define LTSSM_STATE_PRE_DETECT 5 +#define LTSSM_STATE_DETECT_QUIET 0x00 +#define LTSSM_STATE_DETECT_ACT 0x08 +#define LTSSM_STATE_PRE_DETECT_QUIET 0x28 +#define LTSSM_STATE_DETECT_WAIT 0x30 +#define LTSSM_STATE_L2_IDLE 0xa8 #define APPL_RADM_STATUS 0xE4 #define APPL_PM_XMT_TURNOFF_STATE BIT(0) @@ -210,7 +214,8 @@ #define PME_ACK_DELAY 100 /* 100 us */ #define PME_ACK_TIMEOUT 10000 /* 10 ms */ -#define LTSSM_TIMEOUT 50000 /* 50ms */ +#define LTSSM_DELAY 10000 /* 10 ms */ +#define LTSSM_TIMEOUT 120000 /* 120 ms */ #define GEN3_GEN4_EQ_PRESET_INIT 5 @@ -1663,23 +1668,22 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) data &= ~APPL_PINMUX_PEX_RST; appl_writel(pcie, data, APPL_PINMUX); + err = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data, + ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) || + ((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT), + LTSSM_DELAY, LTSSM_TIMEOUT); + if (err) + dev_info(pcie->dev, "Link didn't go to detect state\n"); + /* - * Some cards do not go to detect state even after de-asserting - * PERST#. So, de-assert LTSSM to bring link to detect state. + * Deassert LTSSM state to stop the state toggling between + * polling and detect. */ data = readl(pcie->appl_base + APPL_CTRL); data &= ~APPL_CTRL_LTSSM_EN; writel(data, pcie->appl_base + APPL_CTRL); - - err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, - data, - ((data & - APPL_DEBUG_LTSSM_STATE_MASK) >> - APPL_DEBUG_LTSSM_STATE_SHIFT) == - LTSSM_STATE_PRE_DETECT, - 1, LTSSM_TIMEOUT); - if (err) - dev_info(pcie->dev, "Link didn't go to detect state\n"); } /* * DBI registers may not be accessible after this as PLL-E would be @@ -1769,19 +1773,24 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) if (pcie->ep_state == EP_STATE_DISABLED) return; - /* Disable LTSSM */ + ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, + ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_PRE_DETECT_QUIET) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_WAIT) || + ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_L2_IDLE), + LTSSM_DELAY, LTSSM_TIMEOUT); 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Thu, 13 Oct 2022 11:39:44 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 07/21] PCI: tegra194: Disable direct speed change for EP Date: Fri, 14 Oct 2022 00:08:40 +0530 Message-ID: <20221013183854.21087-8-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT098:EE_|BL1PR12MB5302:EE_ X-MS-Office365-Filtering-Correlation-Id: 15b41eb3-eaff-47ff-e793-08daad4a5541 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nyb4t4+6JpeakYc7lbnqDah7DWhDw3JNZ4uL2uNjpk23XMQpjrFyczbGxfkYqkiWf+Q9BqQm9t1zZAZqEGSxIVn9YtvUDO3JIXPy02fHJY3KMlyVRWGqMkjLeQEz/PfxS75IeMjve5h73Sx4qc5NTWinKGA6VSZ8V7MakmQsROL7z8PzS9GerNAc9xD+mkYgOFCoxv4o2Ps6miutrHi4rEachw3vL4r5kDu9K7ZJajkRdoaqSD77TUyGPLLw9ya+mwypjk6YIg7aZqvp24geJb6Wf/iSGR7KhMYgIEtvf5raGknY/4jnM+m4d6mhNTCajidcEpKKSYlkCpH5rr36g2SfYejyiJ9+dEldJceP2c3BsSKqQcthbEe/bJ2mYI3waA5DrDGQ/1WYQZVIw74F0ihOUJFKoVsr/JAutkFl7y/mQmDOhqoUy48ebE92IzGa7p//xrDFi72/GQRNVYakK76Qz9Io4LjNRxZ4qnLcQJLOJR9JqqTfXso/ZBfF8Ls/629jd6O27oBHplIkVaAn9+gq33dzTgt9I4F07N8llY3MaFAAOXjBlU2Zn3rrzw20ysjX8qLDiJxameNH73dHoBoj+yAYnllE8crpxmayizQY44fuWGjP/RejYD3zrcpJzZf8BIG/rI/hEEi0saKtoZugJWvljsRHx81GW16xMoGImKrmiUbHFv0kevZQhXUdV2xqUokWIPGsZTxbEKQGJnyXrywxkH+vQsqBEG0+xurDYXeo10+tBRQRmTNGvY/IH8MmmwEbjf+CsAGY8pYxVAZ5EtzEyiXSUcVXViuTRgU= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(39860400002)(346002)(376002)(451199015)(36840700001)(40470700004)(46966006)(5660300002)(7416002)(1076003)(186003)(336012)(2616005)(7636003)(2906002)(356005)(41300700001)(26005)(8936002)(7696005)(921005)(82310400005)(86362001)(40460700003)(426003)(36756003)(83380400001)(47076005)(40480700001)(82740400003)(36860700001)(478600001)(316002)(110136005)(54906003)(8676002)(4326008)(70206006)(70586007)(6666004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:39:59.4195 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15b41eb3-eaff-47ff-e793-08daad4a5541 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT098.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5302 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Disable direct speed change for the endpoint to prevent it from initiating the speed change post physical layer link up at gen1. This leaves the speed change ownership with the host. Signed-off-by: Vidya Sagar --- V3: * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 897e2a22bcd3..dff38f73d9a7 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1929,6 +1929,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) reset_control_deassert(pcie->core_rst); + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_SPEED_CHANGE; + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + if (pcie->update_fc_fixup) { val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF); val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT; From patchwork Thu Oct 13 18:38:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006318 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8686EC43217 for ; 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Thu, 13 Oct 2022 11:39:51 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 08/21] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration Date: Fri, 14 Oct 2022 00:08:41 +0530 Message-ID: <20221013183854.21087-9-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT076:EE_|MW4PR12MB7334:EE_ X-MS-Office365-Filtering-Correlation-Id: df9accda-60ec-4ee7-375d-08daad4a59d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Gc0KjmIvxlROgoN238165KtSuw4LlDvCjJTp6QDGXw55GQLQXEPME2gFgggGp0P9ldJ0qziQOuxGmLmtrE7VX2ZObGKOUtveMaayywg7OGwZeBMqCa5SIrZzintVdsWz7WkMiIL1zIRNQDmdx+ZvtE42G2pUfSl3PYdddm/aJObAEOm0L7zZ37VTITviozxPvVLYvbpGBHiQG5gqc2hNWKBc4ouG0dgymM5GfRfu0hEhw2n2hrDHY5MP/Xeq+5g7k8Uprw0GW+wVLxWGYoJIuPz0LBgJy4cbLSmrKPZX1xVeH54pguoFiESrDHSUdYD1pX6K9rY9OE/GU51RambpbBrXIbtVt1rMFycneM44GMN11InvNJQ7nKQ3PFrb0zt+6FQJcMGpJbT4Ep3yYIUIep/M2k9UhST4XK9oreFIRRIk4OHyPUubAJt+Tq42Xm/Gar1Z2PQx16ncarh7ODjUhulFP8xZzKT3mxGiY8UIsiOJZYdZ4BaGYqIiYsYrrm/V5AcM6huRtxynHWZR648NDgifHKqCr96bLVCoUhomK4GlezH9hcm/REUApqNm1AGmtdSyx8k75vdYemaJaeMEd9WE0tuQfYcLteb6pNdCu5Z5RkPsZl4kXN3Y+Szp4FLWcntEpAg2wtkOGfTQehsimEIDuYJFDAGPKAiGk451EWbX59nP5UrQtX5uheZXXX+onYMvGSJixj6leYQXDTOlG3V7xdG+2lIbkoWteQWJLY3n/debTHZSK7jV77COzNV2ZhH3dMriA4hjAUwhTdqW7afEBTGZem8+2je8BxYx6o4= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(346002)(376002)(136003)(451199015)(40470700004)(46966006)(36840700001)(336012)(7416002)(5660300002)(7696005)(1076003)(186003)(2616005)(7636003)(2906002)(356005)(41300700001)(26005)(8936002)(82740400003)(82310400005)(921005)(86362001)(40480700001)(426003)(36756003)(83380400001)(36860700001)(47076005)(40460700003)(478600001)(316002)(110136005)(54906003)(70206006)(8676002)(70586007)(4326008)(6666004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:06.9033 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df9accda-60ec-4ee7-375d-08daad4a59d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT076.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7334 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change to Gen1 during initialization. This helps in the below surprise link down cases, - Surprise link down happens at Gen3/Gen4 link speed. - Surprise link down happens and external REFCLK is cut off, which causes UPHY PLL rate to deviate to an invalid rate. Signed-off-by: Vidya Sagar --- V3: * Removed "Reported-by: kernel test robot " based on Bjorn's review comment * Reworded the commit message V2: * Addressed review comment from test bot and Vinod drivers/phy/tegra/phy-tegra194-p2u.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c index 1415ca71de38..633e6b747275 100644 --- a/drivers/phy/tegra/phy-tegra194-p2u.c +++ b/drivers/phy/tegra/phy-tegra194-p2u.c @@ -15,6 +15,7 @@ #include #define P2U_CONTROL_CMN 0x74 +#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE BIT(13) #define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20) #define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0 @@ -85,8 +86,21 @@ static int tegra_p2u_power_on(struct phy *x) return 0; } +static int tegra_p2u_calibrate(struct phy *x) +{ + struct tegra_p2u *phy = phy_get_drvdata(x); + u32 val; + + val = p2u_readl(phy, P2U_CONTROL_CMN); + val |= P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE; + p2u_writel(phy, val, P2U_CONTROL_CMN); + + return 0; +} + static const struct phy_ops ops = { .power_on = tegra_p2u_power_on, + .calibrate = tegra_p2u_calibrate, .owner = THIS_MODULE, }; From patchwork Thu Oct 13 18:38:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006321 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9672FC433FE for ; Thu, 13 Oct 2022 18:43:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230246AbiJMSn2 (ORCPT ); Thu, 13 Oct 2022 14:43:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229871AbiJMSnC (ORCPT ); Thu, 13 Oct 2022 14:43:02 -0400 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1anam02on2047.outbound.protection.outlook.com [40.107.96.47]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6A2C1929D; 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Thu, 13 Oct 2022 11:40:02 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:40:02 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:39:58 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 09/21] PCI: tegra194: Calibrate P2U for endpoint mode Date: Fri, 14 Oct 2022 00:08:42 +0530 Message-ID: <20221013183854.21087-10-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT051:EE_|MN0PR12MB5859:EE_ X-MS-Office365-Filtering-Correlation-Id: d168f173-7866-4d8c-54f2-08daad4a5d83 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:13.2232 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d168f173-7866-4d8c-54f2-08daad4a5d83 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5859 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Calibrate P2U for endpoint controller to request UPHY PLL rate change to Gen1 during initialization. This helps to reset stale PLL state from the previous bad link state. Signed-off-by: Vidya Sagar --- V3: * Reworded the commit message V2: * None drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index dff38f73d9a7..910dc6c2154e 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1130,6 +1130,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie) ret = phy_power_on(pcie->phys[i]); if (ret < 0) goto phy_exit; + + if (pcie->of_data->mode == DW_PCIE_EP_TYPE) + phy_calibrate(pcie->phys[i]); } return 0; From patchwork Thu Oct 13 18:38:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006325 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B63E0C4321E for ; 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Thu, 13 Oct 2022 11:40:05 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 10/21] PCI: tegra194: Free resources during controller deinitialization Date: Fri, 14 Oct 2022 00:08:43 +0530 Message-ID: <20221013183854.21087-11-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT038:EE_|DS7PR12MB5911:EE_ X-MS-Office365-Filtering-Correlation-Id: af831bb4-a975-43eb-c292-08daad4a600c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4zcgVGdQjalMWiBTtbmiw7RSxl8i690JhwLeJIfb3Bwn8H06iSRGvE8qJU9eFydCmtBuHjrrqScS0xNFyDVaemaZz6k0JaohPYkbYOdslu2HcbtRvzE7xg0axqHaThf80djaqkKbhTI0K4BypTDiNn4vv1oaqIAilvcYNVIPuPmBVRd08BTYAeODBsJeG5tc+D83rs/gmp7SFCC3Wrqk+QJLDXMXSgGQ4oth6mw6uNA0ZsvlSE2MGdg5k45hmCzraffqjW+BzrJaH4av6479Z50nfCrBJTCWBSPhdte8HCUC9p9OrOAes3NWHHPuyIxqfzU4LtSSROl2Y3yCZ0U3W2KR9qf2/quES2O0sVkOhHIBxvj4E0YWNL13Df4r/kNWisv5NDLj/Kx7Ll1bgIU8dIsW1Es6wPLj9nN4CiTQ2r+WC5ugZCqX4Qco8y8bmosFBHg+1i0c2v7iNSiVIbkS21f6zw4IypsvktqYTFHdtDeC0x9t5A02NjckE0JKITRhaxtXBMJmqMkUEX+rOudts/IJNrHdHN7YtwRw0e8Wp+eXoI8a/RBI2SGgOvOiqcXtDYqIru3mNiCUj3WB/hQMFUJHkRXPrwoVzdOOK8vByj/fHV7/H2hTG5w5bn0NqmSKL0btMRUWMvZ/fD5KedHNi0UUcX1wPtatetDTcMcUgzeVRt13m1bI/C34Ou5KX9jO5ZvVkeBKYvEwAvA7kcqYq1thpYF7KoKBKsL0OJyPN993LyjrZZ3iJsVJOCjbzbP/V6R10snMtpQ0bRANg0stPLLaSYWX/++yTTepwXt/PJY= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(346002)(396003)(39860400002)(136003)(451199015)(36840700001)(40470700004)(46966006)(26005)(7696005)(36860700001)(82740400003)(4326008)(316002)(8676002)(70206006)(921005)(70586007)(7636003)(86362001)(40460700003)(36756003)(40480700001)(356005)(82310400005)(83380400001)(186003)(6666004)(47076005)(2616005)(478600001)(54906003)(2906002)(41300700001)(336012)(5660300002)(7416002)(1076003)(8936002)(110136005)(426003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:17.5418 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af831bb4-a975-43eb-c292-08daad4a600c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5911 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Call dw_pcie_ep_deinit() during controller deinitialization to free the resources allocated in common DesignWare driver. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 910dc6c2154e..7820bf4b9786 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1770,12 +1770,16 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) { + struct dw_pcie *pci = &pcie->pci; + struct dw_pcie_ep *ep = &pci->ep; u32 val; int ret; if (pcie->ep_state == EP_STATE_DISABLED) return; + dw_pcie_ep_deinit_notify(ep); + ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) || ((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) || From patchwork Thu Oct 13 18:38:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006323 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EF26C4167D for ; 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Thu, 13 Oct 2022 11:40:12 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 11/21] PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration Date: Fri, 14 Oct 2022 00:08:44 +0530 Message-ID: <20221013183854.21087-12-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT051:EE_|BL1PR12MB5363:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a27a0a5-6cfa-41e7-6a96-08daad4a64bd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Bhx0jkYdVo6kBP2mJy8iVbRXgADkH2qKf/gju/KAkWwXUw9lhexqAzpdHwK0rBXgxeZNCD1W5E1RB/E0NIHEUO8BGw2dEl8XoAmre3ZOnyNIpHJcBUgSEyX2CGWXEfe67BJvLJJEhnKNvbfcREbZR8wOhbwcV0YVwhJ393nvD1aaFzaphuFhRoQiU8g8RTcO7ZHj84/BmRvQtzp9XODTznpiWhlltVEQSkbshx/e2PetksF55q6WR4D7NLmsG6pj8I4wX1X/5ONBPkZsDWl4AXEKOF2dkvFOESaQm6e63AwAbiOaROlIYCocoxFpRJZP8esxiCs0wM6/cNq+0fGopdvuzSJ1pd9qBStnhAq/x2L7rUXWF9En+bZK2kLZoN+HEJeD2b+vGJpk8kb/NVpGvdHHOmOFd80gk8QaCMM3wOs4A77HQIV5qc4j/CqdTWOjqSLT+HSiRcoI32/RU+WR/xmv7tgyHf1VNS81RP52BYigMbLcjIXvoL1XEuWXpVE8WL7H3H3elCXaLPusFpWwqloyuJfoskNgypvB9N4KGTZjcr+NvA2o3c1UchVeJddc8TIz3OFJ/K004u4tMw3bHj61eESM+2EyGamjaFf5w/V7GLPi/Bft96SOS1o1gntIw82BNRlYQZoytY9GNAFvgeGQCTpna92XIKCPWD8V7zGgY1T0WLqbiZbuJs8DuXFIrlvnDQoRBWmOjdv09cElLfsrvnuirF5eL7nJ0+aKSywPn1mTISb3MVvH4rLRVhkheTufVW9R+shVGsVTzkTyT3leOApWhtABBSQ5lOL2a1Y= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(39860400002)(346002)(376002)(451199015)(36840700001)(40470700004)(46966006)(5660300002)(7416002)(1076003)(186003)(336012)(2616005)(7636003)(2906002)(356005)(41300700001)(26005)(8936002)(7696005)(921005)(82310400005)(86362001)(40460700003)(426003)(36756003)(83380400001)(47076005)(40480700001)(82740400003)(36860700001)(478600001)(316002)(110136005)(54906003)(8676002)(4326008)(70206006)(70586007)(6666004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:25.3635 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a27a0a5-6cfa-41e7-6a96-08daad4a64bd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5363 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra PCIe endpoint has a common interrupt that notifies hardware events like link up, LTR send, etc. DMA completion event is also notified over this interrupt. Remove IRQF_ONESHOT flag from interrupt registration and allow DMA driver to share this interrupt. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 7820bf4b9786..786e5d5f43b9 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2354,7 +2354,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) ret = devm_request_threaded_irq(dev, pp->irq, tegra_pcie_ep_hard_irq, tegra_pcie_ep_irq_thread, - IRQF_SHARED | IRQF_ONESHOT, + IRQF_SHARED, "tegra-pcie-ep-intr", pcie); if (ret) { dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, From patchwork Thu Oct 13 18:38:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006320 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20CD1C4332F for ; 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Thu, 13 Oct 2022 11:40:18 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 12/21] PCI: tegra194: Enable DMA interrupt Date: Fri, 14 Oct 2022 00:08:45 +0530 Message-ID: <20221013183854.21087-13-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT074:EE_|DM4PR12MB6568:EE_ X-MS-Office365-Filtering-Correlation-Id: 02db9b6d-fa3c-4d5b-76cf-08daad4a6764 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: T8ujoV2wIcLBb9jzuOlqb/HDbNjMhUeJE9w6uZIJIT0X/dJRijyZUIiMJnT9Y1ZMHbKI7eBFjyzh7mfYgRA3ZEjY314mEUoihbcamYDAf74c0/CrhQTPXnrMsvC0rJa1AyX1IUHljo9om/O/mQMfnl0Lj3PaPgrIcZ4DrhN43rY3LoFAN9e58f/x3zkyZ72PTZm4hhpd6yvKr7ZGMJOOPWQuR/ova1CA4608h9RP/cdQnOLCLlaP7DLRGmGZ139e1yecOUECX5EdaHGNmnGCfK4SoGGRLha7y8Am0vxvGRbZCxO8sjKik1y/yMo+y7cQlCfO8RiBgDf2XRBEgPu76x3N87rFJ3PqLmew5trA6cGkIg4yDrAgFAxdkLOroU9qxOCG3uZeJZSu+CSoGJUX1Tbo8pD7Za7cZmw8FurUL9kwK+6w3tuOCLkh3kCCsRyPrWWquLvr4jN/PRqk1KJxwmLSxaf48Xh4/1+2Wxx7q9lh3Aayeykcui66Z3YCLWMwbd9Vm8+hTGMQaG4D/9ML/yuF+JZrCtwkLAStYzIsLAqz+UURhgQiYyRBdus3YKOswGILzUGgdN1djlfYyQA74D5sU7u4RpWuKm1rAgkzkAUFc3TFqoqnqwTqkB3SQMXjciVwevJhBHM4Kgzp7wCZpZ7T9EOF/GCXQ8x7hyRtCw3i6JZ9ZWxW2BCAMrcvBDKzqvi4QDv2cyabKWB+/U9gpQsIATOAPLUlGiv1wxVB2eAXwRAAEozh8XE2z3TmDK/J4v3otnsb2ktctIM2V/2gqdV9ayyZyEIDhNJNZ8qK2z4= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(346002)(136003)(376002)(451199015)(40470700004)(46966006)(36840700001)(5660300002)(7416002)(1076003)(186003)(336012)(2616005)(7636003)(2906002)(356005)(41300700001)(26005)(8936002)(7696005)(426003)(921005)(82310400005)(86362001)(40460700003)(36756003)(47076005)(40480700001)(82740400003)(36860700001)(316002)(110136005)(54906003)(478600001)(70206006)(8676002)(70586007)(4326008)(6666004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:29.8606 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02db9b6d-fa3c-4d5b-76cf-08daad4a6764 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT074.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6568 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable DMA interrupt to support Tegra PCIe DMA in both Root port and Endpoint modes. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 786e5d5f43b9..a1c3481585c9 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -94,6 +94,7 @@ #define APPL_INTR_EN_L1_8_0 0x44 #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN BIT(2) #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN BIT(3) +#define APPL_INTR_EN_L1_8_EDMA_INT_EN BIT(6) #define APPL_INTR_EN_L1_8_INTX_EN BIT(11) #define APPL_INTR_EN_L1_8_AER_INT_EN BIT(15) @@ -552,6 +553,13 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) spurious = 0; } + if (status_l0 & APPL_INTR_STATUS_L0_INT_INT) { + status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0); + /* Interrupt is handled by dma driver, don't treat it as spurious */ + if (status_l1 & APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK) + spurious = 0; + } + if (spurious) { dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", status_l0); @@ -781,6 +789,7 @@ static void tegra_pcie_enable_legacy_interrupts(struct dw_pcie_rp *pp) val |= APPL_INTR_EN_L1_8_INTX_EN; val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN; val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN; + val |= APPL_INTR_EN_L1_8_EDMA_INT_EN; if (IS_ENABLED(CONFIG_PCIEAER)) val |= APPL_INTR_EN_L1_8_AER_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); @@ -1927,6 +1936,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val |= APPL_INTR_EN_L0_0_SYS_INTR_EN; val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN; val |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN; + val |= APPL_INTR_EN_L0_0_INT_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L0_0); val = appl_readl(pcie, APPL_INTR_EN_L1_0_0); @@ -1934,6 +1944,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_0_0); + val = appl_readl(pcie, APPL_INTR_EN_L1_8_0); + val |= APPL_INTR_EN_L1_8_EDMA_INT_EN; + appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); + reset_control_deassert(pcie->core_rst); val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); From patchwork Thu Oct 13 18:38:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006327 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4645CC4167D for ; Thu, 13 Oct 2022 18:44:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231393AbiJMSoJ (ORCPT ); Thu, 13 Oct 2022 14:44:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231387AbiJMSnD (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:33.3760 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f45e2618-a5fa-4631-7afb-08daad4a697a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT074.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4121 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org When PCIe link goes down, hardware can retrain the link and try to link up. To enable this feature, program the APPL_CTRL register with hardware hot reset with immediate LTSSM enable mode. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index a1c3481585c9..78ee0f713e71 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1913,6 +1913,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val = appl_readl(pcie, APPL_CTRL); val |= APPL_CTRL_SYS_PRE_DET_STATE; val |= APPL_CTRL_HW_HOT_RST_EN; + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << APPL_CTRL_HW_HOT_RST_MODE_SHIFT); + val |= (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN << APPL_CTRL_HW_HOT_RST_MODE_SHIFT); appl_writel(pcie, val, APPL_CTRL); val = appl_readl(pcie, APPL_CFG_MISC); From patchwork Thu Oct 13 18:38:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006338 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A629BC4321E for ; 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Thu, 13 Oct 2022 11:40:31 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 14/21] PCI: tegra194: Allow system suspend when the Endpoint link is not up Date: Fri, 14 Oct 2022 00:08:47 +0530 Message-ID: <20221013183854.21087-15-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT027:EE_|BN9PR12MB5147:EE_ X-MS-Office365-Filtering-Correlation-Id: f5492732-131d-41d9-da2f-08daad4a7193 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: weHfSMUYOIFpHsz2RS1b+Vy93QLGuPxdmvqhYqwO3qqyCkX4gyYQ0jMbeH+/c9FnOyqFhNelu57lSu4DdmHxYC5DTWWZgC4nFIswjRy7rewTUHADrHp4WW/p0eQ6UwaPDJqvs2yJcaprlrtCeRbSJ1Q3pt9GFWqIbeHi9Azfgm9xD2gmND8lFr15gFxjWpE7NLQmZbwLui6t8GIdD1AGnPrHMy+pAvvAse77xb8Zjp4wb1AcV11mcUVPoihWr1VRUBII965ay2UYPEz8RFElQlqSqanG7fHySyykmk+99YTPrfq8z8iPUMaBk/ToW/DiflADLIltUal21Ewh0EZVZYKTrHRXdAg5XFj0Al80pX2mB5GSPQVitDNRm3drehf9cGOTh1KWNcetDJJK8gNWwPGpLwm4d/ol6ZECydiabwL7GNoVoTNOO33sfiB1OTXvdNCzwQmy9/8wJoqoMpmPtbiq0Gxdd6AMYtPVw2QCj5ZspMFRLXtPlB8Fvk13ulo5MRjJtoFT61HA9Obt9HHnFfN6BtKFZtSLjiwpq/Vn7qg7RWjG0Thfkya9uFVZYzsUbUj1hBF8h7QpniDs+R940yKkeiezdcIDEemI+Ig2RFFFVDj3+kvhZdrLWzLGysFS/znMC7IAZkzVQvfkX9ZpbjQXsvyQ0SHYRgX5Yq69CYOqZNZkAb3HmAYFuzkbmrupX3OlwL7tdyWiEBAWyKnDFTCzL5Na/55Gmu7F62/7d0A87doHnQUWGuh4bQEDm9XewTlhDZuLfIcBlysC5IId0zl/lx/ik0EpWdksXK0lpTk= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(136003)(39860400002)(376002)(451199015)(40470700004)(36840700001)(46966006)(336012)(186003)(2616005)(47076005)(1076003)(83380400001)(7636003)(921005)(356005)(86362001)(7416002)(36860700001)(82740400003)(426003)(2906002)(5660300002)(41300700001)(40460700003)(4326008)(15650500001)(8936002)(40480700001)(82310400005)(110136005)(8676002)(6666004)(478600001)(26005)(7696005)(316002)(54906003)(70206006)(70586007)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:46.8859 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5492732-131d-41d9-da2f-08daad4a7193 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5147 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Only a Root port initiates the L2 sequence. PCIe link is kept in L2 state during suspend. If Endpoint mode is enabled and the link is up, the software cannot proceed with suspend. However, when the PCIe Endpoint driver is probed, but the PCIe link is not up, Tegra can go into suspend state. So, allow system to suspend in this case. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 78ee0f713e71..e6fd713e9868 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2425,8 +2425,14 @@ static int tegra_pcie_dw_suspend_late(struct device *dev) u32 val; if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { - dev_err(dev, "Failed to Suspend as Tegra PCIe is in EP mode\n"); - return -EPERM; + disable_irq(pcie->pex_rst_irq); + + if (pcie->ep_state == EP_STATE_ENABLED) { + dev_err(dev, "Tegra PCIe is in EP mode, suspend not allowed"); + return -EPERM; + } else { + return 0; + } } if (!pcie->link_state && !pcie->slot_pluggable) @@ -2448,6 +2454,9 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) { struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); + if (pcie->of_data->mode == DW_PCIE_EP_TYPE) + return 0; + if (!pcie->link_state && !pcie->slot_pluggable) return 0; @@ -2463,6 +2472,9 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev) struct tegra_pcie_dw *pcie = dev_get_drvdata(dev); int ret; + if (pcie->of_data->mode == DW_PCIE_EP_TYPE) + return 0; + if (!pcie->link_state && !pcie->slot_pluggable) return 0; @@ -2495,8 +2507,8 @@ static int tegra_pcie_dw_resume_early(struct device *dev) u32 val; if (pcie->of_data->mode == DW_PCIE_EP_TYPE) { - dev_err(dev, "Suspend is not supported in EP mode"); - return -ENOTSUPP; + enable_irq(pcie->pex_rst_irq); + return 0; } if (!pcie->link_state && !pcie->slot_pluggable) From patchwork Thu Oct 13 18:38:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006322 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D412EC4332F for ; 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Thu, 13 Oct 2022 11:40:38 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 15/21] PCI: tegra194: Disable L1.2 capability of Tegra234 EP Date: Fri, 14 Oct 2022 00:08:48 +0530 Message-ID: <20221013183854.21087-16-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT081:EE_|DM4PR12MB6087:EE_ X-MS-Office365-Filtering-Correlation-Id: febfad2c-a646-48ad-0091-08daad4a7258 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9B877wshN5K0e30wFa9Oq7T2VX5j74eq7lnBOuD3WcIiHj7oq+NLAoUqKzcjYNYaZ3+V6ghtijzQJIjoPIDZXOtuHixZKucUIVWi78RvKzbbuf0cG6yFHSo6BJbqzNdYljiPoCJHl09Bso2NomxdRg71B7PGNxzZTJRWsREu071vS+AFOIAxewpyq9acAs+UDJFGwGD3ZJ01fITE+4YSngOM/u+JJ1ojQ6xfLnrvx0y7V9XEiszXsT0je+ObRycexBccgVfJaFYiordiBbja0xNKIfkDuc6RK4Lx5aYLt6FCy76LKzAGSxqW6PxN2VGXc7FgQoem1fAaWc6+G25eLOTttzBcK6UxkdI5OWK2MmP3OZDSHqkacrSzeLZ5coj3imWS/OGAuWPpSwGpdg9c0mwvJzFWQSk36jkoXmAo5fP27et+kdSlGkfAJ8tnnZQUA3YkK4i5iidG8BtAn8exP+RjZfRNeHDIHMWPhmT3oelb98EhSutnF9mmbxV9yhPU+ZDtPsI0c2P/bEaqojkAyUZ/He425dYOuuXsG+Bgw8qDz0fqdMKEPfIGLTSzFv7qffs2uE2FEiecKm9hlCGL/kO4t3CD/BnXxkkrG6D+iOgFFfVoytTS3rtKGRvJltYYfpBXRzMlMaF1V4Y+vtw2FjOc6BbYMH3pz6WkGXZFoPWJ8kON614ijDUlTFaIZ6Ie4bvziHRZ1SfLy3xSXe9S6K0Gotz1hmRHoDPoX6imfR53zPzpZDcNd1+/rZUG8dh3TsLMlrrLQW5l2janmjo6LAhbM2yEtZ8MeGv8MrOXJa0= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(346002)(376002)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(186003)(5660300002)(36860700001)(54906003)(41300700001)(47076005)(86362001)(426003)(2616005)(40460700003)(40480700001)(83380400001)(478600001)(7416002)(336012)(2906002)(1076003)(316002)(6666004)(36756003)(110136005)(356005)(7696005)(82310400005)(7636003)(82740400003)(921005)(70206006)(26005)(8936002)(70586007)(4326008)(8676002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:48.2339 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: febfad2c-a646-48ad-0091-08daad4a7258 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT081.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6087 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org When Tegra234 is operating in the endpoint mode with L1.2 enabled, PCIe link goes down during L1.2 exit. This is because Tegra234 is powering up UPHY PLL immediately without making sure that the REFCLK is stable. This is causing UPHY PLL to not lock to the correct frequency and leading to link going down. There is no hardware fix for this, hence do not advertise the L1.2 capability in the endpoint mode. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index e6fd713e9868..d592cf68b02c 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -246,6 +246,7 @@ struct tegra_pcie_dw_of_data { bool has_sbr_reset_fix; bool has_l1ss_exit_fix; bool has_ltr_req_fix; + bool disable_l1_2; u32 cdm_chk_int_en_bit; u32 gen4_preset_vec; u8 n_fts[2]; @@ -1967,10 +1968,11 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) init_host_aspm(pcie); /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ - if (!pcie->supports_clkreq) { + if (!pcie->supports_clkreq) disable_aspm_l11(pcie); + + if (!pcie->supports_clkreq || pcie->of_data->disable_l1_2) disable_aspm_l12(pcie); - } if (!pcie->of_data->has_l1ss_exit_fix) { val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); @@ -2589,6 +2591,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = { .mode = DW_PCIE_EP_TYPE, .has_l1ss_exit_fix = true, .has_ltr_req_fix = true, + .disable_l1_2 = true, .cdm_chk_int_en_bit = BIT(18), /* Gen4 - 6, 8 and 9 presets enabled */ .gen4_preset_vec = 0x340, From patchwork Thu Oct 13 18:38:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006335 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D9FFC4332F for ; Thu, 13 Oct 2022 18:47:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232180AbiJMSrA (ORCPT ); Thu, 13 Oct 2022 14:47:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232235AbiJMSqX (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:40:58.6299 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe24e336-400c-4a5d-ee96-08daad4a7887 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5892 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org LTR message should be sent as soon as the root port enables LTR in the endpoint. Set snoop & no snoop LTR timing and LTR message request before PCIe links up. This ensures that LTR message is sent upstream as soon as LTR is enabled. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index d592cf68b02c..23ca97401339 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -493,11 +493,6 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg) if (val & PCI_COMMAND_MASTER) { ktime_t timeout; - /* 110us for both snoop and no-snoop */ - val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ; - val |= (val << LTR_MST_NO_SNOOP_SHIFT); - appl_writel(pcie, val, APPL_LTR_MSG_1); - /* Send LTR upstream */ val = appl_readl(pcie, APPL_LTR_MSG_2); val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE; @@ -1951,6 +1946,11 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val |= APPL_INTR_EN_L1_8_EDMA_INT_EN; appl_writel(pcie, val, APPL_INTR_EN_L1_8_0); + /* 110us for both snoop and no-snoop */ + val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ; + val |= (val << LTR_MST_NO_SNOOP_SHIFT); + appl_writel(pcie, val, APPL_LTR_MSG_1); + reset_control_deassert(pcie->core_rst); val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); From patchwork Thu Oct 13 18:38:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006326 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1F2DC3A59D for ; Thu, 13 Oct 2022 18:44:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230505AbiJMSoG (ORCPT ); Thu, 13 Oct 2022 14:44:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232253AbiJMSnn (ORCPT ); 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Thu, 13 Oct 2022 11:40:55 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Thu, 13 Oct 2022 11:40:55 -0700 Received: from vidyas-desktop.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.29 via Frontend Transport; Thu, 13 Oct 2022 11:40:50 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 17/21] PCI: tegra194: Reduce AXI slave timeout value Date: Fri, 14 Oct 2022 00:08:50 +0530 Message-ID: <20221013183854.21087-18-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT106:EE_|SJ1PR12MB6123:EE_ X-MS-Office365-Filtering-Correlation-Id: e6fd0f5b-70bc-41f4-0daf-08daad4a7adf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:41:02.4938 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6fd0f5b-70bc-41f4-0daf-08daad4a7adf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT106.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6123 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Reduce the AXI slave timeout value to 7ms to be in line with the CBB logic's timeout value and to avoid CBB reporting errors because of no response from the PCIe IPs AXI slave logic for configuration space accesses through ECAM when the PCIe link is down. Also, set the Completion Timeout value to Range-A: 1ms~10ms to be inline with the AXI timeout value. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 23ca97401339..7890e0c0c0d2 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -198,6 +198,12 @@ #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFFFFFF 1 #define AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 2 +#define PORT_LOGIC_AMBA_LINK_TIMEOUT 0x8D4 +#define AMBA_LINK_TIMEOUT_PERIOD_MASK GENMASK(7, 0) +#define AMBA_LINK_TIMEOUT_PERIOD_VAL 0x7 + +#define PCI_EXP_DEVCTL2_CPL_TO_VAL 0x2 /* Range-A: 1ms to 10ms */ + #define MSIX_ADDR_MATCH_LOW_OFF 0x940 #define MSIX_ADDR_MATCH_LOW_OFF_EN BIT(0) #define MSIX_ADDR_MATCH_LOW_OFF_MASK GENMASK(31, 2) @@ -922,6 +928,18 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) AMBA_ERROR_RESPONSE_CRS_SHIFT); dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val); + /* Reduce the AXI slave Timeout value to 7ms */ + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_LINK_TIMEOUT); + val &= ~AMBA_LINK_TIMEOUT_PERIOD_MASK; + val |= AMBA_LINK_TIMEOUT_PERIOD_VAL; + dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_LINK_TIMEOUT, val); + + /* Set the Completion Timeout value in 1ms~10ms range */ + val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2); + val_16 &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT; + val_16 |= PCI_EXP_DEVCTL2_CPL_TO_VAL; + dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2, val_16); + /* Configure Max lane width from DT */ val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); val &= ~PCI_EXP_LNKCAP_MLW; @@ -1988,6 +2006,12 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B; dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16); + /* Set the Completion Timeout value in 1ms~10ms range */ + val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2); + val_16 &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT; + val_16 |= PCI_EXP_DEVCTL2_CPL_TO_VAL; + dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL2, val_16); + /* Clear Slot Clock Configuration bit if SRNS configuration */ if (pcie->enable_srns) { val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + From patchwork Thu Oct 13 18:38:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006324 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B70CC352A1 for ; Thu, 13 Oct 2022 18:44:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230093AbiJMSoF (ORCPT ); Thu, 13 Oct 2022 14:44:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232267AbiJMSnr (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:41:09.2633 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0345859-7829-4ed5-d5cd-08daad4a7ee0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6179 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org As per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe endpoint device should be in D3 state to assert wake# pin. This takes precedence over PCI Express Base r4.0 v1.0 September 27-2017, 5.2 Link State Power Management which states that the device can be put into D0 state before taking the link to L2 state. So, to enable the wake functionality for endpoints, do not force the devices to D0 state before taking the link to L2 state. There is no functional issue with the endpoints where the link doesn't go into L2 state (the reason why the earlier change was made in the first place) as the root port proceeds with the usual flow post PME timeout. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 41 ---------------------- 1 file changed, 41 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 7890e0c0c0d2..3baf1a26fe68 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1358,44 +1358,6 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, return 0; } -static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) -{ - struct dw_pcie_rp *pp = &pcie->pci.pp; - struct pci_bus *child, *root_bus = NULL; - struct pci_dev *pdev; - - /* - * link doesn't go into L2 state with some of the endpoints with Tegra - * if they are not in D0 state. So, need to make sure that immediate - * downstream devices are in D0 state before sending PME_TurnOff to put - * link into L2 state. - * This is as per PCI Express Base r4.0 v1.0 September 27-2017, - * 5.2 Link State Power Management (Page #428). - */ - - list_for_each_entry(child, &pp->bridge->bus->children, node) { - /* Bring downstream devices to D0 if they are not already in */ - if (child->parent == pp->bridge->bus) { - root_bus = child; - break; - } - } - - if (!root_bus) { - dev_err(pcie->dev, "Failed to find downstream devices\n"); - return; - } - - list_for_each_entry(pdev, &root_bus->devices, bus_list) { - if (PCI_SLOT(pdev->devfn) == 0) { - if (pci_set_power_state(pdev, PCI_D0)) - dev_err(pcie->dev, - "Failed to transition %s to D0 state\n", - dev_name(&pdev->dev)); - } - } -} - static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie) { pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); @@ -1725,7 +1687,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) { - tegra_pcie_downstream_dev_to_D0(pcie); dw_pcie_host_deinit(&pcie->pci.pp); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); @@ -2486,7 +2447,6 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) if (!pcie->link_state && !pcie->slot_pluggable) return 0; - tegra_pcie_downstream_dev_to_D0(pcie); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); @@ -2565,7 +2525,6 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev) if (pcie->slot_pluggable) unregister_gpio_hotplug_slot(&pcie->hp_slot); debugfs_remove_recursive(pcie->debugfs); - tegra_pcie_downstream_dev_to_D0(pcie); disable_irq(pcie->pci.pp.irq); if (IS_ENABLED(CONFIG_PCI_MSI)) From patchwork Thu Oct 13 18:38:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 13006329 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8385C4167E for ; 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Thu, 13 Oct 2022 11:41:04 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , Subject: [PATCH V3 19/21] PCI: tegra194: Free up EP resources during remove() Date: Fri, 14 Oct 2022 00:08:52 +0530 Message-ID: <20221013183854.21087-20-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221013183854.21087-1-vidyas@nvidia.com> References: <20221013183854.21087-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT061:EE_|SN7PR12MB6861:EE_ X-MS-Office365-Filtering-Correlation-Id: 816719c3-e7d0-437b-1cc2-08daad4a8390 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Nl0onNJad4/pqYD7MRyvV31PIZupUaaV+G/yMgCiUH25oaTJ0C5XPKcsbW+euySu+h5CjJs4RmQweBsBttGGfCLnPpytfAbB4gCfcNpQH6ZYctGwMLCX8+UrymCvjVEKtZxHbH0CfTBFuWkM1v0CwVAKONe2MDa788pC6Z+qUCIM9njR1myhN7/jDwIfqgXFLTBt5kMsK4XiozomQIf7SU2n6/yWw0+QTCXIkYHnjDrzkDKLAz5AEmf3GkaGgea9uNCNwc1IDX8BbHJXoJ2lcUyiq3PEjDxy/x1clFVflLHsYs0Q7pDB4TvbtGUYmrRZ6qzAbFKu8a8akqWi8hNr/pb9lcA/G/Lg1/U2GOzHqrcLaf9y8wCk7UejFJct4945Bp/b/Bx8r+sb3CTNEaJCTdjgd5laC3qRO1JXYXgCbx3H5Hqj0+XkOHI66eSJ/678q4rUYDvkSZuNfUHbICJYCKSmG6f9zMKU0cs9cRM299vbAfpLcodKZbUiqQLLhhP7+9OOngJhAdm0bCS9sb7cOH7ZtwDMCGV9x+NSimyFhW0T5aBwHte05pMxAbGSgyj8heSRpzFIsWWsIquoEXZpo5c6vXq4/myc69WvSBkrmt/C1XbIO9cSBWkX+/i1/HTHeGdpuBwfiphLKlrNJs3jkr8EaIHyhFOPTYPwYM1EHmPOsX4+s1VNevY5wk2JEZK1KDMV5oco9Y09zhXljGGl3jdSj6+YJqd79nC0LB3AmlR6RrAZ21/Wrb18l1MOQoyZc/KUS/BrxkP2QlQIGeMnJFm4JfBLjPncUqp5uV4azvs= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(376002)(346002)(136003)(451199015)(36840700001)(40470700004)(46966006)(54906003)(110136005)(426003)(4326008)(40460700003)(6666004)(36756003)(316002)(70206006)(70586007)(7696005)(47076005)(478600001)(7636003)(356005)(1076003)(186003)(40480700001)(921005)(82740400003)(336012)(2616005)(86362001)(36860700001)(26005)(82310400005)(8936002)(5660300002)(7416002)(8676002)(2906002)(41300700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:41:17.1385 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 816719c3-e7d0-437b-1cc2-08daad4a8390 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6861 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Free up the resources during remove() that were acquired by the DesignWare driver for the endpoint mode during proble(). Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 3baf1a26fe68..c88c36d85ee5 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2383,6 +2383,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) static int tegra_pcie_dw_remove(struct platform_device *pdev) { struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev); + struct dw_pcie_ep *ep = &pcie->pci.ep; if (pcie->of_data->mode == DW_PCIE_RC_TYPE) { if (!pcie->link_state && !pcie->slot_pluggable) @@ -2396,6 +2397,7 @@ static int tegra_pcie_dw_remove(struct platform_device *pdev) } else { disable_irq(pcie->pex_rst_irq); pex_ep_event_pex_rst_assert(pcie); + dw_pcie_ep_exit(ep); } pm_runtime_disable(pcie->dev); From patchwork Thu Oct 13 18:38:53 2022 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:41:20.7320 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29b66c5d-8da7-4b57-7170-08daad4a85b4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5709 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra supports PCIe core clock monitoring for any rate changes that may be happening because of the link speed changes. This is useful in tracking any changes in the core clock that are not initiated by the software. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series .../devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml | 6 +++++- .../devicetree/bindings/pci/nvidia,tegra194-pcie.yaml | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml index a24fb8307d29..7c6900802f04 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml @@ -55,12 +55,16 @@ properties: - const: intr clocks: + minItems: 1 items: - - description: module clock + - description: module's core clock + - description: module's monitor clock clock-names: + minItems: 1 items: - const: core + - const: core_m resets: items: diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml index 75da3e8eecb9..aaaa238e6dc1 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml @@ -54,12 +54,16 @@ properties: - const: msi clocks: + minItems: 1 items: - - description: module clock + - description: module's core clock + - description: module's monitor clock clock-names: + minItems: 1 items: - const: core + - const: core_m resets: items: From patchwork Thu Oct 13 18:38:54 2022 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2022 18:41:29.8247 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca3fdb91-1640-4f59-1c4a-08daad4a8b1b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6776 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra supports PCIe core clock monitoring for any rate changes that may be happening because of the link speed changes. This is useful in tracking any changes in the core clock that are not initiated by the software. This patch adds support to parse the monitor clock info from device-tree and enable it if present. Signed-off-by: Vidya Sagar --- V3: * This is a new patch in this series drivers/pci/controller/dwc/pcie-tegra194.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index c88c36d85ee5..28512dc60172 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -265,6 +265,7 @@ struct tegra_pcie_dw { struct resource *atu_dma_res; void __iomem *appl_base; struct clk *core_clk; + struct clk *core_clk_m; struct reset_control *core_apb_rst; struct reset_control *core_rst; struct dw_pcie pci; @@ -978,6 +979,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) } clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); + if (clk_prepare_enable(pcie->core_clk_m)) + dev_err(pci->dev, "Failed to enable core monitor clock\n"); return 0; } @@ -1050,6 +1053,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) val &= ~PCI_DLF_EXCHANGE_ENABLE; dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val); + /* + * core_clk_m is enabled as part of host_init callback in + * dw_pcie_host_init(). Disable the clock since below + * tegra_pcie_dw_host_init() will enable it again. + */ + clk_disable_unprepare(pcie->core_clk_m); tegra_pcie_dw_host_init(pp); dw_pcie_setup_rc(pp); @@ -1059,7 +1068,8 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & PCI_EXP_LNKSTA_CLS; - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); + if (!pcie->core_clk_m) + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); tegra_pcie_enable_interrupts(pp); @@ -1687,6 +1697,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) { + clk_disable_unprepare(pcie->core_clk_m); dw_pcie_host_deinit(&pcie->pci.pp); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); @@ -2266,6 +2277,13 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) return PTR_ERR(pcie->core_clk); } + pcie->core_clk_m = devm_clk_get_optional(dev, "core_m"); + if (IS_ERR(pcie->core_clk_m)) { + dev_err(dev, "Failed to get monitor clock: %ld\n", + PTR_ERR(pcie->core_clk_m)); + return PTR_ERR(pcie->core_clk_m); + } + pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "appl"); if (!pcie->appl_res) { @@ -2449,6 +2467,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) if (!pcie->link_state && !pcie->slot_pluggable) return 0; + clk_disable_unprepare(pcie->core_clk_m); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie);