From patchwork Sun Oct 16 15:01:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 13007838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0847C4167E for ; Sun, 16 Oct 2022 15:03:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229919AbiJPPDS (ORCPT ); Sun, 16 Oct 2022 11:03:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229905AbiJPPDP (ORCPT ); Sun, 16 Oct 2022 11:03:15 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 866A3419B9; Sun, 16 Oct 2022 08:03:11 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id d26so19844344eje.10; Sun, 16 Oct 2022 08:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6FJ7/YP2hXS1vCrLDjBwuedubr0y59mrPeF+JZZ90fI=; b=Oew1i3NVCMoZZdQLuEGDPYbnBZgkBemMYRY0r7R1w5Z/ERIcFek+s7X/04rra1pJDX 7LdhJxuTzW7INr9stEfrMMExZmWIre6R2pVnfciRy+uPNKIpsfBrFfQjDN5YWXyEVKWS XJXGN0deN0tfUH8WV1QCo8qbidvFnvnjjWYqctNJ/iXAvcn1rmPjG6MIMLTxSaHEr6Gs GdHh7pBhCvOrk3BQFlH4ZWvoKhkGrbuQnk2XxS6qD4wCEq3fEccchXOLsxnR8y541N+u 0up5oEEoBMUFW1mmJv5rhMsxEfPRJh2IwKvQaBXsPlPlG5HIjDxdqkupY/GMbkDXEpNw sa8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6FJ7/YP2hXS1vCrLDjBwuedubr0y59mrPeF+JZZ90fI=; b=NaUTHKGtlGBrn+qJyBDAWdynLP3eKbvGYi4o++KX3yZgeKhuRW9/xzXdbYTnhrEXAG 5NnmUQ3eDlneUjm2F28c+J/yB67C67lZaVQoMYrcvFFkcwSdZDpvGd59i8Kv6/P+4oNR 44c0RIM8iGTdYICpjY26ZsvSXYCp71VbMCBVJeMLUsgiZFYz4OAXDjPtV8qssDmUPIxX Cg5Mjl6phJpOV76ujApAz0lliCEOxp8DYjcQPYETtlSlP/cSp6xxjKXeuT52rm2pYGhP iwReQptW8OCyPf8iMSEOo9od/u8yt00oO4K2NCz2hjPfIzW8Qf1H1fe+xIWQSb5jREGE gJXg== X-Gm-Message-State: ACrzQf3tf1C/eKa1rw/j/SGJ6sBGST0rL93eyeOCsPbflBH4yRovaYcG +iky9q05lN0qeyV/AGPlIbw= X-Google-Smtp-Source: AMsMyM4sA5Z6mE6yrCb0Y2Mfw0pJdyAkAD+acsbSybrO901BKkvarjRt9ycDR25jrs4FSidj7mR9nw== X-Received: by 2002:a17:907:a054:b0:78d:7822:3108 with SMTP id gz20-20020a170907a05400b0078d78223108mr5322987ejc.764.1665932589479; Sun, 16 Oct 2022 08:03:09 -0700 (PDT) Received: from hp-power-15.localdomain (mm-39-7-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.7.39]) by smtp.gmail.com with ESMTPSA id u8-20020a17090657c800b0078c1e174e11sm4645699ejr.136.2022.10.16.08.03.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 08:03:09 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Thomas Bogendoerfer , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 1/4] MIPS: ingenic: add new machine type MACH_JZ4755 Date: Sun, 16 Oct 2022 18:01:06 +0300 Message-Id: <20221016150110.3020451-2-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221016150110.3020451-1-lis8215@gmail.com> References: <20221016150110.3020451-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org which is close to jz4725b because it is actually a low price successor of the jz4755. It has the same MIPS32r1 core with Xburst(R) extension MXU version 1 release 2. Signed-off-by: Siarhei Volkau --- arch/mips/ingenic/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/mips/ingenic/Kconfig b/arch/mips/ingenic/Kconfig index f595b339a..edd84cf13 100644 --- a/arch/mips/ingenic/Kconfig +++ b/arch/mips/ingenic/Kconfig @@ -4,6 +4,7 @@ config MACH_INGENIC_GENERIC bool select MACH_INGENIC select MACH_JZ4740 + select MACH_JZ4755 select MACH_JZ4725B select MACH_JZ4770 select MACH_JZ4780 @@ -53,6 +54,10 @@ config MACH_JZ4740 bool select SYS_HAS_CPU_MIPS32_R1 +config MACH_JZ4755 + bool + select SYS_HAS_CPU_MIPS32_R1 + config MACH_JZ4770 bool select MIPS_CPU_SCACHE From patchwork Sun Oct 16 15:01:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 13007837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E283C4332F for ; Sun, 16 Oct 2022 15:03:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229912AbiJPPDS (ORCPT ); Sun, 16 Oct 2022 11:03:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229894AbiJPPDQ (ORCPT ); Sun, 16 Oct 2022 11:03:16 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 128F0419A9; Sun, 16 Oct 2022 08:03:13 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id r17so19857541eja.7; Sun, 16 Oct 2022 08:03:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uB/YFZqZEaKiFGlCwO3LrxhNU5OpxJ4tB5tamj6ARsY=; b=XlKCTvyx4mNCaRV0wCHPRlfvy0I+BXCYT7azBCeF1sjnw72XKi6j32c/FaKi5J5q0D 5tPuneU5aI7Yhh1safVmV8+1rJnpK1bp9LMeOJUUJqmFQ7PkAm85ZiJu/Onr1+KrFaqu XJX0OBVFjcaZKkLDZSNHJOgvCgxTIz0iY7DMYxL1Pkp7QsnDqAoQNcDN8bSg996ji69K 8UvQFVeTsJ737UybdDWWdEIdssl9QONCYD7IHboHds4msZsRl6xI5L9eBuo9EBadHzWR uXuRDS+v5FpUXhnMwkd6jtHSPUZlL/i88kceSeVkKfF+Znl1gPBhlqKtPx2HKWhZPgt1 uc/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uB/YFZqZEaKiFGlCwO3LrxhNU5OpxJ4tB5tamj6ARsY=; b=l0XfskRyr7xBpyV+Q0xQ6KzWULvyj118xumXsr+Lv9dpqMymTLZGxdamUz2GOkzc/G QQfaD5Ge88ccN/dHnES/ITCVW1bJpSYplekuU9npKbfuNgAcpm9Z3rICylSmn9J+dmFv w7JWXr6M2IJHfJkP3cNf/iINZ8JvYzExrewtIO+KL5iv/cUuKcWqoN8h/yu65+m/e0im BKPiOPm6anumtYu6MHiqAhYUv3Gl3vPhEF7Yt62+chApPQtfjgamBPTNoVivHYU3DNzZ 25u52O0RN09GscGh8LFJNOK0Bom4Ha0GVBeGkP32iBO8l3xSHRp8wTASaF1x923yNdYu ajjg== X-Gm-Message-State: ACrzQf31rzJCvuh6N2AZl+YHmzH7C6Dt/kOU4mvj7hFWPdaTxgJ5y6Cn HqjETaQTae15FHSbi1IfmAY= X-Google-Smtp-Source: AMsMyM4R+IqmSByLB30ywIJPoa+9dZ2Txso0yYn1CA19X9qnOcMICH79ap/yXmbggu36r9q6XvwDNA== X-Received: by 2002:a17:907:3da5:b0:78e:793:4084 with SMTP id he37-20020a1709073da500b0078e07934084mr5563503ejc.285.1665932591555; Sun, 16 Oct 2022 08:03:11 -0700 (PDT) Received: from hp-power-15.localdomain (mm-39-7-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.7.39]) by smtp.gmail.com with ESMTPSA id u8-20020a17090657c800b0078c1e174e11sm4645699ejr.136.2022.10.16.08.03.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 08:03:11 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Thomas Bogendoerfer , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 2/4] dt-bindings: ingenic: Add support for the JZ4755 CGU Date: Sun, 16 Oct 2022 18:01:07 +0300 Message-Id: <20221016150110.3020451-3-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221016150110.3020451-1-lis8215@gmail.com> References: <20221016150110.3020451-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Acked-by: Krzysztof Kozlowski Signed-off-by: Siarhei Volkau --- Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml index aa1df03ef..df256ebcd 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml @@ -22,6 +22,7 @@ select: enum: - ingenic,jz4740-cgu - ingenic,jz4725b-cgu + - ingenic,jz4755-cgu - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu @@ -51,6 +52,7 @@ properties: - enum: - ingenic,jz4740-cgu - ingenic,jz4725b-cgu + - ingenic,jz4755-cgu - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu From patchwork Sun Oct 16 15:01:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 13007839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B20FCC433FE for ; Sun, 16 Oct 2022 15:03:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229926AbiJPPDT (ORCPT ); Sun, 16 Oct 2022 11:03:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229908AbiJPPDS (ORCPT ); Sun, 16 Oct 2022 11:03:18 -0400 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B9A240E17; Sun, 16 Oct 2022 08:03:15 -0700 (PDT) Received: by mail-ed1-x531.google.com with SMTP id a13so12893688edj.0; Sun, 16 Oct 2022 08:03:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B9Wg20rVnZ4v1joif76gIBjpt9SJeqrGz8H44eRdP3w=; b=A50Ffwth+rxwdeutEc8TDJvPwet06ye0MWIH/xcNVzsp5XM4majii9YrtKd5oiGkAF EoUP+3h0gDD3IAoB8OFtAyok0J/2UlMUF2idahWkAa9r2tVg+Eb7noyiSrAOeTRDtDe2 QpErXUwTsy4zEFb64wQyRp1pjjVcIufnwZ7CMlYPKQABAYtLMjcOZMzopFw0/y0cGPti F2NLNyboq5gnup6y7VK1zWPcH1DstXaMevdg/RMabnGCkMtvU+SKO+l1vyEGsv0v0mHv diVoWKA3ZDpyg1tcv1I6ORVal8CWAnnsUM80VXq9zAos/86dZmiAoB0fb2s3WK491uZU Mv1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B9Wg20rVnZ4v1joif76gIBjpt9SJeqrGz8H44eRdP3w=; b=UTvC7RIsjpimmdUcyNbjbS6QNowzT00KD/nQSDAbOdsz6TlnAYqysrJ7XF+zSuD4BP iOLLd4VK7O2D+3SFLPLBytPDWet5wfErcQr7ZLsH+2AFqvp3VnSFtdTUUckffr3Ey7zI SE80evcuWbCvTgnDlOidKabsxyY9we8Gh/W6ib3+2EFC2yCto1HWZUEpsGwPrVzThMvV ONWesIUswU5lH7EXniZuhk+nlMYgG5R0s/EZaWgG556CBaQsKQGFU5qtq49roJB4jxZr LnwyMdFPKmKX5zCbvfJ2oQxNW23XuSVbfsbatVT0yKXRAOYe3j4PJ0mcnk+8cPz6TDxP h80g== X-Gm-Message-State: ACrzQf2Bp1X10T+leVDOGGaSUi2BRBn3vnMMJjRrSiUlN+4HdRkQihxn EyCWXnQDtj1d0474tyFPdk8= X-Google-Smtp-Source: AMsMyM6HOhUcf00Igkv0lWYtgsZdw9ZCMSqcer8E0tPJm4/gRRmRWlET+DRSDTRn/FDg2WZ3jNlFiw== X-Received: by 2002:aa7:c78d:0:b0:454:fe1d:8eb1 with SMTP id n13-20020aa7c78d000000b00454fe1d8eb1mr6415212eds.59.1665932593668; Sun, 16 Oct 2022 08:03:13 -0700 (PDT) Received: from hp-power-15.localdomain (mm-39-7-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.7.39]) by smtp.gmail.com with ESMTPSA id u8-20020a17090657c800b0078c1e174e11sm4645699ejr.136.2022.10.16.08.03.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 08:03:13 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Thomas Bogendoerfer , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 3/4] dt-bindings: clock: Add Ingenic JZ4755 CGU header Date: Sun, 16 Oct 2022 18:01:08 +0300 Message-Id: <20221016150110.3020451-4-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221016150110.3020451-1-lis8215@gmail.com> References: <20221016150110.3020451-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This will be used from the devicetree bindings to specify the clocks that should be obtained from the jz4755-cgu driver. Signed-off-by: Siarhei Volkau --- .../dt-bindings/clock/ingenic,jz4755-cgu.h | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 include/dt-bindings/clock/ingenic,jz4755-cgu.h diff --git a/include/dt-bindings/clock/ingenic,jz4755-cgu.h b/include/dt-bindings/clock/ingenic,jz4755-cgu.h new file mode 100644 index 000000000..1ac13d61b --- /dev/null +++ b/include/dt-bindings/clock/ingenic,jz4755-cgu.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +/* + * This header provides clock numbers for the ingenic,jz4755-cgu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ + +#define JZ4755_CLK_EXT 0 +#define JZ4755_CLK_OSC32K 1 +#define JZ4755_CLK_PLL 2 +#define JZ4755_CLK_PLL_HALF 3 +#define JZ4755_CLK_EXT_HALF 4 +#define JZ4755_CLK_CCLK 5 +#define JZ4755_CLK_H0CLK 6 +#define JZ4755_CLK_PCLK 7 +#define JZ4755_CLK_MCLK 8 +#define JZ4755_CLK_H1CLK 9 +#define JZ4755_CLK_UDC 10 +#define JZ4755_CLK_LCD 11 +#define JZ4755_CLK_UART0 12 +#define JZ4755_CLK_UART1 13 +#define JZ4755_CLK_UART2 14 +#define JZ4755_CLK_DMA 15 +#define JZ4755_CLK_MMC 16 +#define JZ4755_CLK_MMC0 17 +#define JZ4755_CLK_MMC1 18 +#define JZ4755_CLK_EXT512 19 +#define JZ4755_CLK_RTC 20 +#define JZ4755_CLK_UDC_PHY 21 +#define JZ4755_CLK_I2S 22 +#define JZ4755_CLK_SPI 23 +#define JZ4755_CLK_AIC 24 +#define JZ4755_CLK_ADC 25 +#define JZ4755_CLK_TCU 26 +#define JZ4755_CLK_BCH 27 +#define JZ4755_CLK_I2C 28 +#define JZ4755_CLK_TVE 29 +#define JZ4755_CLK_CIM 30 +#define JZ4755_CLK_AUX_CPU 31 +#define JZ4755_CLK_AHB1 32 +#define JZ4755_CLK_IDCT 33 +#define JZ4755_CLK_DB 34 +#define JZ4755_CLK_ME 35 +#define JZ4755_CLK_MC 36 +#define JZ4755_CLK_TSSI 37 +#define JZ4755_CLK_IPU 38 + +#endif /* __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ */ From patchwork Sun Oct 16 15:01:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 13007840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F17D7C43219 for ; Sun, 16 Oct 2022 15:03:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229981AbiJPPDb (ORCPT ); Sun, 16 Oct 2022 11:03:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36508 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229948AbiJPPD0 (ORCPT ); Sun, 16 Oct 2022 11:03:26 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9599C41993; Sun, 16 Oct 2022 08:03:17 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id m15so12785333edb.13; Sun, 16 Oct 2022 08:03:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oicZhaFyYQwyfEJAZw8xjpjgeEJyH48EiK4Wz1kX8mo=; b=gE5zkGQCXBMLIitfa424vPCkVcC/e6nBLnolVrHfT04HN1dc46usB/vZ5lI6lnjtCS erFHKZiLRN32XlGHnCd3VJsMhwngb4WSHwslamTYfK8XA5WGUMEoIyo4X1XbB0zCfG2Z Zh1Xr622F8BToMQv+DLkXVktsQY9w2NLBQWevQNkB/BdUMxTOiek9S5i3BX9WPVt7pAB XFeNLNZfqzgG2D/uHqR182kpe5fRBuGVe4J1mas149L0QpAvY61TMplxL8yzgqE9G6PZ ZNlfgDrrpEevNRgVnm+oITCW90rqLREihyIoxxMfoj4w8CkxmmpWyYJwc9AoCjgnSyPX XaeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oicZhaFyYQwyfEJAZw8xjpjgeEJyH48EiK4Wz1kX8mo=; b=5EZTNfq7ZXQSAA/QkpsMCM6nw4u7zvA5cdfRdu8zv9i9FVTtPWHV1pX9ZxhlavQMyy Igfv5CF/EpXn5aEeQ/iWa7+CrMqMVAGDqgzTQBe8ooee3hs+Wq3/MGNvLP6TAsBxhdDM JB2KgtcLjFWei7caeCwghtvd0uZ7LU9OxSAxp31kxdV19UDmG4vicSlVS+7ajvrOpd/O 1SWKiG8sNBYBSrW6VYAer9OeDMqMvsCaTfG/v5QjaC+DF5HW5tHSf//RbXrKcHqxfT2k fka1ZecsLLzQytMl3nswz359TVkQoROH/jSs4YgCJ7/jmuS5AJFJEBWdYGVuXWu3rEoZ l2bA== X-Gm-Message-State: ACrzQf3Fn4hxs6Ce6fzytFpbR99DELKQQoyXx1abMnqqO7TLl2ChfExY K5BMmcqnUIzSzOljL2TA5Sc= X-Google-Smtp-Source: AMsMyM7kMNUzB0vOdNwtSUDlAfBgGPuO63eGi9zL6FNYH/oJdIUOKoNPGsUk+Yyz6rCLuPbqHgUaow== X-Received: by 2002:aa7:c0cf:0:b0:45c:6a06:ea9a with SMTP id j15-20020aa7c0cf000000b0045c6a06ea9amr6399924edp.211.1665932595816; Sun, 16 Oct 2022 08:03:15 -0700 (PDT) Received: from hp-power-15.localdomain (mm-39-7-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.7.39]) by smtp.gmail.com with ESMTPSA id u8-20020a17090657c800b0078c1e174e11sm4645699ejr.136.2022.10.16.08.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Oct 2022 08:03:15 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , Thomas Bogendoerfer , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 4/4] clk: Add Ingenic JZ4755 CGU driver Date: Sun, 16 Oct 2022 18:01:09 +0300 Message-Id: <20221016150110.3020451-5-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221016150110.3020451-1-lis8215@gmail.com> References: <20221016150110.3020451-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add support for the clocks provided by the CGU in the Ingenic JZ4755 SoC. Signed-off-by: Siarhei Volkau --- drivers/clk/ingenic/Kconfig | 10 + drivers/clk/ingenic/Makefile | 1 + drivers/clk/ingenic/jz4755-cgu.c | 350 +++++++++++++++++++++++++++++++ 3 files changed, 361 insertions(+) create mode 100644 drivers/clk/ingenic/jz4755-cgu.c diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig index 898f1bc47..f80ac4f29 100644 --- a/drivers/clk/ingenic/Kconfig +++ b/drivers/clk/ingenic/Kconfig @@ -15,6 +15,16 @@ config INGENIC_CGU_JZ4740 If building for a JZ4740 SoC, you want to say Y here. +config INGENIC_CGU_JZ4755 + bool "Ingenic JZ4755 CGU driver" + default MACH_JZ4755 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic JZ4755 + and compatible SoCs. + + If building for a JZ4755 SoC, you want to say Y here. + config INGENIC_CGU_JZ4725B bool "Ingenic JZ4725B CGU driver" default MACH_JZ4725B diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index 9edfaf461..81d8e23c2 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o +obj-$(CONFIG_INGENIC_CGU_JZ4755) += jz4755-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o diff --git a/drivers/clk/ingenic/jz4755-cgu.c b/drivers/clk/ingenic/jz4755-cgu.c new file mode 100644 index 000000000..16728546a --- /dev/null +++ b/drivers/clk/ingenic/jz4755-cgu.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Ingenic JZ4755 SoC CGU driver + * Heavily based on JZ4725b CGU driver + * + * Copyright (C) 2022 Siarhei Volkau + * Author: Siarhei Volkau + */ + +#include +#include +#include + +#include + +#include "cgu.h" +#include "pm.h" + +/* CGU register offsets */ +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_LCR 0x04 +#define CGU_REG_CPPCR 0x10 +#define CGU_REG_CLKGR 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSCCDR 0x68 +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x7C + +/* bits within the LCR register */ +#define LCR_SLEEP BIT(0) + +static struct ingenic_cgu *cgu; + +static const s8 pll_od_encoding[4] = { + 0x0, 0x1, -1, 0x3, +}; + +static const u8 jz4755_cgu_cpccr_div_table[] = { + 1, 2, 3, 4, 6, 8, +}; + +static const u8 jz4755_cgu_pll_half_div_table[] = { + 2, 1, +}; + +static const struct ingenic_cgu_clk_info jz4755_cgu_clocks[] = { + + /* External clocks */ + + [JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT }, + [JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, + + [JZ4755_CLK_PLL] = { + "pll", CGU_CLK_PLL, + .parents = { JZ4755_CLK_EXT, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_CPPCR, + .rate_multiplier = 1, + .m_shift = 23, + .m_bits = 9, + .m_offset = 2, + .n_shift = 18, + .n_bits = 5, + .n_offset = 2, + .od_shift = 16, + .od_bits = 2, + .od_max = 4, + .od_encoding = pll_od_encoding, + .stable_bit = 10, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 9, + .enable_bit = 8, + }, + }, + + /* Muxes & dividers */ + + [JZ4755_CLK_PLL_HALF] = { + "pll half", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, + jz4755_cgu_pll_half_div_table, + }, + }, + + [JZ4755_CLK_EXT_HALF] = { + "ext half", CGU_CLK_DIV, + .parents = { JZ4755_CLK_EXT, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0, + NULL, + }, + }, + + [JZ4755_CLK_CCLK] = { + "cclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_H0CLK] = { + "hclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_PCLK] = { + "pclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_MCLK] = { + "mclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_H1CLK] = { + "h1clk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_UDC] = { + "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 }, + .mux = { CGU_REG_CPCCR, 29, 1 }, + .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 10 }, + }, + + [JZ4755_CLK_LCD] = { + "lcd", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 9 }, + }, + + [JZ4755_CLK_MMC] = { + "mmc", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, + }, + + [JZ4755_CLK_I2S] = { + "i2s", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 }, + .mux = { CGU_REG_CPCCR, 31, 1 }, + .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, + }, + + [JZ4755_CLK_SPI] = { + "spi", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 4 }, + }, + + [JZ4755_CLK_TVE] = { + "tve", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { JZ4755_CLK_LCD, JZ4755_CLK_EXT, -1, -1 }, + .mux = { CGU_REG_LPCDR, 31, 1 }, + .gate = { CGU_REG_CLKGR, 18 }, + }, + + [JZ4755_CLK_RTC] = { + "rtc", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT512, JZ4755_CLK_OSC32K, -1, -1 }, + .mux = { CGU_REG_OPCR, 2, 1}, + .gate = { CGU_REG_CLKGR, 2 }, + }, + + [JZ4755_CLK_CIM] = { + "cim", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 8 }, + }, + + /* Gate-only clocks */ + + [JZ4755_CLK_UART0] = { + "uart0", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 0 }, + }, + + [JZ4755_CLK_UART1] = { + "uart1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 14 }, + }, + + [JZ4755_CLK_UART2] = { + "uart2", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 15 }, + }, + + [JZ4755_CLK_ADC] = { + "adc", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 7 }, + }, + + [JZ4755_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { JZ4755_CLK_I2S, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 5 }, + }, + + [JZ4755_CLK_I2C] = { + "i2c", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 3 }, + }, + + [JZ4755_CLK_BCH] = { + "bch", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MCLK/* not sure */, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + + [JZ4755_CLK_TCU] = { + "tcu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 1 }, + }, + + [JZ4755_CLK_DMA] = { + "dma", CGU_CLK_GATE, + .parents = { JZ4755_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 12 }, + }, + + [JZ4755_CLK_MMC0] = { + "mmc0", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MMC, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 6 }, + }, + + [JZ4755_CLK_MMC1] = { + "mmc1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MMC, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 16 }, + }, + + [JZ4755_CLK_AUX_CPU] = { + "aux_cpu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 24 }, + }, + + [JZ4755_CLK_AHB1] = { + "ahb1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 23 }, + }, + + [JZ4755_CLK_IDCT] = { + "idct", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 22 }, + }, + + [JZ4755_CLK_DB] = { + "db", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 21 }, + }, + + [JZ4755_CLK_ME] = { + "me", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 20 }, + }, + + [JZ4755_CLK_MC] = { + "mc", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 19 }, + }, + + [JZ4755_CLK_TSSI] = { + "tssi", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF/* not sure */, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 17 }, + }, + + [JZ4755_CLK_IPU] = { + "ipu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF/* not sure */, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 13 }, + }, + + [JZ4755_CLK_EXT512] = { + "ext/512", CGU_CLK_FIXDIV, + .parents = { JZ4755_CLK_EXT }, + + /* JZ4725b doc calls it EXT512, but it seems to be /256... + * Not sure if it applied to JZ4755 too, and which actual + * source is used EXT or EXT_HALF + */ + .fixdiv = { 256 }, + }, + + [JZ4755_CLK_UDC_PHY] = { + "udc_phy", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_OPCR, 6, true }, + }, +}; + +static void __init jz4755_cgu_init(struct device_node *np) +{ + int retval; + + cgu = ingenic_cgu_new(jz4755_cgu_clocks, + ARRAY_SIZE(jz4755_cgu_clocks), np); + if (!cgu) { + pr_err("%s: failed to initialise CGU\n", __func__); + return; + } + + retval = ingenic_cgu_register_clocks(cgu); + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + + ingenic_cgu_register_syscore_ops(cgu); +} +CLK_OF_DECLARE_DRIVER(jz4755_cgu, "ingenic,jz4755-cgu", jz4755_cgu_init);