From patchwork Mon Oct 17 09:12:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13008394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BA98C433FE for ; Mon, 17 Oct 2022 09:12:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 52AA5C433D6; Mon, 17 Oct 2022 09:12:22 +0000 (UTC) Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 44CFEC433C1; Mon, 17 Oct 2022 09:12:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 44CFEC433C1 Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wr1-f48.google.com with SMTP id n12so17430049wrp.10; Mon, 17 Oct 2022 02:12:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=frrJLARgUrWWi3Mt9s7uQpe32ppn7iBrKVIR2j/gFNs=; b=ptoyp83/MlG5dWk/gljcHoXiSSxEyetuV6RHLIMYKr79Be/OdGjDqgeaTWHEd1goIs vj86iQ+jA1pwf5a9DUYEvXIQLl7Iqyge1zFBb3YxZrb/NhIWztccPI03gGlAnx715nMX RXn7P1Odm+kXxPzC6FdCfTBJuyAeYq6sEHRLi2tlalcc/p7nvHz+ts5b9QpfU/tKNbUY tvlHIKCEyTCMCNQS6yr4xqB37TUVdL0QMzlBcr1n4X927oPGAhHYb8urD42bSFoVgvBf bibUAMU6Ju7tJcf9UNTLjrq2ZVt0RpEbEVRND1HjSmyJcbY61GFotdWjo1CJ3dwBtxsA iVMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=frrJLARgUrWWi3Mt9s7uQpe32ppn7iBrKVIR2j/gFNs=; b=i1/M2gk7Xl7WWayhkcwt1xP3SoWeLi4ngPpFMuiEFIJcwNY0xQBhBZtqS1fv1BVcNc 7pecTl3CBIL0OmhYpsso5nksH1pGe7KnDGEnYo96Elngcg4Vz18PwJn3Ekqvg9Yn8kbn 8Lj0L4EYg5kdxzP5N9u3bDsXYFIy+eZLBdp+NOSRDLxrT4EjzshBYh/3NH8AbhFzuTY1 cdIK6h7Nijd+enJMimRy18NYDyu1NKQRKFNeaZfJt4II/lchHg9m1JbRN4V9CZQm8dl4 /B0SEoPcYOY2LuSUZZDr10IVn0epnCdgWGDM8bzaj78AfHGQwJpSRwCxE9EbT894nh63 NjsA== X-Gm-Message-State: ACrzQf1n66l+JEygey3bwZKumNlBKrwexdUw3KLg36T03lso7WlIF7Nu FfwFDZW8T3NV7rknvO13r70= X-Google-Smtp-Source: AMsMyM73lus2yIYE8w3Wt2vJDumJGO4qcKWNPO9+djjQnnsEvWHKQwH86YvNiT9hQckEa7PBV2/Lzw== X-Received: by 2002:adf:e608:0:b0:22e:42ff:2fe with SMTP id p8-20020adfe608000000b0022e42ff02femr5454369wrm.161.1665997938363; Mon, 17 Oct 2022 02:12:18 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:fc4d:6548:d8bd:5bd]) by smtp.gmail.com with ESMTPSA id n14-20020a5d400e000000b0022ae401e9e0sm7921503wrp.78.2022.10.17.02.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Oct 2022 02:12:17 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar List-Id: To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Cc: Conor Dooley , Samuel Holland , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [RFC RESEND PATCH 1/2] arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property Date: Mon, 17 Oct 2022 10:12:00 +0100 Message-Id: <20221017091201.199457-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221017091201.199457-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221017091201.199457-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 From: Lad Prabhakar Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property so that we can share the common parts of the SoC DTSI with the RZ/Five (RISC-V) SoC and the RZ/G2UL (ARM64) SoC. This patch adds a new file r9a07g043u.dtsi to separate out RZ/G2UL (ARM64) SoC specific parts. No functional changes (same DTB). Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 301 +++++++++--------- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 12 + .../boot/dts/renesas/r9a07g043u11-smarc.dts | 2 +- 3 files changed, 163 insertions(+), 152 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index c1fb29de2fa4..c41840e32c30 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -5,7 +5,6 @@ * Copyright (C) 2022 Renesas Electronics Corp. */ -#include #include / { @@ -107,10 +106,10 @@ ssi0: ssi@10049c00 { compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x10049c00 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, @@ -128,10 +127,10 @@ ssi1: ssi@1004a000 { compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x1004a000 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, @@ -149,10 +148,10 @@ ssi2: ssi@1004a400 { compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x1004a400 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, @@ -170,10 +169,10 @@ ssi3: ssi@1004a800 { compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x1004a800 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, @@ -190,9 +189,9 @@ ssi3: ssi@1004a800 { spi0: spi@1004ac00 { compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; reg = <0 0x1004ac00 0 0x400>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; resets = <&cpg R9A07G043_RSPI0_RST>; @@ -208,9 +207,9 @@ spi0: spi@1004ac00 { spi1: spi@1004b000 { compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; reg = <0 0x1004b000 0 0x400>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; resets = <&cpg R9A07G043_RSPI1_RST>; @@ -226,9 +225,9 @@ spi1: spi@1004b000 { spi2: spi@1004b400 { compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; reg = <0 0x1004b400 0 0x400>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; resets = <&cpg R9A07G043_RSPI2_RST>; @@ -245,12 +244,12 @@ scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + , + , + ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; @@ -264,12 +263,12 @@ scif1: serial@1004bc00 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004bc00 0 0x400>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + , + , + ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; @@ -283,12 +282,12 @@ scif2: serial@1004c000 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004c000 0 0x400>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + , + , + ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; @@ -302,12 +301,12 @@ scif3: serial@1004c400 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004c400 0 0x400>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + , + , + ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; @@ -321,12 +320,12 @@ scif4: serial@1004c800 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004c800 0 0x400>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + , + , + ; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; @@ -339,10 +338,10 @@ scif4: serial@1004c800 { sci0: serial@1004d000 { compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d000 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; clock-names = "fck"; @@ -354,10 +353,10 @@ sci0: serial@1004d000 { sci1: serial@1004d400 { compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d400 0 0x400>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; clock-names = "fck"; @@ -369,14 +368,14 @@ sci1: serial@1004d400 { canfd: can@10050000 { compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "g_err", "g_recc", "ch0_err", "ch0_rec", "ch0_trx", "ch1_err", "ch1_rec", "ch1_trx"; @@ -405,14 +404,14 @@ i2c0: i2c@10058000 { #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058000 0 0x400>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; @@ -427,14 +426,14 @@ i2c1: i2c@10058400 { #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058400 0 0x400>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; @@ -449,14 +448,14 @@ i2c2: i2c@10058800 { #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058800 0 0x400>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; @@ -471,14 +470,14 @@ i2c3: i2c@10058c00 { #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058c00 0 0x400>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; @@ -491,7 +490,7 @@ i2c3: i2c@10058c00 { adc: adc@10059000 { compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc"; reg = <0 0x10059000 0 0x400>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>, <&cpg CPG_MOD R9A07G043_ADC_PCLK>; clock-names = "adclk", "pclk"; @@ -551,10 +550,10 @@ cpg: clock-controller@11010000 { sysc: system-controller@11020000 { compatible = "renesas,r9a07g043-sysc"; reg = <0 0x11020000 0 0x10000>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; status = "disabled"; @@ -578,23 +577,23 @@ dmac: dma-controller@11820000 { "renesas,rz-dmac"; reg = <0 0x11820000 0 0x10000>, <0 0x11830000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", @@ -623,8 +622,8 @@ sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g043", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; - interrupts = , - ; + interrupts = , + ; clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, @@ -639,8 +638,8 @@ sdhi1: mmc@11c10000 { compatible = "renesas,sdhi-r9a07g043", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; - interrupts = , - ; + interrupts = , + ; clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, @@ -655,9 +654,9 @@ eth0: ethernet@11c20000 { compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; reg = <0 0x11c20000 0 0x10000>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "mux", "fil", "arp_ns"; phy-mode = "rgmii"; clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, @@ -675,9 +674,9 @@ eth1: ethernet@11c30000 { compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; reg = <0 0x11c30000 0 0x10000>; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "mux", "fil", "arp_ns"; phy-mode = "rgmii"; clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, @@ -705,7 +704,7 @@ phyrst: usbphy-ctrl@11c40000 { ohci0: usb@11c50000 { compatible = "generic-ohci"; reg = <0 0x11c50000 0 0x100>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; resets = <&phyrst 0>, @@ -719,7 +718,7 @@ ohci0: usb@11c50000 { ohci1: usb@11c70000 { compatible = "generic-ohci"; reg = <0 0x11c70000 0 0x100>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; resets = <&phyrst 1>, @@ -733,7 +732,7 @@ ohci1: usb@11c70000 { ehci0: usb@11c50100 { compatible = "generic-ehci"; reg = <0 0x11c50100 0 0x100>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; resets = <&phyrst 0>, @@ -748,7 +747,7 @@ ehci0: usb@11c50100 { ehci1: usb@11c70100 { compatible = "generic-ehci"; reg = <0 0x11c70100 0 0x100>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; resets = <&phyrst 1>, @@ -764,7 +763,7 @@ usb2_phy0: usb-phy@11c50200 { compatible = "renesas,usb2-phy-r9a07g043", "renesas,rzg2l-usb2-phy"; reg = <0 0x11c50200 0 0x700>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; resets = <&phyrst 0>; @@ -777,7 +776,7 @@ usb2_phy1: usb-phy@11c70200 { compatible = "renesas,usb2-phy-r9a07g043", "renesas,rzg2l-usb2-phy"; reg = <0 0x11c70200 0 0x700>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; resets = <&phyrst 1>; @@ -790,10 +789,10 @@ hsusb: usb@11c60000 { compatible = "renesas,usbhs-r9a07g043", "renesas,rza2-usbhs"; reg = <0 0x11c60000 0 0x10000>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; resets = <&phyrst 0>, @@ -812,8 +811,8 @@ wdt0: watchdog@12800800 { clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, <&cpg CPG_MOD R9A07G043_WDT0_CLK>; clock-names = "pclk", "oscclk"; - interrupts = , - ; + interrupts = , + ; interrupt-names = "wdt", "perrout"; resets = <&cpg R9A07G043_WDT0_PRESETN>; power-domains = <&cpg>; @@ -824,7 +823,7 @@ ostm0: timer@12801000 { compatible = "renesas,r9a07g043-ostm", "renesas,ostm"; reg = <0x0 0x12801000 0x0 0x400>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; resets = <&cpg R9A07G043_OSTM0_PRESETZ>; power-domains = <&cpg>; @@ -835,7 +834,7 @@ ostm1: timer@12801400 { compatible = "renesas,r9a07g043-ostm", "renesas,ostm"; reg = <0x0 0x12801400 0x0 0x400>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; resets = <&cpg R9A07G043_OSTM1_PRESETZ>; power-domains = <&cpg>; @@ -846,7 +845,7 @@ ostm2: timer@12801800 { compatible = "renesas,r9a07g043-ostm", "renesas,ostm"; reg = <0x0 0x12801800 0x0 0x400>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; resets = <&cpg R9A07G043_OSTM2_PRESETZ>; power-domains = <&cpg>; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi new file mode 100644 index 000000000000..be84392ee47f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include + +#define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI nr na + +#include "r9a07g043.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 059885a01ede..01483b4302c2 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -17,7 +17,7 @@ #define SW_SW0_DEV_SEL 1 #define SW_ET0_EN_N 1 -#include "r9a07g043.dtsi" +#include "r9a07g043u.dtsi" #include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc.dtsi" From patchwork Mon Oct 17 09:12:01 2022 Content-Type: text/plain; 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Mon, 17 Oct 2022 02:12:19 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar List-Id: To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Cc: Conor Dooley , Samuel Holland , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [RFC RESEND PATCH 2/2] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts Date: Mon, 17 Oct 2022 10:12:01 +0100 Message-Id: <20221017091201.199457-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221017091201.199457-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221017091201.199457-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 From: Lad Prabhakar Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that r9a07g043.dtsi can be shared with RZ/Five (RISC-V SoC). Below are the changes due to which SoC specific parts are moved to r9a07g043u.dtsi: - RZ/G2UL has Cortex-A55 (ARM64) whereas the RZ/Five has AX45MP (RISC-V) - RZ/G2UL has GICv3 as interrupt controller whereas the RZ/Five has PLIC - RZ/G2UL has interrupts for SYSC block whereas interrupts are missing for SYSC block on RZ/Five Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 54 +------------------ arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 60 +++++++++++++++++++++ 2 files changed, 61 insertions(+), 53 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index c41840e32c30..fd2b7d7e6d1a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2UL SoC + * Device Tree Source for the RZ/Five and RZ/G2UL SoCs * * Copyright (C) 2022 Renesas Electronics Corp. */ @@ -68,36 +68,8 @@ opp-1000000000 { }; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a55"; - reg = <0>; - device_type = "cpu"; - #cooling-cells = <2>; - next-level-cache = <&L3_CA55>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; - operating-points-v2 = <&cluster0_opp>; - }; - - L3_CA55: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-size = <0x40000>; - }; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -550,12 +522,6 @@ cpg: clock-controller@11010000 { sysc: system-controller@11020000 { compatible = "renesas,r9a07g043-sysc"; reg = <0 0x11020000 0 0x10000>; - interrupts = , - , - , - ; - interrupt-names = "lpm_int", "ca55stbydone_int", - "cm33stbyr_int", "ca55_deny"; status = "disabled"; }; @@ -608,16 +574,6 @@ dmac: dma-controller@11820000 { dma-channels = <16>; }; - gic: interrupt-controller@11900000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0x11900000 0 0x40000>, - <0x0 0x11940000 0 0x60000>; - interrupts = ; - }; - sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g043", "renesas,rcar-gen3-sdhi"; @@ -883,12 +839,4 @@ target: trip-point { }; }; }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index be84392ee47f..dcbeda9b6c23 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -10,3 +10,63 @@ #define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI nr na #include "r9a07g043.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + #cooling-cells = <2>; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + operating-points-v2 = <&cluster0_opp>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; + +&soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = ; + }; +}; + +&sysc { + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; +};