From patchwork Wed Oct 19 18:38:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Thaler X-Patchwork-Id: 13012278 X-Patchwork-Delegate: bpf@iogearbox.net Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D22C4C433FE for ; Wed, 19 Oct 2022 18:38:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230168AbiJSSiw (ORCPT ); Wed, 19 Oct 2022 14:38:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229680AbiJSSiv (ORCPT ); Wed, 19 Oct 2022 14:38:51 -0400 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAF1517D87F for ; Wed, 19 Oct 2022 11:38:50 -0700 (PDT) Received: by mail-pg1-x52a.google.com with SMTP id q1so17011111pgl.11 for ; Wed, 19 Oct 2022 11:38:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=s9xNB+9pkjsuEgXzNEYq8ChwptKRSqWxHSgvfEMrQ0s=; b=RZkENNSDBphbae7yFwQJUAEfHL4MQZtPZhxVSeHnCXf8cOa+O8p3sJHobXGG4pmnWK FWzVWx4ZFP+Tl5b7DUYFa76SbU7Lts7TTwuC7Y/NpNiDl1bJURKpU2Vh3I4so1BRH/Vv 4Ii2bo6O6mHAbh3SJGFa4t66Pde4dSHB6Tvk9sO0DyAo48Kq1iLHo7fJNyUF2EyYurcY aXuAq9UJR1XHqRzHvqHRWQI4Km97TnI9ulalzibruTbaTI7mdBG5T9vwVQI4mxuDO7sO P/a67ZXGJH1WjmaJ0ag3uBeo9spGKNhlmtPmkYIwwBEhATO42XtKEo+ufdIGt5ebqLr/ gu5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=s9xNB+9pkjsuEgXzNEYq8ChwptKRSqWxHSgvfEMrQ0s=; b=zjXWDxDZ/W6ZveYvdyJTISpV7F5eljpWQzhcHylbOKbRnGq9l/oB1Ug9bjtyPjnQ5R MKEAP3lKpuRsUuA0v0FAXqO5fsgMr0I2c40DRsC/ZTTt9SZlR1eNRil0tyQ1Sz72xo8c W1f+t4TnVGT1yHlzaYUQ9u0xvpkEyjf6wy1G0ub+pFifnTyT1WjE6DOfiS7B76v/MFKv DskFqQCsEWz2E9UllYDwmiOfl1RmK2mfAa5WKiZNFuVvBR4RCTIE1fcx4GJzfF73es34 bfKER32ZOQCzCi58oa0qsPcY1wDtVdkN2QB5Kw/PIcH5M5bCt+2YsTQNMFmE+iUldpoG KRhA== X-Gm-Message-State: ACrzQf2G2JIFjS+k+uo/JSAjl0o2P2MxjJkLpb4cLCYmUcGVxjRvVEjd K+qx3ccFV+U0aPCbKwRyABvK/MWibIF7SQ== X-Google-Smtp-Source: AMsMyM4FBUjNwC1kSVow/araIYsSfON5R3NnsXWGO0/P7G3RslCE4EHApcxHHClKlbO/wPaMuSPDtg== X-Received: by 2002:a63:1e47:0:b0:43c:261f:f773 with SMTP id p7-20020a631e47000000b0043c261ff773mr8444942pgm.1.1666204729976; Wed, 19 Oct 2022 11:38:49 -0700 (PDT) Received: from mariner-vm.. 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[67.185.99.176]) by smtp.gmail.com with ESMTPSA id x2-20020a170902a38200b00177ff4019d9sm11104510pla.274.2022.10.19.11.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 11:38:49 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 1/4] bpf, docs: Add note about type convention Date: Wed, 19 Oct 2022 18:38:42 +0000 Message-Id: <20221019183845.905-1-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Add note about type convention Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 4997d2088..6847a4cbf 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -7,6 +7,11 @@ eBPF Instruction Set Specification, v1.0 This document specifies version 1.0 of the eBPF instruction set. +Documentation conventions +========================= + +For brevity, this document uses the type notion "u64", "u32", etc. +to mean an unsigned integer whose width is the specified number of bits. Registers and calling convention ================================ @@ -116,6 +121,8 @@ BPF_END 0xd0 byte swap operations (see `Byte swap instructions`_ below) dst_reg = (u32) dst_reg + (u32) src_reg; +where '(u32)' indicates truncation to 32 bits. + ``BPF_ADD | BPF_X | BPF_ALU64`` means:: dst_reg = dst_reg + src_reg From patchwork Wed Oct 19 18:38:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Thaler X-Patchwork-Id: 13012279 X-Patchwork-Delegate: bpf@iogearbox.net Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E3FBC4332F for ; Wed, 19 Oct 2022 18:38:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229680AbiJSSix (ORCPT ); Wed, 19 Oct 2022 14:38:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230154AbiJSSiw (ORCPT ); Wed, 19 Oct 2022 14:38:52 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1674217D87F for ; Wed, 19 Oct 2022 11:38:52 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id fw14so17662474pjb.3 for ; Wed, 19 Oct 2022 11:38:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rCDmQ9xrAmjZGrgEFa9vY4JR2yCT6Jw9ahBiSCvLJ/g=; b=c8+eQ40FIkjNEj8ttqyXmUcelsZu7ov0f0IGlxfmrIxlo3FG0SE+a6jX1kP3dd2U7u 8U95OVG+txXYb2ZtBvewi/ukEiyNYbo4yID+wkvSuuGX2nxwu59wCaI/Y2C9sHtQaKS5 TwYO8hkGsxVPEX7UlkCPw6TDu+bwl1/ufC6uDq8Zz9HA1fmi2Eo/oQMdzPyI9fp17Gez YtnunUOof5uMvIPgx+IH06G5nlb0E8d9bD2vwZkr5VM4vyJsQyORe0yOmTxD7HvrpBJT r/7xz+WxxXZ4xHVWqWsotOHSQQlMxfuM4HmcwVaq6rz/74bmq3ToLn1oFcCq7iAOwRqJ tcYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rCDmQ9xrAmjZGrgEFa9vY4JR2yCT6Jw9ahBiSCvLJ/g=; b=cfxDAWE+83iltfRS3yE2zyev4fnhKXG/eJoCSl2Q9pQ/kSuiZgvTPWdvTWunl+GKQ6 gGqQokR9m63iSHWdJYwHsjkt/sKsOeuWz72hWsyXz3U7jrivWvywQy5Fx5mYnCdGWSCh 9vxY5BGJaQSVdwlk3jdHacvMLAYxkUqFG0QoZ89YY3Urtgr+rPVac3lUBFlw1+Gpqi3M NsWVL2oL6PiuRKAZOxq5QPdluL3Be+XLBMehqQ5JdwbWNyGy1SuAJeR91vxh26hLGCP7 G0YIdMQ9tN5ySwaHzm4Y4XCrV5rtfMF1Y5utl/0kPE8DtQSgQTJuEExU1XQL5HDCNW9F BuRg== X-Gm-Message-State: ACrzQf07oRrGEioVtc5HgO+3ROL0gdvB0WxFcqoggPG7GB9f0zViLT0M h6tWac8mQITe5KblO3Zr2udPGTBHKaIuOQ== X-Google-Smtp-Source: AMsMyM6+yFOsW5lsUTCDsJKLSuYkQLB0C4SGONr/bjWBT8Bk7mMw/r794zH3+i0bQtzxbM4OyDSwDQ== X-Received: by 2002:a17:902:8c81:b0:178:1701:cd with SMTP id t1-20020a1709028c8100b00178170100cdmr10018742plo.138.1666204731188; Wed, 19 Oct 2022 11:38:51 -0700 (PDT) Received: from mariner-vm.. (c-67-185-99-176.hsd1.wa.comcast.net. [67.185.99.176]) by smtp.gmail.com with ESMTPSA id x2-20020a170902a38200b00177ff4019d9sm11104510pla.274.2022.10.19.11.38.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 11:38:50 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 2/4] bpf, docs: Fix modulo zero, division by zero, overflow, and underflow Date: Wed, 19 Oct 2022 18:38:43 +0000 Message-Id: <20221019183845.905-2-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 In-Reply-To: <20221019183845.905-1-dthaler1968@googlemail.com> References: <20221019183845.905-1-dthaler1968@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Fix modulo zero, division by zero, overflow, and underflow. Also clarify how a negative immediate value is ued in unsigned division Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 6847a4cbf..3a64d4b49 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -104,19 +104,26 @@ code value description BPF_ADD 0x00 dst += src BPF_SUB 0x10 dst -= src BPF_MUL 0x20 dst \*= src -BPF_DIV 0x30 dst /= src +BPF_DIV 0x30 dst = (src != 0) ? (dst / src) : 0 BPF_OR 0x40 dst \|= src BPF_AND 0x50 dst &= src BPF_LSH 0x60 dst <<= src BPF_RSH 0x70 dst >>= src BPF_NEG 0x80 dst = ~src -BPF_MOD 0x90 dst %= src +BPF_MOD 0x90 dst = (src != 0) ? (dst % src) : dst BPF_XOR 0xa0 dst ^= src BPF_MOV 0xb0 dst = src BPF_ARSH 0xc0 sign extending shift right BPF_END 0xd0 byte swap operations (see `Byte swap instructions`_ below) ======== ===== ========================================================== +Underflow and overflow are allowed during arithmetic operations, +meaning the 64-bit or 32-bit value will wrap. If +eBPF program execution would result in division by zero, +the destination register is instead set to zero. +If execution would result in modulo by zero, +the destination register is instead left unchanged. + ``BPF_ADD | BPF_X | BPF_ALU`` means:: dst_reg = (u32) dst_reg + (u32) src_reg; @@ -135,6 +142,10 @@ where '(u32)' indicates truncation to 32 bits. src_reg = src_reg ^ imm32 +Also note that the division and modulo operations are unsigned, +where 'imm' is first sign extended to 64 bits and then converted +to an unsigned 64-bit value. There are no instructions for +signed division or modulo. Byte swap instructions ~~~~~~~~~~~~~~~~~~~~~~ From patchwork Wed Oct 19 18:38:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Thaler X-Patchwork-Id: 13012281 X-Patchwork-Delegate: bpf@iogearbox.net Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CD0DC4332F for ; Wed, 19 Oct 2022 18:39:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229785AbiJSSjT (ORCPT ); Wed, 19 Oct 2022 14:39:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230481AbiJSSjF (ORCPT ); Wed, 19 Oct 2022 14:39:05 -0400 Received: from mail-oi1-x22f.google.com (mail-oi1-x22f.google.com [IPv6:2607:f8b0:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B4A5F53D6 for ; Wed, 19 Oct 2022 11:39:04 -0700 (PDT) Received: by mail-oi1-x22f.google.com with SMTP id j188so20257181oih.4 for ; Wed, 19 Oct 2022 11:39:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jcX2mJ3fFojEo2hfaxGiaRqzWuPlP1L0U3++56+JvDo=; b=fkKoU6acZoLhkUKieitO4Xp3NkvXCRIzRHXf6SnErtV1DtoQ3MEmf4W06825oKrutR V4RZuXrPj3xO3GYx9mtCzDNFlbzqQVn6SUU2ASC6CRwWE9yuU826FGfceo+wwrQiBN4N 0ddwBs9IvBIb8pQ56Kzso6BL272QSQNAqVyhyjYKlTmix1jk7UOnqySDRWlEbsOeJ0ra MrAtKSghd4A7cMar95pp5qK5TPyMT84rFkPsrmqAyla3WJHjOuvxoc6ARKsEvc5bKFwI MZ/NY68+37+LdGI1cuhx4p5TJCR8bTnnjv4ptpA+58T8mrLgFxNv8cAJVbun+UQEXCwV /GBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jcX2mJ3fFojEo2hfaxGiaRqzWuPlP1L0U3++56+JvDo=; b=e6T6Jo27XG2G2noxRxfWTwF19J2PRlc0RewVpGyp/Gqfk7M0i/yE/geoFR9gLVfITo qmnvct9VJ2T0T7OrwNq1EN95W6IMIhus7ebYO32iY+FCFB8wKPQS+pWsY8p5cc6ReVtJ ykOoviNWeSXG3R35VF5ePAWBuVMgg3bj/xRxfW04fGsaGZ2Gb4apEdRnmz/mE16fQzKQ mRYXE0FfdqtdGAUr2hZWEZOMszFjUH5Is426wPD9sR427J12ZMGc2N48IO2p2KQrQCA1 1VkTZ60y2WV9J+vf0Zl3B3VgVt+YMAOeyo+WQUXiyPOSlVhlsJ/gMWuWHplNGgM5wsOO Qy2Q== X-Gm-Message-State: ACrzQf17I8t1GdXAYXLqwz3hKIMUUymcvWaQATbBI2r+XgMZFiF90KjX YR2XCtPJTEn7Nrj1YYdkXGDVGe3cT5l04g== X-Google-Smtp-Source: AMsMyM76wZA3DEwdp0S1YmFsxfMvWVFVs9rv3gNR1yj8kclCRha3CoaIk865R9Y4k/WIhG04cTrE/Q== X-Received: by 2002:a17:90b:4f8f:b0:20d:be54:f34f with SMTP id qe15-20020a17090b4f8f00b0020dbe54f34fmr33036230pjb.245.1666204732568; Wed, 19 Oct 2022 11:38:52 -0700 (PDT) Received: from mariner-vm.. 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[67.185.99.176]) by smtp.gmail.com with ESMTPSA id x2-20020a170902a38200b00177ff4019d9sm11104510pla.274.2022.10.19.11.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 11:38:52 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 3/4] bpf, docs: Use consistent names for the same field Date: Wed, 19 Oct 2022 18:38:44 +0000 Message-Id: <20221019183845.905-3-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 In-Reply-To: <20221019183845.905-1-dthaler1968@googlemail.com> References: <20221019183845.905-1-dthaler1968@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Use consistent names for the same field Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 107 ++++++++++++++++++-------- 1 file changed, 76 insertions(+), 31 deletions(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 3a64d4b49..29b599c70 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -35,20 +35,59 @@ Instruction encoding eBPF has two instruction encodings: * the basic instruction encoding, which uses 64 bits to encode an instruction -* the wide instruction encoding, which appends a second 64-bit immediate value - (imm64) after the basic instruction for a total of 128 bits. +* the wide instruction encoding, which appends a second 64-bit immediate (i.e., + constant) value after the basic instruction for a total of 128 bits. -The basic instruction encoding looks as follows: +The basic instruction encoding is as follows, where MSB and LSB mean the most significant +bits and least significant bits, respectively: ============= ======= =============== ==================== ============ 32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB) ============= ======= =============== ==================== ============ -immediate offset source register destination register opcode +imm offset src dst opcode ============= ======= =============== ==================== ============ +imm + signed integer immediate value + +offset + signed integer offset used with pointer arithmetic + +src + the source register number (0-10), except where otherwise specified + (`64-bit immediate instructions`_ reuse this field for other purposes) + +dst + destination register number (0-10) + +opcode + operation to perform + Note that most instructions do not use all of the fields. Unused fields shall be cleared to zero. +As discussed below in `64-bit immediate instructions`_, a 64-bit immediate +instruction uses a 64-bit immediate value that is constructed as follows. +The 64 bits following the basic instruction contain a pseudo instruction +using the same format but with opcode, dst, src, and offset all set to zero, +and imm containing the high 32 bits of the immediate value. + +================= ================== +64 bits (MSB) 64 bits (LSB) +================= ================== +basic instruction pseudo instruction +================= ================== + +Thus the 64-bit immediate value is constructed as follows: + + imm64 = imm + (next_imm << 32) + +where 'next_imm' refers to the imm value of the pseudo instruction +following the basic instruction. + +In the remainder of this document 'src' and 'dst' refer to the values of the source +and destination registers, respectively, rather than the register number. + Instruction classes ------------------- @@ -76,20 +115,24 @@ For arithmetic and jump instructions (``BPF_ALU``, ``BPF_ALU64``, ``BPF_JMP`` an ============== ====== ================= 4 bits (MSB) 1 bit 3 bits (LSB) ============== ====== ================= -operation code source instruction class +code source instruction class ============== ====== ================= -The 4th bit encodes the source operand: +code + the operation code, whose meaning varies by instruction class - ====== ===== ======================================== - source value description - ====== ===== ======================================== - BPF_K 0x00 use 32-bit immediate as source operand - BPF_X 0x08 use 'src_reg' register as source operand - ====== ===== ======================================== +source + the source operand location, which unless otherwise specified is one of: -The four MSB bits store the operation code. + ====== ===== ========================================== + source value description + ====== ===== ========================================== + BPF_K 0x00 use 32-bit 'imm' value as source operand + BPF_X 0x08 use 'src' register value as source operand + ====== ===== ========================================== +instruction class + the instruction class (see `Instruction classes`_) Arithmetic instructions ----------------------- @@ -117,6 +160,8 @@ BPF_ARSH 0xc0 sign extending shift right BPF_END 0xd0 byte swap operations (see `Byte swap instructions`_ below) ======== ===== ========================================================== +where 'src' is the source operand value. + Underflow and overflow are allowed during arithmetic operations, meaning the 64-bit or 32-bit value will wrap. If eBPF program execution would result in division by zero, @@ -126,21 +171,21 @@ the destination register is instead left unchanged. ``BPF_ADD | BPF_X | BPF_ALU`` means:: - dst_reg = (u32) dst_reg + (u32) src_reg; + dst = (u32) (dst + src) where '(u32)' indicates truncation to 32 bits. ``BPF_ADD | BPF_X | BPF_ALU64`` means:: - dst_reg = dst_reg + src_reg + dst = dst + src ``BPF_XOR | BPF_K | BPF_ALU`` means:: - src_reg = (u32) src_reg ^ (u32) imm32 + src = (u32) src ^ (u32) imm ``BPF_XOR | BPF_K | BPF_ALU64`` means:: - src_reg = src_reg ^ imm32 + src = src ^ imm Also note that the division and modulo operations are unsigned, where 'imm' is first sign extended to 64 bits and then converted @@ -173,11 +218,11 @@ Examples: ``BPF_ALU | BPF_TO_LE | BPF_END`` with imm = 16 means:: - dst_reg = htole16(dst_reg) + dst = htole16(dst) ``BPF_ALU | BPF_TO_BE | BPF_END`` with imm = 64 means:: - dst_reg = htobe64(dst_reg) + dst = htobe64(dst) Jump instructions ----------------- @@ -252,15 +297,15 @@ instructions that transfer data between a register and memory. ``BPF_MEM | | BPF_STX`` means:: - *(size *) (dst_reg + off) = src_reg + *(size *) (dst + offset) = src_reg ``BPF_MEM | | BPF_ST`` means:: - *(size *) (dst_reg + off) = imm32 + *(size *) (dst + offset) = imm32 ``BPF_MEM | | BPF_LDX`` means:: - dst_reg = *(size *) (src_reg + off) + dst = *(size *) (src + offset) Where size is one of: ``BPF_B``, ``BPF_H``, ``BPF_W``, or ``BPF_DW``. @@ -294,11 +339,11 @@ BPF_XOR 0xa0 atomic xor ``BPF_ATOMIC | BPF_W | BPF_STX`` with 'imm' = BPF_ADD means:: - *(u32 *)(dst_reg + off16) += src_reg + *(u32 *)(dst + offset) += src ``BPF_ATOMIC | BPF_DW | BPF_STX`` with 'imm' = BPF ADD means:: - *(u64 *)(dst_reg + off16) += src_reg + *(u64 *)(dst + offset) += src In addition to the simple atomic operations, there also is a modifier and two complex atomic operations: @@ -313,16 +358,16 @@ BPF_CMPXCHG 0xf0 | BPF_FETCH atomic compare and exchange The ``BPF_FETCH`` modifier is optional for simple atomic operations, and always set for the complex atomic operations. If the ``BPF_FETCH`` flag -is set, then the operation also overwrites ``src_reg`` with the value that +is set, then the operation also overwrites ``src`` with the value that was in memory before it was modified. -The ``BPF_XCHG`` operation atomically exchanges ``src_reg`` with the value -addressed by ``dst_reg + off``. +The ``BPF_XCHG`` operation atomically exchanges ``src`` with the value +addressed by ``dst + offset``. The ``BPF_CMPXCHG`` operation atomically compares the value addressed by -``dst_reg + off`` with ``R0``. If they match, the value addressed by -``dst_reg + off`` is replaced with ``src_reg``. In either case, the -value that was at ``dst_reg + off`` before the operation is zero-extended +``dst + offset`` with ``R0``. If they match, the value addressed by +``dst + offset`` is replaced with ``src``. In either case, the +value that was at ``dst + offset`` before the operation is zero-extended and loaded back to ``R0``. 64-bit immediate instructions @@ -335,7 +380,7 @@ There is currently only one such instruction. ``BPF_LD | BPF_DW | BPF_IMM`` means:: - dst_reg = imm64 + dst = imm64 Legacy BPF Packet access instructions From patchwork Wed Oct 19 18:38:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Thaler X-Patchwork-Id: 13012280 X-Patchwork-Delegate: bpf@iogearbox.net Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2AEFC4332F for ; Wed, 19 Oct 2022 18:38:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229885AbiJSSi4 (ORCPT ); Wed, 19 Oct 2022 14:38:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229803AbiJSSiz (ORCPT ); Wed, 19 Oct 2022 14:38:55 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4C77189C30 for ; Wed, 19 Oct 2022 11:38:54 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id e129so17023157pgc.9 for ; Wed, 19 Oct 2022 11:38:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M0k3UitIuZs8QbREBS2h3Pc+EVFq/RHeV38kSddPEQQ=; b=cJIdnYGrlFLTQ/pmsfdG6vB3y/ot1C7WuTo0EQv85ateL6+L/hYQRtD3QLoXxIkxBf fhWG6SYs0aMulhAFsj7xr2OGF5Suk387VXzIVH5PPRqPTuogyp5PS9E5XkjaPzdMtYRR vVd0HVJH3l/vk/MhCco3mS48Lk7AzVPursUfIcvFCH8zkFEcV4PFqzZu8Hcs71axxyK0 9stR6kfTPKJRD1v2io1cZL4HClTEY+OLIdLpPxKxrTfLzXJrVzTIFn/6orfaRZKdOPIf GqQxKZS7OnrTWqpAb6ADFzdjmZBYwZU5VNVsM3lOCgBCofH6Gzm5F1hBEKo1iNpZsGYo 3nTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M0k3UitIuZs8QbREBS2h3Pc+EVFq/RHeV38kSddPEQQ=; b=xd78yLEABrmh4GCNNLW30Krq3EhU38OH0zyWN7NnGIXW2NPoeY1mCK6vtfOyuvF7cw MJdGwh9aq46E8UL9JXAEzTRzcUwAe9/OUF6PqUaB2uu7SBDnCqJ+As/zcK2cI3grSEB+ xBe7G+9KXFzUkgmnWYgZjaN/AZ7t/+/dbInESEE4vbPbJqOTUmkcCs9jW0CrQPcy7YNB xoRlyca9pJhE3OOT/407Fy+3hLGfcQ+CP1ldj3ioQVfuukqNXqKY4Zth20RLeI8Jtxcs T1enJJVage31kKhdOY4swv0PgI7JnBUzBHedJp7nwnBdsZSP52zBp3JrXv+TpE0z5UKy K8TQ== X-Gm-Message-State: ACrzQf1BIX51e3vCQjcHWVbRyEb2S4ALZcWp7Sc4u3kbPhZ8fG/yJMA2 +ll93i3IbPJ4nYXMBocevgEka7JXB4Edqw== X-Google-Smtp-Source: AMsMyM647pe54sjfn91KpZTfSIEArldRGfeq3X3oQcbXBYMNs8zSTUJE/WoXxq2JvPGn2qpwNpq2/A== X-Received: by 2002:a63:5519:0:b0:457:dced:8ba1 with SMTP id j25-20020a635519000000b00457dced8ba1mr8161929pgb.163.1666204733726; Wed, 19 Oct 2022 11:38:53 -0700 (PDT) Received: from mariner-vm.. (c-67-185-99-176.hsd1.wa.comcast.net. [67.185.99.176]) by smtp.gmail.com with ESMTPSA id x2-20020a170902a38200b00177ff4019d9sm11104510pla.274.2022.10.19.11.38.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 11:38:53 -0700 (PDT) From: dthaler1968@googlemail.com To: bpf@vger.kernel.org Cc: Dave Thaler Subject: [PATCH 4/4] bpf, docs: Explain helper functions Date: Wed, 19 Oct 2022 18:38:45 +0000 Message-Id: <20221019183845.905-4-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 In-Reply-To: <20221019183845.905-1-dthaler1968@googlemail.com> References: <20221019183845.905-1-dthaler1968@googlemail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Explain helper functions. Kernel functions and bpf to bpf calls are covered in a later commit in this set ("Add extended call instructions"). Signed-off-by: Dave Thaler --- Documentation/bpf/instruction-set.rst | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 29b599c70..f9e56d9d5 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -242,7 +242,7 @@ BPF_JSET 0x40 PC += off if dst & src BPF_JNE 0x50 PC += off if dst != src BPF_JSGT 0x60 PC += off if dst > src signed BPF_JSGE 0x70 PC += off if dst >= src signed -BPF_CALL 0x80 function call +BPF_CALL 0x80 function call see `Helper functions`_ BPF_EXIT 0x90 function / program return BPF_JMP only BPF_JLT 0xa0 PC += off if dst < src unsigned BPF_JLE 0xb0 PC += off if dst <= src unsigned @@ -253,6 +253,22 @@ BPF_JSLE 0xd0 PC += off if dst <= src signed The eBPF program needs to store the return value into register R0 before doing a BPF_EXIT. +Helper functions +~~~~~~~~~~~~~~~~ +Helper functions are a concept whereby BPF programs can call into a +set of function calls exposed by the eBPF runtime. Each helper +function is identified by an integer used in a ``BPF_CALL`` instruction. +The available helper functions may differ for each eBPF program type. + +Conceptually, each helper function is implemented with a commonly shared function +signature defined as: + + u64 function(u64 r1, u64 r2, u64 r3, u64 r4, u64 r5) + +In actuality, each helper function is defined as taking between 0 and 5 arguments, +with the remaining registers being ignored. The definition of a helper function +is responsible for specifying the type (e.g., integer, pointer, etc.) of the value returned, +the number of arguments, and the type of each argument. Load and store instructions ===========================