From patchwork Thu Oct 20 07:58:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13012771 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2E52C433FE for ; Thu, 20 Oct 2022 07:59:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=I+TqpGYL5Hn8IxI6A5QFSIvI9oDUayPBi0LyZ/+c9Y8=; b=koj/f3e/jBLOZ7 AsoJ1cCS6Byi2n3wnaYN+mF9+k7e/GU6vlL/kIhc0TiJnYRQlnffP63fatQxDO71x78ADBmPhzguu Y+YcdEsdclZBEyAKJV5rg5iWkTNBa4wdno8Km1FXoxEESuTlfF6IHJGkliQ60xRYYJ097XrQ9FcyG qvsBcZBMGMYLk/VZnV2/ERqAMmu9M+hProUxV6bXspCGebBGAUUMdwj7yCQC/OPFGVgHtHwHmycNT BFdmBdegh6rQfFd2aaAps+6VFr1grc4TyzRQ/xf4O8ZftJqc/pnwUuMD8rq3Os3IF0idRa0J1uhvU At4o2kHAI4J+DynGsnBQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1olQSH-00C0rs-Ax; Thu, 20 Oct 2022 07:59:05 +0000 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1olQSE-00C0oq-BB for linux-riscv@lists.infradead.org; Thu, 20 Oct 2022 07:59:03 +0000 Received: by mail-pf1-x431.google.com with SMTP id m6so19609608pfb.0 for ; Thu, 20 Oct 2022 00:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pAsIYw7sZ9pedrVTYHgIfzcW6BaLpjWwdgXvgEmQOaY=; b=KVCqQo/Qymbi41s1GUvHpj3Wa5ZypO8gqStPS/9xn5zgaSL7zarcIcxDhnsDA/Iv6H xDxS2Ox3UAG1mZR376x/ShdVFwZWb1o8wEai1lgskVK8Y2IGL9/Ulx0HVzk8RtyhbKhm QP/grnXg+4nuN2+5lplMkJjPRv6pcSnWZCLkH/y8xE86Y4JaQp9Cijci1o5tTkUDzGPj rZU62/JDjfV98OLvz/x0lhSpy3gj5m3JOcNChEIHA6cpCS4LSCXSz7KKmPPpcsPMgEdl JOAGQSC4At6e1OBUJ0L17wsET+PnN4fPY/XJvBo81AgTiL+SNJb5OfHwaMExuIQ2rZ+/ 2AzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pAsIYw7sZ9pedrVTYHgIfzcW6BaLpjWwdgXvgEmQOaY=; b=WBV3jkvChSSokSkj3kQjSD4WPbjX0GXsMhmhyFxmU4JP8Vjyfm7+3AmFJ4p8Uo/M3q VP2JaLmlqWJm95mK4viPAyR9kqyTbc7fN8ujtCfB0atTSTYSueK10NmWsiz1CnJYwmrQ 934qfIonjgRFhVrg+xtt0cNiBOliff3FQs6utyH+lBlnJ9xtsGwyyiCe8lp4Jidmqxc3 HZw/0f2hEt3G6fVRXuAYHhRx58IGmYuDA3GnX+chmIpeNedpciYY+uluI4vm1qvL9VjL 9WAfF1KeZE5X7B2kodhkAiOkrosY/tgUSGfaoGSRifwrglE3GXmNRv4unsbBzStYnhEz ibtg== X-Gm-Message-State: ACrzQf3RMl5614ztLGg2JluoWc8X5/0Q0EAXB+f1hrmxp+QoTphUE5PZ OSLZJr+32bRVEk2Wcq53VwEI2w== X-Google-Smtp-Source: AMsMyM7UCFvQaa7jwg80SjAqa1N1TyrjSWdPX8DKXF4Z/drUnTh21rNLOzM1OFg/9Bs2UjVCRigQtQ== X-Received: by 2002:a63:cf4f:0:b0:462:da7a:1ded with SMTP id b15-20020a63cf4f000000b00462da7a1dedmr10543458pgj.605.1666252739916; Thu, 20 Oct 2022 00:58:59 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.80.23]) by smtp.gmail.com with ESMTPSA id h30-20020aa79f5e000000b0052dfe83e19csm13206438pfr.16.2022.10.20.00.58.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 00:58:59 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Jones , kernel test robot , Anup Patel , Conor Dooley Subject: [PATCH v5 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM Date: Thu, 20 Oct 2022 13:28:43 +0530 Message-Id: <20221020075846.305576-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020075846.305576-1-apatel@ventanamicro.com> References: <20221020075846.305576-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221020_005902_413777_19C6C829 X-CRM114-Status: GOOD ( 16.01 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Andrew Jones riscv_cbom_block_size and riscv_init_cbom_blocksize() should always be available and riscv_init_cbom_blocksize() should always be invoked, even when compiling without RISCV_ISA_ZICBOM enabled. This is because disabling RISCV_ISA_ZICBOM means "don't use zicbom instructions in the kernel" not "pretend there isn't zicbom, even when there is". When zicbom is available, whether the kernel enables its use with RISCV_ISA_ZICBOM or not, KVM will offer it to guests. Ensure we can build KVM and that the block size is initialized even when compiling without RISCV_ISA_ZICBOM. Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") Reported-by: kernel test robot Signed-off-by: Andrew Jones Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/include/asm/cacheflush.h | 8 ------ arch/riscv/mm/cacheflush.c | 38 ++++++++++++++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 41 ----------------------------- 3 files changed, 38 insertions(+), 49 deletions(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 8a5c246b0a21..f6fbe7042f1c 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -42,16 +42,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local); #endif /* CONFIG_SMP */ -/* - * The T-Head CMO errata internally probe the CBOM block size, but otherwise - * don't depend on Zicbom. - */ extern unsigned int riscv_cbom_block_size; -#ifdef CONFIG_RISCV_ISA_ZICBOM void riscv_init_cbom_blocksize(void); -#else -static inline void riscv_init_cbom_blocksize(void) { } -#endif #ifdef CONFIG_RISCV_DMA_NONCOHERENT void riscv_noncoherent_supported(void); diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6cb7d96ad9c7..57b40a350420 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #ifdef CONFIG_SMP @@ -86,3 +87,40 @@ void flush_icache_pte(pte_t pte) flush_icache_all(); } #endif /* CONFIG_MMU */ + +unsigned int riscv_cbom_block_size; +EXPORT_SYMBOL_GPL(riscv_cbom_block_size); + +void riscv_init_cbom_blocksize(void) +{ + struct device_node *node; + unsigned long cbom_hartid; + u32 val, probed_block_size; + int ret; + + probed_block_size = 0; + for_each_of_cpu_node(node) { + unsigned long hartid; + + ret = riscv_of_processor_hartid(node, &hartid); + if (ret) + continue; + + /* set block-size for cbom extension if available */ + ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); + if (ret) + continue; + + if (!probed_block_size) { + probed_block_size = val; + cbom_hartid = hartid; + } else { + if (probed_block_size != val) + pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", + cbom_hartid, hartid); + } + } + + if (probed_block_size) + riscv_cbom_block_size = probed_block_size; +} diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b0add983530a..d919efab6eba 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -8,13 +8,8 @@ #include #include #include -#include -#include #include -unsigned int riscv_cbom_block_size; -EXPORT_SYMBOL_GPL(riscv_cbom_block_size); - static bool noncoherent_supported; void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, @@ -77,42 +72,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, dev->dma_coherent = coherent; } -#ifdef CONFIG_RISCV_ISA_ZICBOM -void riscv_init_cbom_blocksize(void) -{ - struct device_node *node; - unsigned long cbom_hartid; - u32 val, probed_block_size; - int ret; - - probed_block_size = 0; - for_each_of_cpu_node(node) { - unsigned long hartid; - - ret = riscv_of_processor_hartid(node, &hartid); - if (ret) - continue; - - /* set block-size for cbom extension if available */ - ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); - if (ret) - continue; - - if (!probed_block_size) { - probed_block_size = val; - cbom_hartid = hartid; - } else { - if (probed_block_size != val) - pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", - cbom_hartid, hartid); - } - } - - if (probed_block_size) - riscv_cbom_block_size = probed_block_size; -} -#endif - void riscv_noncoherent_supported(void) { WARN(!riscv_cbom_block_size, From patchwork Thu Oct 20 07:58:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13012772 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A170DC433FE for ; Thu, 20 Oct 2022 07:59:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ERNH/83Lk6vTNmxYwnu7232d+1jfTGqVU3g6kpEJV5w=; b=04CNEgPIS3XE88 6Al+HZ3u/aqpeGZfPhmqoAvGrQ9CS9E/eZngOaLFO/22LKEJ6IQNbn6GzNJflLioV2boXkL+o6m2Q G36w+LvQWZWOkIrgLRkcg0ID23gCNx8TX0+Yw88Au9yE8+dn20eGQI8MEMDhF/e71MmDtDpx4t/PN +Adv2appI9OCAOnLCJZR+PYJm0ca1FaoUEY2pRJmsFCAxjhky7V56OZmJw1yf+ChCzQyVFhvP7+eY ISTHRu2dvMd5JObTIfE1Hb6zCTLcxb2FP1glNx82C4K8QYSus/UvLfXcYQ9wkaLoBbAePB+fXEpIU jlWDSsEt41nSNflVUonQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1olQSK-00C0u2-Oa; Thu, 20 Oct 2022 07:59:08 +0000 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1olQSJ-00C0rj-1V for linux-riscv@lists.infradead.org; Thu, 20 Oct 2022 07:59:08 +0000 Received: by mail-pl1-x62f.google.com with SMTP id y4so734592plb.2 for ; Thu, 20 Oct 2022 00:59:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XuilwbSjTkXNw6j4kYlnUJ0pwJrZlWFK5/+cTZqJbNQ=; b=ZKNy4Em5+FuBRP2gsIy40Yrk6FnGU3CqJrbS4NGA0H4o/nv3ogel1a+BelUzdLO1+g EU+MmxJ/fG6lCskSK8CjnrO6mvqd192jk75tdkMPCx2sj0HVYrLPSIl/FCjUKLQqhXIR O+B28Y0IXu56SXNEgwVgKrhhZ6VobhnpNyQY2oG3K0B/EDQxN58o7Xd2xk1gaHZyl3fF njlaQHg7PekkPyXa7GZgMueBWS6N6jJ9f91rD5qgIsxZw9SBJj74KQ+Ze7eazFE4kmgx E0MgKtM0nHURmmTr65D876z74uLsOqBlxTsCGuq16N7OZB/lo37TXNpMWUkkYyqExwcp ohiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XuilwbSjTkXNw6j4kYlnUJ0pwJrZlWFK5/+cTZqJbNQ=; b=GbKGjaTVGA+P7iVutb0LE9VRNheCLokrkkT/1GVSZfArLwMds+beuyMtLXHaceKohJ 5rNTsDUBWGrSZPmn7HBUEwqFR9Io5aZqPS3Lc2Xnm4v2V2p/ZclaZ1kUCihxt1LRRLXS si4DTdcpggh8/hBKKDkASo71KIcZa3OIiyBk9Im4QAPoVPLJnFLrkxzrRIdzUSwqPFAE 03MaChHBog06Nw+m1Wejjxiaf52/DbSU0+i8LeMSPOOZvZQi/XyHq2Q+OKEKNZRmuUBr bGtS7pOsu+PTyIyFd31OrhHwv9DzyxjrHrJ7gdHD8kydB/fjZDh++aqwKmY5aycpr3+j xT8g== X-Gm-Message-State: ACrzQf07JUthv9P4R7C5ihBG+ExiCKGDHZ1DpgonQDsc4TcCFUZXhDR8 CDTpaXgrTuV3dkuFY0Ir4uqSKg== X-Google-Smtp-Source: AMsMyM4owvZnTyqDDywJXkxNgsuebJjnZ5lE2U3qnXcYFm8cRhbjwN/IzGov1M7IHnfRXLtTT1BHcA== X-Received: by 2002:a17:902:eb89:b0:185:33d:cb34 with SMTP id q9-20020a170902eb8900b00185033dcb34mr12806731plg.55.1666252744045; Thu, 20 Oct 2022 00:59:04 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.80.23]) by smtp.gmail.com with ESMTPSA id h30-20020aa79f5e000000b0052dfe83e19csm13206438pfr.16.2022.10.20.00.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 00:59:03 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH v5 2/4] RISC-V: Fix MEMREMAP_WB for systems with Svpbmt Date: Thu, 20 Oct 2022 13:28:44 +0530 Message-Id: <20221020075846.305576-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020075846.305576-1-apatel@ventanamicro.com> References: <20221020075846.305576-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221020_005907_103945_B43894CF X-CRM114-Status: UNSURE ( 9.00 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently, the memremap() called with MEMREMAP_WB maps memory using the generic ioremap() function which breaks on system with Svpbmt because memory mapped using _PAGE_IOREMAP page attributes is treated as strongly-ordered non-cacheable IO memory. To address this, we implement RISC-V specific arch_memremap_wb() which maps memory using _PAGE_KERNEL page attributes resulting in write-back cacheable mapping on systems with Svpbmt. Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- arch/riscv/include/asm/io.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 92080a227937..42497d487a17 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -135,4 +135,9 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) #include +#ifdef CONFIG_MMU +#define arch_memremap_wb(addr, size) \ + ((__force void *)ioremap_prot((addr), (size), _PAGE_KERNEL)) +#endif + #endif /* _ASM_RISCV_IO_H */ From patchwork Thu Oct 20 07:58:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13012773 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB4D5C433FE for ; Thu, 20 Oct 2022 07:59:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8R0n0GPtEX0PNmePzPYFBQOKR/X+TTGgyZNOfkcDrzU=; b=w28OUILu0rhBOM IUsak1zDNlQr+cVOo9fgq6/IXd4tPnjqKqHt7mCKBrAp0XGaql88RQVSq1AcNj4U30F+m20EG+Gfs tUoxovhjlduSyrVA9X6c2CBOOg5KxiDkAUIVBjX3vZFl/984DkSVNrK7NOpTSkQ2utRSUuLOKhPwk Cb4hFr4xecY6FmqL1qiU2iJS8wADxjp+VBYVcw4k3m23s8xwA83vrSDl0vrjG/S7iIoExuZIx/QHe GsCTFJQGWIe7YgVZsFiHWX7yenSdmR+byCzq4sjkzhZAazZSIiT9HeQs6wfrlsDz0FMwLaBwoI58t 33GZ2OOzG9UqpehXemFg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1olQSP-00C0wW-6r; Thu, 20 Oct 2022 07:59:13 +0000 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1olQSM-00C0tJ-5q for linux-riscv@lists.infradead.org; Thu, 20 Oct 2022 07:59:11 +0000 Received: by mail-pf1-x42a.google.com with SMTP id i3so19539827pfc.11 for ; Thu, 20 Oct 2022 00:59:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VDJV4ZwRVQLzE0DQMb9i2tBKWni84XeHMbgigRoQK/0=; b=RtIs+Fo57m4OyjqREQ+GmkLa1gtB+nd1wI1cynGPWeyR4VuzuTZWYwxJp3qb38jND+ jXzllqItnzM8dXynZdtd4gBtlQcrTFv3q3wLdb9aYmU1re7J1CS7QNaEBpwC5Es4tMoP 8fhXm+QGwvfvAnRFygQrEktJR97lrpRTNwcBmjOVjVyH0enR9liXz+TuLkEd3jbxNgtS 0Q5pPUbWB2jqGj3mst8Fq1vF9FPWmupAtBR8zOnr4ZeSflblwpcDKp/m4D9umY0Ly4J6 EgHMvrkLGNAoI6X8hUK3eiUWTy+WmHETYpx3tSzPJFfbAnLWn8XU2jYA24Eu1d6/08Ar W+wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VDJV4ZwRVQLzE0DQMb9i2tBKWni84XeHMbgigRoQK/0=; b=lXjAJGJU7VDyGrwyjoD9qWu5hvIiBmPm5m9hLA3H+HYpG5K2ou4N2jzS6wcvv2XKjy RRmAPiMAQCIZaFWyg1QEsPA21G98Hh6c5mdKEDDFfSC+K2xNdf7WcLQGzZVjKDW3XuHF w+aaB1X+BflHFbDB1Ek0zxHP6BYQTLsnDPZ6XnCBT2TF5hiMc+LDj3NelOfGj0M+fIKx MJZpizKNK/YsytrzRJ0Vva1efjhvuCp9Jt6Un6KB8ocJ8t0g8gatGvk+ZR4+v6EtWpPw dCZipchOUrcN5D246grYVcwfJzqYTzRFvkH/48Ar/W/rdLgP9u+pnpa2NLkstDrq00sL r/Mg== X-Gm-Message-State: ACrzQf1ZOdiZjpWr2Ojo4TiMOEqGH+1setLIOSwP6j9jtXQHNRGoTeau 4NxJb30NEp30GubOFJ5aWdmkvQ== X-Google-Smtp-Source: AMsMyM4+Y3j2NNCSyJHfzbf9XmZTArI3CBMgBB4JZwGFMWkS1y+U/PGzCotqjnP6BECxn5NkaxBZpA== X-Received: by 2002:a63:2b4b:0:b0:440:2963:5863 with SMTP id r72-20020a632b4b000000b0044029635863mr10501248pgr.28.1666252748070; Thu, 20 Oct 2022 00:59:08 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.80.23]) by smtp.gmail.com with ESMTPSA id h30-20020aa79f5e000000b0052dfe83e19csm13206438pfr.16.2022.10.20.00.59.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 00:59:07 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH v5 3/4] RISC-V: Implement arch specific PMEM APIs Date: Thu, 20 Oct 2022 13:28:45 +0530 Message-Id: <20221020075846.305576-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020075846.305576-1-apatel@ventanamicro.com> References: <20221020075846.305576-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221020_005910_226501_31749CF9 X-CRM114-Status: GOOD ( 13.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The NVDIMM PMEM driver expects arch specific APIs for cache maintenance and if arch does not provide these APIs then NVDIMM PMEM driver will always use MEMREMAP_WT to map persistent memory which in-turn maps as UC memory type defined by the RISC-V Svpbmt specification. Now that the Svpbmt and Zicbom support is available in RISC-V kernel, we implement PMEM APIs using ALT_CMO_OP() macros so that the NVDIMM PMEM driver can use MEMREMAP_WB to map persistent memory. Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 1 + arch/riscv/mm/Makefile | 1 + arch/riscv/mm/pmem.c | 21 +++++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 arch/riscv/mm/pmem.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6b48a3ae9843..025e2a1b1c60 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -25,6 +25,7 @@ config RISCV select ARCH_HAS_GIGANTIC_PAGE select ARCH_HAS_KCOV select ARCH_HAS_MMIOWB + select ARCH_HAS_PMEM_API select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index d76aabf4b94d..3b368e547f83 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -31,3 +31,4 @@ endif obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o +obj-$(CONFIG_ARCH_HAS_PMEM_API) += pmem.o diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c new file mode 100644 index 000000000000..089df92ae876 --- /dev/null +++ b/arch/riscv/mm/pmem.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include +#include + +#include + +void arch_wb_cache_pmem(void *addr, size_t size) +{ + ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); +} +EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); + +void arch_invalidate_pmem(void *addr, size_t size) +{ + ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); +} +EXPORT_SYMBOL_GPL(arch_invalidate_pmem); From patchwork Thu Oct 20 07:58:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13012774 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22F4AC4332F for ; Thu, 20 Oct 2022 07:59:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VAG6PNjIYmLqTuGIeOwVsF8LbJffHJHY9dL/+kAaDEs=; b=bE3DAYCh3HfgQl JQKuOqoNX9VXyW8DN4AVsFgeo5zpWO6vhlheKRc2xJoma8IBhMwzFVQ4K5NH4WAJPalLN/nGwB3I2 jg6ZvoGFV0qy5gEu4jYxx8oAqeOQD9j1RKLQEIqKhgeRp+O6iD03xuq1tht9y/0ZLNO6rKvKDwmtI dd6wpEP/26jfiS+PsV5kRHpjzEtH6ICkn0+LRtcSJrv12rzx+fjG4qkzhQFqzP+647JfuXqXaIKRV 4F8fQLoWqTvlLR2eWsXw+lnHzX3+U3X4YRNdRQrTEOynlDg9EIUbZGat4Iw5//cXp9WW7+ENLE+fq 0EeoFCLCv1jusPdKeDWw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1olQST-00C133-0Z; Thu, 20 Oct 2022 07:59:17 +0000 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1olQSQ-00C0w0-V9 for linux-riscv@lists.infradead.org; Thu, 20 Oct 2022 07:59:16 +0000 Received: by mail-pg1-x52a.google.com with SMTP id e129so18513797pgc.9 for ; Thu, 20 Oct 2022 00:59:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5TnLW0RVC/l/l6ZpSJGiQ9RS55Sh7Bww2u/zF6eZ2bY=; b=eL/0WYugw3H/1sxFC9WdKuigQo+DLOOuD80Q50Flm9AQs84m3h9nhYf0lLQYFWRd39 DXs4iq9U35DNMud1OLd+16okiAB2eoq7QcO9OSbRglrpg20DSO8trF8j8xmLmCcLLGPC cN3DT63GsaCqDSugUopR1AvikeqYg8gC613t1k9CY7q9hO9lJ8lvKYl8Ek4e6lDvJMlw vPg3fbNz3pUhmLaNqjOoHF5hZZCC/VZeRstJaWGQUmsQd8PNC4hcrRrPGFxTNz1xt4pK Bw1uR/NrBdi2x1QlXQ8AkRO/ok1dsPlcpY1fOB2o0/DwqFlo7APjo4OD+L3+tAq4gC1g HMtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5TnLW0RVC/l/l6ZpSJGiQ9RS55Sh7Bww2u/zF6eZ2bY=; b=RAh0D5Yz6LwwoeWC0Z5LHBTGfFuJCpSE5fZaujwuG5ZG9rEHHbOZdFyVa+fuIQdmsi PQzJpwVD1u4ERUMoTLaF4myfXyk34X/cVm5lCXDId7UtJZ+IO7jFPuUWv9x1NCkvhvMO uhAHIrc5KmatMdwVJSKZZQZEg7GsQxFSvUepgIzF7/tFhuLJOirw0W1C+Ymjs0qA5z+W HdsHy6t7YESj/llfT7gjw7Ig3GM+grdlZnuP2G6kkhBsp71bzGLlxMzzwzn4gh9gta8W s/K+nJ0GXeY9NzpH8dTH6GiMk5BUHlir2PzBlzQyzm+uXyZYY6dNT1S1OeQgsimygpE0 YCAw== X-Gm-Message-State: ACrzQf1WjE/5xiVkqqenrvW4zFLiZDGfUf0KndmahnO1NtoXvn3hAhhA BvwQ+HEoSj4FHh8Coinrk+QFjA== X-Google-Smtp-Source: AMsMyM5695BW3bf/MyxpS9FPVNImhqrzxiREVKiQzjuNPGrSayyB3orzN/hf7wn69DCszXPk5MNb7w== X-Received: by 2002:a63:ef18:0:b0:439:befc:d89c with SMTP id u24-20020a63ef18000000b00439befcd89cmr10373730pgh.504.1666252752020; Thu, 20 Oct 2022 00:59:12 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.80.23]) by smtp.gmail.com with ESMTPSA id h30-20020aa79f5e000000b0052dfe83e19csm13206438pfr.16.2022.10.20.00.59.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 00:59:11 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v5 4/4] RISC-V: Enable PMEM drivers Date: Thu, 20 Oct 2022 13:28:46 +0530 Message-Id: <20221020075846.305576-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020075846.305576-1-apatel@ventanamicro.com> References: <20221020075846.305576-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221020_005915_021767_5BD88D4F X-CRM114-Status: UNSURE ( 7.06 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We now have PMEM arch support available in RISC-V kernel so let us enable relevant drivers in defconfig. Signed-off-by: Anup Patel --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 05fd5fcf24f9..462da9f7410d 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -159,6 +159,7 @@ CONFIG_VIRTIO_MMIO=y CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_CTRL=y CONFIG_RPMSG_VIRTIO=y +CONFIG_LIBNVDIMM=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y