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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 01/12] Arm: GICv3: Sysreg emulation is applicable for Aarch64 only Date: Fri, 21 Oct 2022 16:31:17 +0100 Message-ID: <20221021153128.44226-2-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT018:EE_|MN0PR12MB6319:EE_ X-MS-Office365-Filtering-Correlation-Id: ef95849f-fcec-4e2a-42cf-08dab37965f0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xbE6eyyPJmD9Tb/YTpKB+sPbR8jeBrzmY4TukGJNKkkDHivDPYM3LPKG9J/QU5cYmpQGOyANQjROI+aev2++RaTZg6LzwTBuk1JFX8newkIiBRXw7Rq7JogoHzvm6nTh3OZx+RxI+Wpz6yyJnaqKT8TlnK1Kh9Dc7p34g6vJi4lNaqzoEZTjDgzb9TxqTak8IpRd5gHFEy/wywxLGxn2OWgNhZvkswfwPPhypKpnRC5QVotfGaGKRdqETOMJVjQfesZfXpm0ckrhbDebNAmNi3R4+J5BwbcngPSyJIhuM5hdDgTX8VFztQ8zbiWv+sHVf487URmlHiw0iVjNkl7j98CFAB2u1uuLJxNRnI7lUun1VPkflOniDeRoYkNiQjXqm/OtpKO9QU7y9JHiJEJJuinE4+wrWiXAMjKB7lJCh9v9JFf+Er9nyjP+l1asFQenQqVrXBPcd6pkbbGY+zUR/tHbHJkOfLrzVbCngqzZWjsADwhCccS4v4hJxNKX/ywkaR3sI1+VAcMd6+O1U/s3gA/vvfD/yKpFOc7zsw2iTnhUR/eEs4pGxjTAAcxYcB/38IGp5z76g76I5Y47uV/2q6aLln8Kfpu5jPmpqjI/lB9PTx2vdHMrZ3F+AE7qGv1JgeUB7F8nfX8PeqiFHXvLu1P9gE3HMvFJ/UTY4rDQEOLKBQt+bTV6CNO8u47pa3uEE9JzbwnFr22QXPA7RCv6LmL+zLU8szzG6YF8U/VX7w+fWybA/6YxbfDPlrpFSAX0Yib9moqpad9tzVYPd/9IckMYUGBfU6w76SH9KcWS9YQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(39860400002)(396003)(346002)(451199015)(46966006)(40470700004)(36840700001)(70586007)(82740400003)(6666004)(5660300002)(186003)(8936002)(1076003)(36860700001)(40460700003)(336012)(36756003)(40480700001)(2616005)(41300700001)(70206006)(4326008)(8676002)(426003)(47076005)(26005)(2906002)(478600001)(82310400005)(356005)(81166007)(316002)(54906003)(6916009)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:00.8537 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef95849f-fcec-4e2a-42cf-08dab37965f0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6319 Refer ARM DDI 0487G.b ID072021, EC==0b011000 is supported for Aarch64 state only. This is when MSR, MRS, System instruction execution in AArch64 state is trapped, that is not reported using EC 0b000000, 0b000001 or 0b000111. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/vgic-v3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 0c23f6df9d..c31140eb20 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1520,6 +1520,7 @@ static bool vgic_v3_emulate_sgi1r(struct cpu_user_regs *regs, uint64_t *r, } } +#ifdef CONFIG_ARM_64 static bool vgic_v3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr) { struct hsr_sysreg sysreg = hsr.sysreg; @@ -1540,6 +1541,7 @@ static bool vgic_v3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr) return false; } } +#endif static bool vgic_v3_emulate_cp64(struct cpu_user_regs *regs, union hsr hsr) { @@ -1563,8 +1565,10 @@ static bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr) { switch (hsr.ec) { +#ifdef CONFIG_ARM_64 case HSR_EC_SYSREG: return vgic_v3_emulate_sysreg(regs, hsr); +#endif case HSR_EC_CP15_64: return vgic_v3_emulate_cp64(regs, hsr); default: From patchwork Fri Oct 21 15:31:18 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 02/12] Arm: GICv3: Move the macros to compute the affnity level to arm64/arm32 Date: Fri, 21 Oct 2022 16:31:18 +0100 Message-ID: <20221021153128.44226-3-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT056:EE_|CH3PR12MB7497:EE_ X-MS-Office365-Filtering-Correlation-Id: 306a0c7a-cd74-45fc-b6b6-08dab379687f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xRAKep4aX+Wez7T1xQTkOI4t+8TrMrwbL0KKC70pc+keeJRcflLu41uNaDCeKMMzyopjn4HLDXVi5q92Ep53klYwibnGxap5D9+c8ifxq7BeYKkxuP/yDLP+eTJX1cmDBTArwsBLmX2YUgy5Uhi27vYLtjBx2rb/VvUEx1jLBZWGKeOQ8cLDfSBmuGt1EpIqIcF+hSWhPBAUduA5lMasrZiN+GyzEVvkTWsQYFy/Nipbor7QPX57FbnTH/0X0/XwyzYx4y7kAgw5UbQR+WsCp6h5+XxKjD66PhrV5vvXT+gy+ws22vrWZG+Vpwq6UOh9SThZD1CZVQvbWGELTe/L/ftN662nZaH0FTdk46dnRDFfxeV++hp0egAXFRfRfVbWpZJJIXjhNk3aXgj4mYN8erCAs0J3vjmWp/DsGMkBZ/OW9D9I7jXZHzRZMQEYm+8fO0UkQYvKUWfHKuA6y2oxaQld7mJ8ssGFwqBTAZewGYM8OgjJ4d24y6PZDc6SknXV8h98PgHIaRd18vPUB6e9PcRPx1DgPJBXMLSYQ04ynYqCNKL5ZFtVhanTWSAnfaXUO5KqUFU9j7uTgtAc791N1ogEqDXO2oyvt48iBGRJ/NyMpUU6Ukk/TpoLFi2adeNz65MRbnAHg8hpRN9HrfNllGwYWvHUL+Z8ljt3kP3+tPvfHk3q7uAuBkm6XrF0Gv5CtdneI3nx3Xi3q6bZg8Eq2hxBSJt/IdtixXxNbwpeQTzehvnMsldiBjF9maNvCD0fDZ2kdi/G3lSmExjkwLZS5t1VqUGZ+uRLm7yym5qbjkUs/zy3Es08z819zzScuLbdXWN7SsmOTqMvOPKEa/PYDUHTxayCI72H99/NCBki6rIyxBdlr9DqjfGWO/YnQpM4 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(376002)(136003)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(36860700001)(316002)(6916009)(41300700001)(54906003)(186003)(8936002)(47076005)(426003)(40480700001)(2616005)(26005)(6666004)(2906002)(70586007)(336012)(1076003)(5660300002)(70206006)(83380400001)(36756003)(40460700003)(4326008)(8676002)(478600001)(82310400005)(81166007)(356005)(82740400003)(966005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:05.1492 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 306a0c7a-cd74-45fc-b6b6-08dab379687f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7497 Refer https://elixir.bootlin.com/linux/v6.1-rc1/source/arch/arm64/ \ include/asm/cputype.h#L14 , these macros are specific for arm64. When one computes MPIDR_LEVEL_SHIFT(3), it crosses the width of a 32 bit register. Refer https://elixir.bootlin.com/linux/v6.1-rc1/source/arch/arm/include/ \ asm/cputype.h#L54 , these macros are specific for arm32. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/arm32/processor.h | 10 ++++++++++ xen/arch/arm/include/asm/arm64/processor.h | 13 +++++++++++++ xen/arch/arm/include/asm/processor.h | 14 -------------- 3 files changed, 23 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/processor.h b/xen/arch/arm/include/asm/arm32/processor.h index 4e679f3273..3e03ce78dc 100644 --- a/xen/arch/arm/include/asm/arm32/processor.h +++ b/xen/arch/arm/include/asm/arm32/processor.h @@ -56,6 +56,16 @@ struct cpu_user_regs uint32_t pad1; /* Doubleword-align the user half of the frame */ }; +/* + * Macros to extract affinity level. Picked from kernel + */ + +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) +#define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level) + +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ + ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK) + #endif #endif /* __ASM_ARM_ARM32_PROCESSOR_H */ diff --git a/xen/arch/arm/include/asm/arm64/processor.h b/xen/arch/arm/include/asm/arm64/processor.h index c749f80ad9..c026334eec 100644 --- a/xen/arch/arm/include/asm/arm64/processor.h +++ b/xen/arch/arm/include/asm/arm64/processor.h @@ -84,6 +84,19 @@ struct cpu_user_regs uint64_t sp_el1, elr_el1; }; +/* + * Macros to extract affinity level. picked from kernel + */ + +#define MPIDR_LEVEL_BITS_SHIFT 3 +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) + +#define MPIDR_LEVEL_SHIFT(level) \ + (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT) + +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) + #undef __DECL_REG #endif /* __ASSEMBLY__ */ diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h index 1dd81d7d52..7d90c3b5f2 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -118,20 +118,6 @@ #define MPIDR_INVALID (~MPIDR_HWID_MASK) #define MPIDR_LEVEL_BITS (8) - -/* - * Macros to extract affinity level. picked from kernel - */ - -#define MPIDR_LEVEL_BITS_SHIFT 3 -#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) - -#define MPIDR_LEVEL_SHIFT(level) \ - (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT) - -#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ - (((mpidr) >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) - #define AFFINITY_MASK(level) ~((_AC(0x1,UL) << MPIDR_LEVEL_SHIFT(level)) - 1) /* TTBCR Translation Table Base Control Register */ From patchwork Fri Oct 21 15:31:19 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 03/12] Arm: GICv3: Enable vreg_reg64_* macros for AArch32 Date: Fri, 21 Oct 2022 16:31:19 +0100 Message-ID: <20221021153128.44226-4-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT045:EE_|IA1PR12MB6281:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f385dee-6892-49c2-dbac-08dab379686e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pgVOpVJYvg1kjNgiGfm4vFwxKUi8YM199IJ5Y7gquURQM0k+AP1yLzh2rnQa6v1n7E1ckKgjTruXh1sY8RoX5995p4h7vRQ8mIRfWqmSriFeBfl/EPaWfukCLsOUCqcC1L1hMlFcfeW8qc4Zfefykv/yWTDBVHgxCMQHMeI++xPqTAbx4TStB2ewcykIk8E2x2qyl4EkD9mUT2VIPMtzr7BTolxq3K2rNbvNy1FFvw817MW4W/kV5cCNk4T0f/r/OZ+K7p2ETiuCpt/9m5S3i+C73uw8peQ448Iddn+4ZntKd+r5P2vXmRUkvSucVi0RdOlE9CbZD+5w6zm+0o+bvGFG+tlvYoGzj3D4Ud6QhfK4QnyGThGQbDtunDSLuw3fDopMkbLd4COrci3b53A+ydwKqJFfUrtyxrThjh7MEFfGE5gD0Z5qWaPjRQa6N2ME3vgIJwHVpBYVmLIlTEVEh+9RGH/WAj0Kk3at29oTuoRrO2uhxjYiF5VIug/9yo+Qn8dAYV9Pb8KjyIG409TrXseo+16lArBEmH4t7eQbtCvnGa8G2lfK9MGDs24djBXtwe1JK/bMwPUmxzOlgtsfDh3VR3nxrAK/I09qTQtUh+KasHXYyL7B0krTe7tC44CNHCvLrF2rfSnTBAbJodIYsK6DrhjQcEGLMZhe7aJNkUkQOOudVEnCHuym7e5PArtA1egMU7Vx9K+qOBThwZA7UZrSsSWI3rohIB/JfMzVg9WaOn6Ff+2VI5ZZjO5kygA5yHepD8icJvVBYK3D+hEH/2fuG3WRiCmAchu/FA1j4fE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(346002)(376002)(136003)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(8676002)(8936002)(41300700001)(5660300002)(2906002)(4326008)(356005)(70206006)(6916009)(82740400003)(36860700001)(478600001)(26005)(6666004)(70586007)(316002)(186003)(36756003)(82310400005)(54906003)(40480700001)(40460700003)(2616005)(81166007)(1076003)(336012)(83380400001)(426003)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:05.0388 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f385dee-6892-49c2-dbac-08dab379686e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6281 In some situations (eg GICR_TYPER), the hypervior may need to emulate 64bit registers in aarch32 mode. In such situations, the hypervisor may need to read/modify the lower or upper 32 bits of the 64 bit register. In aarch32, 64 bit is represented by unsigned long long. Thus, we need to change the prototype accordingly. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/vreg.h | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/include/asm/vreg.h b/xen/arch/arm/include/asm/vreg.h index f26a70d024..ac6e702c5c 100644 --- a/xen/arch/arm/include/asm/vreg.h +++ b/xen/arch/arm/include/asm/vreg.h @@ -95,7 +95,7 @@ static inline bool vreg_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr * Note that the alignment fault will always be taken in the guest * (see B3.12.7 DDI0406.b). */ -static inline register_t vreg_reg_extract(unsigned long reg, +static inline register_t vreg_reg_extract(unsigned long long reg, unsigned int offset, enum dabt_size size) { @@ -105,7 +105,7 @@ static inline register_t vreg_reg_extract(unsigned long reg, return reg; } -static inline void vreg_reg_update(unsigned long *reg, register_t val, +static inline void vreg_reg_update(unsigned long long *reg, register_t val, unsigned int offset, enum dabt_size size) { @@ -116,7 +116,7 @@ static inline void vreg_reg_update(unsigned long *reg, register_t val, *reg |= ((unsigned long)val & mask) << shift; } -static inline void vreg_reg_setbits(unsigned long *reg, register_t bits, +static inline void vreg_reg_setbits(unsigned long long *reg, register_t bits, unsigned int offset, enum dabt_size size) { @@ -126,7 +126,7 @@ static inline void vreg_reg_setbits(unsigned long *reg, register_t bits, *reg |= ((unsigned long)bits & mask) << shift; } -static inline void vreg_reg_clearbits(unsigned long *reg, register_t bits, +static inline void vreg_reg_clearbits(unsigned long long *reg, register_t bits, unsigned int offset, enum dabt_size size) { @@ -149,7 +149,7 @@ static inline void vreg_reg##sz##_update(uint##sz##_t *reg, \ register_t val, \ const mmio_info_t *info) \ { \ - unsigned long tmp = *reg; \ + unsigned long long tmp = *reg; \ \ vreg_reg_update(&tmp, val, info->gpa & (offmask), \ info->dabt.size); \ @@ -161,7 +161,7 @@ static inline void vreg_reg##sz##_setbits(uint##sz##_t *reg, \ register_t bits, \ const mmio_info_t *info) \ { \ - unsigned long tmp = *reg; \ + unsigned long long tmp = *reg; \ \ vreg_reg_setbits(&tmp, bits, info->gpa & (offmask), \ info->dabt.size); \ @@ -173,7 +173,7 @@ static inline void vreg_reg##sz##_clearbits(uint##sz##_t *reg, \ register_t bits, \ const mmio_info_t *info) \ { \ - unsigned long tmp = *reg; \ + unsigned long long tmp = *reg; \ \ vreg_reg_clearbits(&tmp, bits, info->gpa & (offmask), \ info->dabt.size); \ @@ -181,15 +181,8 @@ static inline void vreg_reg##sz##_clearbits(uint##sz##_t *reg, \ *reg = tmp; \ } -/* - * 64 bits registers are only supported on platform with 64-bit long. - * This is also allow us to optimize the 32 bit case by using - * unsigned long rather than uint64_t - */ -#if BITS_PER_LONG == 64 -VREG_REG_HELPERS(64, 0x7); -#endif VREG_REG_HELPERS(32, 0x3); +VREG_REG_HELPERS(64, 0x7); #undef VREG_REG_HELPERS From patchwork Fri Oct 21 15:31:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13014963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D548C433FE for ; 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bh=d3z1fYyjNNFULchMYPGXqvwacdX9nW9qmaUMKuj/M3A=; b=x+hjeR/kGqA+zLETj2Ta8PT0VHLtXwEcYfjOM7y47E1UG6w71hunllmtn67YqsOKy8fQ/bSZdB4U+6tUaXhOIJz7Drs5OpsJ6QjF9rpR4dQUEjVbPRd/xXreAylmjGtPL3MbFZ62S82GzurFZL5MllNxpmfme5SZvVpgFiHfl9M= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 04/12] Arm: GICv3: Emulate GICR_TYPER on AArch32 Date: Fri, 21 Oct 2022 16:31:20 +0100 Message-ID: <20221021153128.44226-5-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT022:EE_|MW4PR12MB5626:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d5d9836-905d-4508-a848-08dab3796a6a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:08.3667 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d5d9836-905d-4508-a848-08dab3796a6a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5626 Refer Arm IHI 0069H ID020922, The upper 32 bits of GICR_TYPER represent the affinity whereas the lower 32 bits represent the other bits (eg processor number, etc). MPIDR_AFFINITY_LEVEL() returns a 32 bit number on aarch32. Thus, this is appended to return GICR_TYPER register. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/vgic-v3.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index c31140eb20..d86b41a39f 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -190,14 +190,18 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, case VREG64(GICR_TYPER): { - uint64_t typer, aff; + uint64_t typer; + uint32_t aff; if ( !vgic_reg64_check_access(dabt) ) goto bad_width; - aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 56 | - MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 48 | - MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 40 | - MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0) << 32); + aff = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 24 | + MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 16 | + MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 8 | + MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0)); typer = aff; + + typer = typer << 32; + /* We use the VCPU ID as the redistributor ID in bits[23:8] */ typer |= v->vcpu_id << GICR_TYPER_PROC_NUM_SHIFT; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 05/12] Arm: GICv3: Emulate GICR_PENDBASER and GICR_PROPBASER on AArch32 Date: Fri, 21 Oct 2022 16:31:21 +0100 Message-ID: <20221021153128.44226-6-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT004:EE_|DM4PR12MB5343:EE_ X-MS-Office365-Filtering-Correlation-Id: 0df10cb3-4e2d-421b-79bb-08dab3796c6e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: l9GOfyapDhb4HMYPkXnT60+LCACh8lYXr2DoeXX57VFfW1/K18LQVYcyDu2Q/zBG3cG/azTDXpXcpcMxTgmDMQVLtgFTMi47Icndmev5W106/5N5u7+c6GwRuBSCbZkcmMACR17WuN8irt/QqKQJtdgDkP4zu02HjV86WSGPQFCL76RnFzIdyts58q3hxFu3IIzU/WF8pJPuoW/u3s6Tn8aJdH1bMp6ZdaOMvzj6jZEvQ2l1Oyw+ChCYlsfFvcjkMStIBehX30/XxwcIw7U3FRz25nu3lqMEG18Q2wgzgK8cxEw58bD4MnApS66iJt7zvTMUggr0cerpEJxNXso63TdrwcH+rDjqdPR+CzJmBQs24luNrddOMoQecNEFZ1S6IoAEClVpVMrJNRWSi17LMtwv26zu2qVjkNSRpfud6AkCEidjMTnQ+v7ohHTWfC0GQrbWIQ5pSVRud7OHOPymlT03v6s0CBomzl5oSf0G09P0B8bEHXlzi5F4Q/tVkd+bPlh/RRn35uaPaJIhd3KA6dsRlvvM2zA1WWn6o4PLA2uErOC4msSeYxNDzC3hrMLR/I8RQVLR11VWXghOhEodT9fhb944p2qcIfEihffAA1T7oUvWaO7bGxlSszez6Fy6f4xxb9kH/yS7C5oxNyeIkad/njt9Uvf81P7K8eHbwPeKEdrzL8lkEsCLt/Ba6+k18YpzQv+ddJLWiBdLtuZ/IqJoxg+8mEs0ZgiT6dnMi+oA77hL0/i5ruNzSHDAH3WzkRelGcmaREb1M9P92oVLArqW5+hVPLaWAe0g1mG3vmd5tnT8kE7vcKPbtQNu13FS X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(396003)(136003)(376002)(451199015)(36840700001)(46966006)(40470700004)(41300700001)(2906002)(356005)(47076005)(186003)(83380400001)(26005)(2616005)(81166007)(82740400003)(5660300002)(426003)(1076003)(8936002)(82310400005)(8676002)(40460700003)(40480700001)(336012)(478600001)(70586007)(6666004)(4326008)(54906003)(70206006)(316002)(36756003)(6916009)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:11.7628 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0df10cb3-4e2d-421b-79bb-08dab3796c6e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5343 'unsigned long long' is defined as 64 bit across both aarch32 and aarch64. So, use 'ULL' for 64 bit word instead of UL which is 32 bits for aarch32. GICR_PENDBASER and GICR_PROPBASER both are 64 bit registers. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/gic_v3_defs.h | 16 ++++++++-------- xen/arch/arm/vgic-v3.c | 6 ++++-- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index 728e28d5e5..48a1bc401e 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -134,15 +134,15 @@ #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT 56 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ - (7UL << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT) + (7ULL << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT) #define GICR_PROPBASER_SHAREABILITY_SHIFT 10 #define GICR_PROPBASER_SHAREABILITY_MASK \ - (3UL << GICR_PROPBASER_SHAREABILITY_SHIFT) + (3ULL << GICR_PROPBASER_SHAREABILITY_SHIFT) #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT 7 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ - (7UL << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT) + (7ULL << GICR_PROPBASER_INNER_CACHEABILITY_SHIFT) #define GICR_PROPBASER_RES0_MASK \ - (GENMASK(63, 59) | GENMASK(55, 52) | GENMASK(6, 5)) + (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) #define GICR_PENDBASER_SHAREABILITY_SHIFT 10 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT 7 @@ -152,11 +152,11 @@ #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ (7UL << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT) #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ - (7UL << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT) -#define GICR_PENDBASER_PTZ BIT(62, UL) + (7ULL << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT) +#define GICR_PENDBASER_PTZ BIT(62, ULL) #define GICR_PENDBASER_RES0_MASK \ - (BIT(63, UL) | GENMASK(61, 59) | GENMASK(55, 52) | \ - GENMASK(15, 12) | GENMASK(6, 0)) + (BIT(63, ULL) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ + GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) #define DEFAULT_PMR_VALUE 0xff diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index d86b41a39f..9f31360f56 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -254,14 +254,16 @@ static int __vgic_v3_rdistr_rd_mmio_read(struct vcpu *v, mmio_info_t *info, case VREG64(GICR_PENDBASER): { unsigned long flags; + uint64_t value; if ( !v->domain->arch.vgic.has_its ) goto read_as_zero_64; if ( !vgic_reg64_check_access(dabt) ) goto bad_width; spin_lock_irqsave(&v->arch.vgic.lock, flags); - *r = vreg_reg64_extract(v->arch.vgic.rdist_pendbase, info); - *r &= ~GICR_PENDBASER_PTZ; /* WO, reads as 0 */ + value = v->arch.vgic.rdist_pendbase; + value &= ~GICR_PENDBASER_PTZ; /* WO, reads as 0 */ + *r = vreg_reg64_extract(value, info); spin_unlock_irqrestore(&v->arch.vgic.lock, flags); return 1; } From patchwork Fri Oct 21 15:31:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13014964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47451C433FE for ; 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bh=qLgWVOt1DQu03UMiS7oEpaPHJ6p9hu7nypVok0V2YKI=; b=CqaEY6X15ctal43GnekMmBOuPCw/Zq1DAGH0wIqoQs6LvRocH3YdiPcJCVajo5uw/cOWFxECRlsLoc4ps5Pq8jXOAuymG0jaz/9lFL7OlhhhecleuZ9ZcCui42HG9kXVVaUOGWdFm56ZBb9sLz0XQ3vTy6iX5hqm6OnaCGGKTbc= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 06/12] Arm: GICv3: Emulate of ICC_SGI1R on AArch32 Date: Fri, 21 Oct 2022 16:31:22 +0100 Message-ID: <20221021153128.44226-7-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EF:EE_|CY5PR12MB6180:EE_ X-MS-Office365-Filtering-Correlation-Id: d8b442ed-71db-4171-2304-08dab3796e26 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:14.5660 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8b442ed-71db-4171-2304-08dab3796e26 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6180 Refer Arm IHI 0069H ID020922, 12.5.23, ICC_SGI1R is a 64 bit register on Aarch32 systems. Thus, the prototype needs to change to reflect this. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/vgic-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 9f31360f56..48e8ef95d2 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1482,7 +1482,7 @@ write_reserved: return 1; } -static bool vgic_v3_to_sgi(struct vcpu *v, register_t sgir) +static bool vgic_v3_to_sgi(struct vcpu *v, uint64_t sgir) { int virq; int irqmode; From patchwork Fri Oct 21 15:31:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13014966 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 834BEFA373D for ; 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bh=tmDx4afjf7Hk3KdCSZeZ9Tvo7rmO4RVpxVthRWoG+NA=; b=YxqWZlkByLXfOZqz/gaRBgS0MJldkNvzfoX7L/sNCkJC1nmZTw4reb1568LFstDNYJ6XPAsP9C1hI+QDgLBgNEEE71JZGznygDDYSPAGqgJmLrsMe+BsOQ1rS1idzAq9N3gqVCZTOcqjhwG6L0pw03/rfdGCI5I7yeoQFupze94= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 07/12] Arm: GICv3: Emulate ICH_LR_EL2 on AArch32 Date: Fri, 21 Oct 2022 16:31:23 +0100 Message-ID: <20221021153128.44226-8-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EA:EE_|CH2PR12MB5514:EE_ X-MS-Office365-Filtering-Correlation-Id: 656ac450-729b-4212-7b4b-08dab37971b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:20.4267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 656ac450-729b-4212-7b4b-08dab37971b7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB5514 Refer "Arm IHI 0069H ID020922", 12.4.6, Interrupt Controller List Registers AArch64 System register ICH_LR_EL2 bits [31:0] are architecturally mapped to AArch32 System register ICH_LR[31:0]. AArch64 System register ICH_LR_EL2 bits [63:32] are architecturally mapped to AArch32 System register ICH_LRC[31:0]. Defined ICH_LR<0...15>_EL2 and ICH_LRC<0...15>_EL2 for Aarch32. For AArch32, the link register is stored as :- (((uint64_t) ICH_LRC<0...15>_EL2) << 32) | ICH_LR<0...15>_EL2 Also, ICR_LR macros need to be modified as ULL is 64 bits for AArch32 and AArch64. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/gic-v3.c | 132 +++++++++++------------ xen/arch/arm/include/asm/arm32/sysregs.h | 52 +++++++++ xen/arch/arm/include/asm/arm64/sysregs.h | 7 +- xen/arch/arm/include/asm/gic_v3_defs.h | 6 +- 4 files changed, 126 insertions(+), 71 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 018fa0dfa0..8b4b168e78 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -73,37 +73,37 @@ static inline void gicv3_save_lrs(struct vcpu *v) switch ( gicv3_info.nr_lrs ) { case 16: - v->arch.gic.v3.lr[15] = READ_SYSREG(ICH_LR15_EL2); + v->arch.gic.v3.lr[15] = READ_SYSREG_LR(15); case 15: - v->arch.gic.v3.lr[14] = READ_SYSREG(ICH_LR14_EL2); + v->arch.gic.v3.lr[14] = READ_SYSREG_LR(14); case 14: - v->arch.gic.v3.lr[13] = READ_SYSREG(ICH_LR13_EL2); + v->arch.gic.v3.lr[13] = READ_SYSREG_LR(13); case 13: - v->arch.gic.v3.lr[12] = READ_SYSREG(ICH_LR12_EL2); + v->arch.gic.v3.lr[12] = READ_SYSREG_LR(12); case 12: - v->arch.gic.v3.lr[11] = READ_SYSREG(ICH_LR11_EL2); + v->arch.gic.v3.lr[11] = READ_SYSREG_LR(11); case 11: - v->arch.gic.v3.lr[10] = READ_SYSREG(ICH_LR10_EL2); + v->arch.gic.v3.lr[10] = READ_SYSREG_LR(10); case 10: - v->arch.gic.v3.lr[9] = READ_SYSREG(ICH_LR9_EL2); + v->arch.gic.v3.lr[9] = READ_SYSREG_LR(9); case 9: - v->arch.gic.v3.lr[8] = READ_SYSREG(ICH_LR8_EL2); + v->arch.gic.v3.lr[8] = READ_SYSREG_LR(8); case 8: - v->arch.gic.v3.lr[7] = READ_SYSREG(ICH_LR7_EL2); + v->arch.gic.v3.lr[7] = READ_SYSREG_LR(7); case 7: - v->arch.gic.v3.lr[6] = READ_SYSREG(ICH_LR6_EL2); + v->arch.gic.v3.lr[6] = READ_SYSREG_LR(6); case 6: - v->arch.gic.v3.lr[5] = READ_SYSREG(ICH_LR5_EL2); + v->arch.gic.v3.lr[5] = READ_SYSREG_LR(5); case 5: - v->arch.gic.v3.lr[4] = READ_SYSREG(ICH_LR4_EL2); + v->arch.gic.v3.lr[4] = READ_SYSREG_LR(4); case 4: - v->arch.gic.v3.lr[3] = READ_SYSREG(ICH_LR3_EL2); + v->arch.gic.v3.lr[3] = READ_SYSREG_LR(3); case 3: - v->arch.gic.v3.lr[2] = READ_SYSREG(ICH_LR2_EL2); + v->arch.gic.v3.lr[2] = READ_SYSREG_LR(2); case 2: - v->arch.gic.v3.lr[1] = READ_SYSREG(ICH_LR1_EL2); + v->arch.gic.v3.lr[1] = READ_SYSREG_LR(1); case 1: - v->arch.gic.v3.lr[0] = READ_SYSREG(ICH_LR0_EL2); + v->arch.gic.v3.lr[0] = READ_SYSREG_LR(0); break; default: BUG(); @@ -120,37 +120,37 @@ static inline void gicv3_restore_lrs(const struct vcpu *v) switch ( gicv3_info.nr_lrs ) { case 16: - WRITE_SYSREG(v->arch.gic.v3.lr[15], ICH_LR15_EL2); + WRITE_SYSREG_LR(15, v->arch.gic.v3.lr[15]); case 15: - WRITE_SYSREG(v->arch.gic.v3.lr[14], ICH_LR14_EL2); + WRITE_SYSREG_LR(14, v->arch.gic.v3.lr[14]); case 14: - WRITE_SYSREG(v->arch.gic.v3.lr[13], ICH_LR13_EL2); + WRITE_SYSREG_LR(13, v->arch.gic.v3.lr[13]); case 13: - WRITE_SYSREG(v->arch.gic.v3.lr[12], ICH_LR12_EL2); + WRITE_SYSREG_LR(12, v->arch.gic.v3.lr[12]); case 12: - WRITE_SYSREG(v->arch.gic.v3.lr[11], ICH_LR11_EL2); + WRITE_SYSREG_LR(11, v->arch.gic.v3.lr[11]); case 11: - WRITE_SYSREG(v->arch.gic.v3.lr[10], ICH_LR10_EL2); + WRITE_SYSREG_LR(10, v->arch.gic.v3.lr[10]); case 10: - WRITE_SYSREG(v->arch.gic.v3.lr[9], ICH_LR9_EL2); + WRITE_SYSREG_LR(9, v->arch.gic.v3.lr[9]); case 9: - WRITE_SYSREG(v->arch.gic.v3.lr[8], ICH_LR8_EL2); + WRITE_SYSREG_LR(8, v->arch.gic.v3.lr[8]); case 8: - WRITE_SYSREG(v->arch.gic.v3.lr[7], ICH_LR7_EL2); + WRITE_SYSREG_LR(7, v->arch.gic.v3.lr[7]); case 7: - WRITE_SYSREG(v->arch.gic.v3.lr[6], ICH_LR6_EL2); + WRITE_SYSREG_LR(6, v->arch.gic.v3.lr[6]); case 6: - WRITE_SYSREG(v->arch.gic.v3.lr[5], ICH_LR5_EL2); + WRITE_SYSREG_LR(5, v->arch.gic.v3.lr[5]); case 5: - WRITE_SYSREG(v->arch.gic.v3.lr[4], ICH_LR4_EL2); + WRITE_SYSREG_LR(4, v->arch.gic.v3.lr[4]); case 4: - WRITE_SYSREG(v->arch.gic.v3.lr[3], ICH_LR3_EL2); + WRITE_SYSREG_LR(3, v->arch.gic.v3.lr[3]); case 3: - WRITE_SYSREG(v->arch.gic.v3.lr[2], ICH_LR2_EL2); + WRITE_SYSREG_LR(2, v->arch.gic.v3.lr[2]); case 2: - WRITE_SYSREG(v->arch.gic.v3.lr[1], ICH_LR1_EL2); + WRITE_SYSREG_LR(1, v->arch.gic.v3.lr[1]); case 1: - WRITE_SYSREG(v->arch.gic.v3.lr[0], ICH_LR0_EL2); + WRITE_SYSREG_LR(0, v->arch.gic.v3.lr[0]); break; default: BUG(); @@ -161,22 +161,22 @@ static uint64_t gicv3_ich_read_lr(int lr) { switch ( lr ) { - case 0: return READ_SYSREG(ICH_LR0_EL2); - case 1: return READ_SYSREG(ICH_LR1_EL2); - case 2: return READ_SYSREG(ICH_LR2_EL2); - case 3: return READ_SYSREG(ICH_LR3_EL2); - case 4: return READ_SYSREG(ICH_LR4_EL2); - case 5: return READ_SYSREG(ICH_LR5_EL2); - case 6: return READ_SYSREG(ICH_LR6_EL2); - case 7: return READ_SYSREG(ICH_LR7_EL2); - case 8: return READ_SYSREG(ICH_LR8_EL2); - case 9: return READ_SYSREG(ICH_LR9_EL2); - case 10: return READ_SYSREG(ICH_LR10_EL2); - case 11: return READ_SYSREG(ICH_LR11_EL2); - case 12: return READ_SYSREG(ICH_LR12_EL2); - case 13: return READ_SYSREG(ICH_LR13_EL2); - case 14: return READ_SYSREG(ICH_LR14_EL2); - case 15: return READ_SYSREG(ICH_LR15_EL2); + case 0: return READ_SYSREG_LR(0); + case 1: return READ_SYSREG_LR(1); + case 2: return READ_SYSREG_LR(2); + case 3: return READ_SYSREG_LR(3); + case 4: return READ_SYSREG_LR(4); + case 5: return READ_SYSREG_LR(5); + case 6: return READ_SYSREG_LR(6); + case 7: return READ_SYSREG_LR(7); + case 8: return READ_SYSREG_LR(8); + case 9: return READ_SYSREG_LR(9); + case 10: return READ_SYSREG_LR(10); + case 11: return READ_SYSREG_LR(11); + case 12: return READ_SYSREG_LR(12); + case 13: return READ_SYSREG_LR(13); + case 14: return READ_SYSREG_LR(14); + case 15: return READ_SYSREG_LR(15); default: BUG(); } @@ -187,52 +187,52 @@ static void gicv3_ich_write_lr(int lr, uint64_t val) switch ( lr ) { case 0: - WRITE_SYSREG(val, ICH_LR0_EL2); + WRITE_SYSREG_LR(0, val); break; case 1: - WRITE_SYSREG(val, ICH_LR1_EL2); + WRITE_SYSREG_LR(1, val); break; case 2: - WRITE_SYSREG(val, ICH_LR2_EL2); + WRITE_SYSREG_LR(2, val); break; case 3: - WRITE_SYSREG(val, ICH_LR3_EL2); + WRITE_SYSREG_LR(3, val); break; case 4: - WRITE_SYSREG(val, ICH_LR4_EL2); + WRITE_SYSREG_LR(4, val); break; case 5: - WRITE_SYSREG(val, ICH_LR5_EL2); + WRITE_SYSREG_LR(5, val); break; case 6: - WRITE_SYSREG(val, ICH_LR6_EL2); + WRITE_SYSREG_LR(6, val); break; case 7: - WRITE_SYSREG(val, ICH_LR7_EL2); + WRITE_SYSREG_LR(7, val); break; case 8: - WRITE_SYSREG(val, ICH_LR8_EL2); + WRITE_SYSREG_LR(8, val); break; case 9: - WRITE_SYSREG(val, ICH_LR9_EL2); + WRITE_SYSREG_LR(9, val); break; case 10: - WRITE_SYSREG(val, ICH_LR10_EL2); + WRITE_SYSREG_LR(10, val); break; case 11: - WRITE_SYSREG(val, ICH_LR11_EL2); + WRITE_SYSREG_LR(11, val); break; case 12: - WRITE_SYSREG(val, ICH_LR12_EL2); + WRITE_SYSREG_LR(12, val); break; case 13: - WRITE_SYSREG(val, ICH_LR13_EL2); + WRITE_SYSREG_LR(13, val); break; case 14: - WRITE_SYSREG(val, ICH_LR14_EL2); + WRITE_SYSREG_LR(14, val); break; case 15: - WRITE_SYSREG(val, ICH_LR15_EL2); + WRITE_SYSREG_LR(15, val); break; default: return; @@ -417,12 +417,12 @@ static void gicv3_dump_state(const struct vcpu *v) if ( v == current ) { for ( i = 0; i < gicv3_info.nr_lrs; i++ ) - printk(" HW_LR[%d]=%lx\n", i, gicv3_ich_read_lr(i)); + printk(" HW_LR[%d]=%llx\n", i, gicv3_ich_read_lr(i)); } else { for ( i = 0; i < gicv3_info.nr_lrs; i++ ) - printk(" VCPU_LR[%d]=%lx\n", i, v->arch.gic.v3.lr[i]); + printk(" VCPU_LR[%d]=%llx\n", i, v->arch.gic.v3.lr[i]); } } diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/include/asm/arm32/sysregs.h index 6841d5de43..f3b4dfbca8 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -62,9 +62,61 @@ #define READ_SYSREG(R...) READ_SYSREG32(R) #define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) +#define ICH_LR_REG(INDEX) ICH_LR ## INDEX ## _EL2 +#define ICH_LRC_REG(INDEX) ICH_LRC ## INDEX ## _EL2 + +#define READ_SYSREG_LR(INDEX) ((((uint64_t) \ + (READ_SYSREG(ICH_LRC_REG(INDEX)))) << 32) | \ + (READ_SYSREG(ICH_LR_REG(INDEX)))) + +#define WRITE_SYSREG_LR(INDEX, V) WRITE_SYSREG \ + (V&0xFFFFFFFF, ICH_LR_REG(INDEX)); \ + WRITE_SYSREG(V>>32, ICH_LRC_REG(INDEX)); + /* MVFR2 is not defined on ARMv7 */ #define MVFR2_MAYBE_UNDEFINED +#define ___CP32(a,b,c,d,e) a,b,c,d,e +#define __LR0_EL2(x) ___CP32(p15,4,c12,c12,x) +#define __LR8_EL2(x) ___CP32(p15,4,c12,c13,x) + +#define __LRC0_EL2(x) ___CP32(p15,4,c12,c14,x) +#define __LRC8_EL2(x) ___CP32(p15,4,c12,c15,x) + +#define ICH_LR0_EL2 __LR0_EL2(0) +#define ICH_LR1_EL2 __LR0_EL2(1) +#define ICH_LR2_EL2 __LR0_EL2(2) +#define ICH_LR3_EL2 __LR0_EL2(3) +#define ICH_LR4_EL2 __LR0_EL2(4) +#define ICH_LR5_EL2 __LR0_EL2(5) +#define ICH_LR6_EL2 __LR0_EL2(6) +#define ICH_LR7_EL2 __LR0_EL2(7) +#define ICH_LR8_EL2 __LR8_EL2(0) +#define ICH_LR9_EL2 __LR8_EL2(1) +#define ICH_LR10_EL2 __LR8_EL2(2) +#define ICH_LR11_EL2 __LR8_EL2(3) +#define ICH_LR12_EL2 __LR8_EL2(4) +#define ICH_LR13_EL2 __LR8_EL2(5) +#define ICH_LR14_EL2 __LR8_EL2(6) +#define ICH_LR15_EL2 __LR8_EL2(7) + +#define ICH_LRC0_EL2 __LRC0_EL2(0) +#define ICH_LRC1_EL2 __LRC0_EL2(1) +#define ICH_LRC2_EL2 __LRC0_EL2(2) +#define ICH_LRC3_EL2 __LRC0_EL2(3) +#define ICH_LRC4_EL2 __LRC0_EL2(4) +#define ICH_LRC5_EL2 __LRC0_EL2(5) +#define ICH_LRC6_EL2 __LRC0_EL2(6) +#define ICH_LRC7_EL2 __LRC0_EL2(7) +#define ICH_LRC8_EL2 __LRC8_EL2(0) +#define ICH_LRC9_EL2 __LRC8_EL2(1) +#define ICH_LRC10_EL2 __LRC8_EL2(2) +#define ICH_LRC11_EL2 __LRC8_EL2(3) +#define ICH_LRC12_EL2 __LRC8_EL2(4) +#define ICH_LRC13_EL2 __LRC8_EL2(5) +#define ICH_LRC14_EL2 __LRC8_EL2(6) +#define ICH_LRC15_EL2 __LRC8_EL2(7) + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM32_SYSREGS_H */ diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index 54670084c3..d45fe815f9 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -469,8 +469,11 @@ asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ _r; }) -#define READ_SYSREG(name) READ_SYSREG64(name) -#define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) +#define READ_SYSREG(name) READ_SYSREG64(name) +#define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) +#define ICH_LR_REG(index) ICH_LR ## index ## _EL2 +#define WRITE_SYSREG_LR(index, v) WRITE_SYSREG(v, ICH_LR_REG(index)) +#define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) #endif /* _ASM_ARM_ARM64_SYSREGS_H */ diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index 48a1bc401e..87115f8b25 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -185,9 +185,9 @@ #define ICH_LR_HW_SHIFT 61 #define ICH_LR_GRP_MASK 0x1 #define ICH_LR_GRP_SHIFT 60 -#define ICH_LR_MAINTENANCE_IRQ (1UL<<41) -#define ICH_LR_GRP1 (1UL<<60) -#define ICH_LR_HW (1UL<<61) +#define ICH_LR_MAINTENANCE_IRQ (1ULL<<41) +#define ICH_LR_GRP1 (1ULL<<60) +#define ICH_LR_HW (1ULL<<61) #define ICH_VTR_NRLRGS 0x3f #define ICH_VTR_PRIBITS_MASK 0x7 From patchwork Fri Oct 21 15:31:24 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 08/12] Arm: GICv3: Define ICH_AP0R and ICH_AP1R for AArch32 Date: Fri, 21 Oct 2022 16:31:24 +0100 Message-ID: <20221021153128.44226-9-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8E8:EE_|SA3PR12MB7951:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e145c3d-9219-480a-45fa-08dab379773b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7FJqjnSe0FzfMuExIrH0jTmtfI6ezT4GfiHPDzOw43WDaVDM+n95anoMVTObwx+71lD67NYYhCfnVnSaFOJ1LHtVAufuAJOZaBFfZiwUZhqsJHF3GjrIl4CdCtYssHVRfvHjBRcnf/DkaPU3DMODiou61fHXxTPE+GA9WYk37ZaIKpQBYCD0U+z2/mUjzOn23U16eeY5q4F/wyzfKwQi8SRl6jvfT0wHBYtwAuLh8f/jKWPxPhaXxXmmhTiRjJF/knD9K/0f4Vg4J+JGZyTQ+T5c9YtoL3DeBH5ztE6E4UHmDfYG2dMtx+V+iM4KGummnUwnipzMxyn5Kke4V20aQBtQwo4ewfgJIAIUgglmtX9KCGQ1NjzIAj7rf71FJ7a/TixF6xrQhhuYVpSHSTavMQOWwSLFoOqGAPa4xyxYOMd97cR7Yl4yLz0/TzIzb72Dsf5TSqodMWaOlAxeKz/0nLo39O/qjBj50vhU73UOCfYzpa5SZnl14MPLgpQDhiAezxVHEjzL3ONF1GYmZLkQpyNW1NsV0FbJQliDUhPPY5h1RynsNsIOA+1aSJ5D8R/sCYzWrtfaPF6muohdtzwu5x4vv1pP7tyQxhpyD+s/gI9L0mYV3nSYCWXPnN/mf3IMSJ6NZ0d7eOw0xtCaS9KSAghBzEwtlJ8J6aOkFgo6B5NBNRLAJN4FGeN4WO2m6jnFWuevckHDU+9S39+IZF+OKAUBPG3XhZrzGHi+jAv5N60yJ3SRzr9m3QhF01igefCVT/ej2jcQO2Dj7W+diNylGRdSVS3LFuDNd9X6lvXQGPLOCvmSX6rRNhxXyG1AD8B5 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(346002)(39860400002)(396003)(136003)(451199015)(36840700001)(46966006)(40470700004)(2906002)(478600001)(81166007)(1076003)(186003)(82740400003)(40460700003)(356005)(6916009)(316002)(36756003)(8676002)(41300700001)(54906003)(4326008)(82310400005)(70586007)(70206006)(5660300002)(8936002)(2616005)(36860700001)(336012)(47076005)(426003)(40480700001)(26005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:29.6165 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e145c3d-9219-480a-45fa-08dab379773b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7951 Refer "Arm IHI 0069H ID020922", 12.7.1 - Interrupt Controller Hyp Active Priorities Group0 Registers 0-3 12.7.2 - Interrupt Controller Hyp Active Priorities Group1 Registers 0-3 Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/arm32/sysregs.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/include/asm/arm32/sysregs.h index f3b4dfbca8..693da22324 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -117,6 +117,18 @@ #define ICH_LRC14_EL2 __LRC8_EL2(6) #define ICH_LRC15_EL2 __LRC8_EL2(7) +#define __AP0Rx_EL2(x) ___CP32(p15,4,c12,c8,x) +#define ICH_AP0R0_EL2 __AP0Rx_EL2(0) +#define ICH_AP0R1_EL2 __AP0Rx_EL2(1) +#define ICH_AP0R2_EL2 __AP0Rx_EL2(2) +#define ICH_AP0R3_EL2 __AP0Rx_EL2(3) + +#define __AP1Rx_EL2(x) ___CP32(p15,4,c12,c9,x) +#define ICH_AP1R0_EL2 __AP1Rx_EL2(0) +#define ICH_AP1R1_EL2 __AP1Rx_EL2(1) +#define ICH_AP1R2_EL2 __AP1Rx_EL2(2) +#define ICH_AP1R3_EL2 __AP1Rx_EL2(3) + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM32_SYSREGS_H */ From patchwork Fri Oct 21 15:31:25 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 09/12] Arm: GICv3: Define GIC registers for AArch32 Date: Fri, 21 Oct 2022 16:31:25 +0100 Message-ID: <20221021153128.44226-10-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT116:EE_|MN0PR12MB6320:EE_ X-MS-Office365-Filtering-Correlation-Id: bae72055-30f9-40eb-2721-08dab37976d0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SrPB+O+VX9a7l+kIZegZ2CrKSovbvs5vQk6h4soiDC95vnGM9OGLDpt4uGZcGT1V4qXNEBcsNWE++NaUq01sj3Ms9XYzs7Mr1VQDJhBCyLmrv+Ru6K4znVvH3sqpcyUWZODaxdEpBn2BJezDil+KpN2ZDG2xOqjWI5cMWK7HDaGdaTr9OPa7hyuM59qfAzMlzq7hVKWYK6nf2JB9yD1nMZeUuzJmvLe/xUkELYdMdvMVisHO3rfLkGrHKknUjHOd4u34DndP+UyyZJMbwSLKWRDYhV15PCXgMhMRK5Gq+ffau4feRsINCuJyeDeds6zGbS/U/sH679EPc8o1SCCcO/nwPnwetRFpaUQas489Yfppx9SZHI7jHMABpFzivyvJuiBVsyXp13tnpHFt3o8Br3yKcVa6xDrZvBbnq9vz6glljR8tqzRRU4sPLLXLtmVRZDZkja3iYQp1ErITMvNStfDKmf8h3xNoOKyG+rqoaFtTvBmrdTA5CKoqjHIYAH45tdhRuf33PVg8bcf/ZXQrZLA08K078kfVszjoO+/2V5ATfeFGdwvAGPrBea+vpMIblfcxQ6p/0uAf2nNNvTtBlvvHVJodtrPQRWPY1jnUdiod1Djngfq32GeOpQQ/Cm2qXNh1EyICe/NWeVo9aw01dZsL5NaO3eUOe5GMmAJg8RJuCg8axBPKFKyTewz/bcrRdRMIHbZI1jl6EVhtBS09HAQklwZ9rO0TN8CTvg1daohuWV/4zE0qolQxE1HTTo1MBtFQgwtSarv28L/87Hi1Uf+8RJpPfmExB8elIE4roK1TBwKxErsA3idRy47CTgHv X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(376002)(136003)(396003)(451199015)(36840700001)(46966006)(40470700004)(478600001)(41300700001)(316002)(4326008)(54906003)(8936002)(6916009)(8676002)(70206006)(70586007)(36860700001)(47076005)(40480700001)(356005)(81166007)(186003)(82740400003)(1076003)(2616005)(40460700003)(426003)(26005)(82310400005)(83380400001)(336012)(36756003)(2906002)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:29.1645 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bae72055-30f9-40eb-2721-08dab37976d0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT116.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6320 Refer "Arm IHI 0069H ID020922" 12.5.23 ICC_SGI1R, Interrupt Controller Software Generated Interrupt Group 1 Register 12.5.12 ICC_HSRE, Interrupt Controller Hyp System Register Enable register 12.7.10 ICH_VTR, Interrupt Controller VGIC Type Register 12.7.5 ICH_HCR, Interrupt Controller Hyp Control Register 12.5.20 ICC_PMR, Interrupt Controller Interrupt Priority Mask Register 12.5.24 ICC_SRE, Interrupt Controller System Register Enable register 12.5.7 ICC_DIR, Interrupt Controller Deactivate Interrupt Register 12.5.9 ICC_EOIR1, Interrupt Controller End Of Interrupt Register 1 12.5.14 ICC_IAR1, Interrupt Controller Interrupt Acknowledge Register 1 12.5.5 ICC_BPR1, Interrupt Controller Binary Point Register 1 12.5.6 ICC_CTLR, Interrupt Controller Control Register 12.5.16 ICC_IGRPEN1, Interrupt Controller Interrupt Group 1 Enable register 12.7.9 ICH_VMCR, Interrupt Controller Virtual Machine Control Register Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/arm32/sysregs.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/xen/arch/arm/include/asm/arm32/sysregs.h b/xen/arch/arm/include/asm/arm32/sysregs.h index 693da22324..d2c5a115f9 100644 --- a/xen/arch/arm/include/asm/arm32/sysregs.h +++ b/xen/arch/arm/include/asm/arm32/sysregs.h @@ -129,6 +129,22 @@ #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) +#define ICC_SGI1R_EL1 p15,0,c12 + +#define ICC_SRE_EL2 p15,4,c12,c9,5 +#define ICH_VTR_EL2 p15,4,c12,c11,1 +#define ICH_HCR_EL2 p15,4,c12,c11,0 + +#define ICC_PMR_EL1 p15,0,c4,c6,0 +#define ICC_SRE_EL1 p15,0,c12,c12,5 +#define ICC_DIR_EL1 p15,0,c12,c11,1 +#define ICC_EOIR1_EL1 p15,0,c12,c12,1 +#define ICC_IAR1_EL1 p15,0,c12,c12,0 +#define ICC_BPR1_EL1 p15,0,c12,c12,3 +#define ICC_CTLR_EL1 p15,0,c12,c12,4 +#define ICC_IGRPEN1_EL1 p15,0,c12,c12,7 +#define ICH_VMCR_EL2 p15,4,c12,c11,7 + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM32_SYSREGS_H */ From patchwork Fri Oct 21 15:31:26 2022 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 10/12] Arm: GICv3: Use ULL instead of UL for 64bits Date: Fri, 21 Oct 2022 16:31:26 +0100 Message-ID: <20221021153128.44226-11-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT113:EE_|LV2PR12MB5918:EE_ X-MS-Office365-Filtering-Correlation-Id: 2ee603b3-888e-414e-b599-08dab379790d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NMQxIhQKx73s8kdC3DZ7VaYVPnLcgQz6jk0QIrAVKDOs53IXcDE6hM4E8i0fIXteDSHo5dNcV6cGWFWkKYqICaxD4dVeRh53B/tL8eWChw9SR3s5Y+IEnvWCw0NNnWgkBddGajx+i6/c4ySxd0/w5e2TtRYvgG4AmLEBhL3NER95b/KipVJCBj1CFqBaDCpyGIYSVPfDKZygxGtd+KLh8LwbNhcTjqnQbTf3pWiU7ixy72c4v8OovmpWQwkeJg+zTVQgWwWC2xAX+ldK/kZ39o1qfainAVDzodZ/aDIiAiw/weH0+4z+9UpF0T3nCpBHil9X+k3HW89w+h0p89/egovMoqBXuDkRIHGziGNDTB7hOkxmv/cTR46F09V8veq7BLaSwZEJB1v874RRFHWfxBPxiPkFBRVmYlBTdOxjT/DrUUBBNtw5vZmOW/0LVup24mf/6XoLv1Q2YCxcsSw1PsD9sMF4d9jIM6pBboQ+dTWNya50Rzjav5U1MOlv1k0gUAgB4PyOGKAon2QgbTbqWi/v4Vys94vja/8pp1lRrowdVNEg98lN3emEstq9GMM2wgfFPbTnUkWPc2gqOVIFGMgBZlMYyQvZSHXqaiIiyDAd6/v+OEbt/cTqbWrLA9+VEiYZrbR/Vt4H/YEzZ5fOMoOem01x34atv/CqCSkJNVKjeOrHnoVRxBP3VZ6Tbf0fYzN0L8IpqV+LMJCxKd16S0ppChTz56P+iu49E/MyN9lXkHlPTHpYj9XGJzuVU9ByYJCL9nHxEv1mB1+QdlpFNA2wQgATua5jtIDSqAEK5BE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(136003)(39860400002)(376002)(451199015)(36840700001)(40470700004)(46966006)(4326008)(2906002)(336012)(8936002)(41300700001)(186003)(40460700003)(1076003)(5660300002)(6666004)(36756003)(26005)(478600001)(426003)(2616005)(47076005)(8676002)(70206006)(70586007)(356005)(83380400001)(81166007)(82310400005)(316002)(82740400003)(6916009)(54906003)(36860700001)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:32.9390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ee603b3-888e-414e-b599-08dab379790d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT113.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5918 "unsigned long long" is defined as 64 bits on AArch64 and AArch32 Thus, one should this instead of "unsigned long" which is 32 bits on AArch32. Also use 'PRIu64' instead of 'lx' to print uint64_t. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/gic-v3-its.c | 20 ++++++++++---------- xen/arch/arm/gic-v3-lpi.c | 8 ++++---- xen/arch/arm/gic-v3.c | 4 ++-- xen/arch/arm/include/asm/gic_v3_defs.h | 2 +- xen/arch/arm/include/asm/gic_v3_its.h | 2 +- xen/arch/arm/vgic-v3-its.c | 17 +++++++++-------- 6 files changed, 27 insertions(+), 26 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index e217c21bf8..dd056a3140 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -163,7 +163,7 @@ static int gicv3_its_wait_commands(struct host_its *hw_its) static uint64_t encode_rdbase(struct host_its *hw_its, unsigned int cpu, uint64_t reg) { - reg &= ~GENMASK(51, 16); + reg &= ~GENMASK_ULL(51, 16); reg |= gicv3_get_redist_address(cpu, hw_its->flags & HOST_ITS_USES_PTA); @@ -219,7 +219,7 @@ static int its_send_cmd_mapd(struct host_its *its, uint32_t deviceid, { ASSERT(size_bits <= its->evid_bits); ASSERT(size_bits > 0); - ASSERT(!(itt_addr & ~GENMASK(51, 8))); + ASSERT(!(itt_addr & ~GENMASK_ULL(51, 8))); /* The number of events is encoded as "number of bits minus one". */ size_bits--; @@ -273,9 +273,9 @@ int gicv3_its_setup_collection(unsigned int cpu) #define BASER_ATTR_MASK \ ((0x3UL << GITS_BASER_SHAREABILITY_SHIFT) | \ - (0x7UL << GITS_BASER_OUTER_CACHEABILITY_SHIFT) | \ - (0x7UL << GITS_BASER_INNER_CACHEABILITY_SHIFT)) -#define BASER_RO_MASK (GENMASK(58, 56) | GENMASK(52, 48)) + (0x7ULL << GITS_BASER_OUTER_CACHEABILITY_SHIFT) | \ + (0x7ULL << GITS_BASER_INNER_CACHEABILITY_SHIFT)) +#define BASER_RO_MASK (GENMASK_ULL(58, 56) | GENMASK_ULL(52, 48)) /* Check that the physical address can be encoded in the PROPBASER register. */ static bool check_baser_phys_addr(void *vaddr, unsigned int page_bits) @@ -287,13 +287,13 @@ static bool check_baser_phys_addr(void *vaddr, unsigned int page_bits) static uint64_t encode_baser_phys_addr(paddr_t addr, unsigned int page_bits) { - uint64_t ret = addr & GENMASK(47, page_bits); + uint64_t ret = addr & GENMASK_ULL(47, page_bits); if ( page_bits < 16 ) return ret; /* For 64K pages address bits 51-48 are encoded in bits 15-12. */ - return ret | ((addr & GENMASK(51, 48)) >> (48 - 12)); + return ret | ((addr & GENMASK_ULL(51, 48)) >> (48 - 12)); } static void *its_map_cbaser(struct host_its *its) @@ -310,7 +310,7 @@ static void *its_map_cbaser(struct host_its *its) if ( !buffer ) return NULL; - if ( virt_to_maddr(buffer) & ~GENMASK(51, 12) ) + if ( virt_to_maddr(buffer) & ~GENMASK_ULL(51, 12) ) { xfree(buffer); return NULL; @@ -446,7 +446,7 @@ static int gicv3_disable_its(struct host_its *hw_its) udelay(1); } while ( NOW() <= deadline ); - printk(XENLOG_ERR "ITS@%lx not quiescent.\n", hw_its->addr); + printk(XENLOG_ERR "ITS@%" PRIu64 " not quiescent.\n", hw_its->addr); return -ETIMEDOUT; } @@ -999,7 +999,7 @@ static void add_to_host_its_list(paddr_t addr, paddr_t size, its_data->size = size; its_data->dt_node = node; - printk("GICv3: Found ITS @0x%lx\n", addr); + printk("GICv3: Found ITS 0x%" PRIu64 "\n", addr); list_add_tail(&its_data->entry, &host_its_list); } diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index 61d90eb386..9ca74bc321 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -134,7 +134,7 @@ void gicv3_set_redist_address(paddr_t address, unsigned int redist_id) uint64_t gicv3_get_redist_address(unsigned int cpu, bool use_pta) { if ( use_pta ) - return per_cpu(lpi_redist, cpu).redist_addr & GENMASK(51, 16); + return per_cpu(lpi_redist, cpu).redist_addr & GENMASK_ULL(51, 16); else return per_cpu(lpi_redist, cpu).redist_id << 16; } @@ -253,7 +253,7 @@ static int gicv3_lpi_allocate_pendtable(unsigned int cpu) return -ENOMEM; /* Make sure the physical address can be encoded in the register. */ - if ( virt_to_maddr(pendtable) & ~GENMASK(51, 16) ) + if ( virt_to_maddr(pendtable) & ~GENMASK_ULL(51, 16) ) { xfree(pendtable); return -ERANGE; @@ -281,7 +281,7 @@ static int gicv3_lpi_set_pendtable(void __iomem *rdist_base) return -ENOMEM; } - ASSERT(!(virt_to_maddr(pendtable) & ~GENMASK(51, 16))); + ASSERT(!(virt_to_maddr(pendtable) & ~GENMASK_ULL(51, 16))); val = GIC_BASER_CACHE_RaWaWb << GICR_PENDBASER_INNER_CACHEABILITY_SHIFT; val |= GIC_BASER_CACHE_SameAsInner << GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT; @@ -329,7 +329,7 @@ static int gicv3_lpi_set_proptable(void __iomem * rdist_base) return -ENOMEM; /* Make sure the physical address can be encoded in the register. */ - if ( (virt_to_maddr(table) & ~GENMASK(51, 12)) ) + if ( (virt_to_maddr(table) & ~GENMASK_ULL(51, 12)) ) { xfree(table); return -ERANGE; diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 8b4b168e78..35eaa30c67 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -417,12 +417,12 @@ static void gicv3_dump_state(const struct vcpu *v) if ( v == current ) { for ( i = 0; i < gicv3_info.nr_lrs; i++ ) - printk(" HW_LR[%d]=%llx\n", i, gicv3_ich_read_lr(i)); + printk(" HW_LR[%d]=%" PRIu64 "\n", i, gicv3_ich_read_lr(i)); } else { for ( i = 0; i < gicv3_info.nr_lrs; i++ ) - printk(" VCPU_LR[%d]=%llx\n", i, v->arch.gic.v3.lr[i]); + printk(" VCPU_LR[%d]=%" PRIu64 "\n", i, v->arch.gic.v3.lr[i]); } } diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h index 87115f8b25..3a24bd4825 100644 --- a/xen/arch/arm/include/asm/gic_v3_defs.h +++ b/xen/arch/arm/include/asm/gic_v3_defs.h @@ -195,7 +195,7 @@ #define ICH_SGI_IRQMODE_SHIFT 40 #define ICH_SGI_IRQMODE_MASK 0x1 -#define ICH_SGI_TARGET_OTHERS 1UL +#define ICH_SGI_TARGET_OTHERS 1ULL #define ICH_SGI_TARGET_LIST 0 #define ICH_SGI_IRQ_SHIFT 24 #define ICH_SGI_IRQ_MASK 0xf diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/asm/gic_v3_its.h index fae3f6ecef..5ae50b18ea 100644 --- a/xen/arch/arm/include/asm/gic_v3_its.h +++ b/xen/arch/arm/include/asm/gic_v3_its.h @@ -38,7 +38,7 @@ #define GITS_PIDR2 GICR_PIDR2 /* Register bits */ -#define GITS_VALID_BIT BIT(63, UL) +#define GITS_VALID_BIT BIT(63, ULL) #define GITS_CTLR_QUIESCENT BIT(31, UL) #define GITS_CTLR_ENABLE BIT(0, UL) diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c index 58d939b85f..2b7bb17800 100644 --- a/xen/arch/arm/vgic-v3-its.c +++ b/xen/arch/arm/vgic-v3-its.c @@ -96,13 +96,13 @@ typedef uint16_t coll_table_entry_t; * in the lowest 5 bits of the word. */ typedef uint64_t dev_table_entry_t; -#define DEV_TABLE_ITT_ADDR(x) ((x) & GENMASK(51, 8)) +#define DEV_TABLE_ITT_ADDR(x) ((x) & GENMASK_ULL(51, 8)) #define DEV_TABLE_ITT_SIZE(x) (BIT(((x) & GENMASK(4, 0)) + 1, UL)) #define DEV_TABLE_ENTRY(addr, bits) \ (((addr) & GENMASK(51, 8)) | (((bits) - 1) & GENMASK(4, 0))) #define GITS_BASER_RO_MASK (GITS_BASER_TYPE_MASK | \ - (0x1fL << GITS_BASER_ENTRY_SIZE_SHIFT)) + (0x1fLL << GITS_BASER_ENTRY_SIZE_SHIFT)) /* * The physical address is encoded slightly differently depending on @@ -112,10 +112,10 @@ typedef uint64_t dev_table_entry_t; static paddr_t get_baser_phys_addr(uint64_t reg) { if ( reg & BIT(9, UL) ) - return (reg & GENMASK(47, 16)) | + return (reg & GENMASK_ULL(47, 16)) | ((reg & GENMASK(15, 12)) << 36); else - return reg & GENMASK(47, 12); + return reg & GENMASK_ULL(47, 12); } /* Must be called with the ITS lock held. */ @@ -414,7 +414,7 @@ static int update_lpi_property(struct domain *d, struct pending_irq *p) if ( !d->arch.vgic.rdists_enabled ) return 0; - addr = d->arch.vgic.rdist_propbase & GENMASK(51, 12); + addr = d->arch.vgic.rdist_propbase & GENMASK_ULL(51, 12); ret = access_guest_memory_by_ipa(d, addr + p->irq - LPI_OFFSET, &property, sizeof(property), false); @@ -897,7 +897,8 @@ out_unlock: static void dump_its_command(uint64_t *command) { - gdprintk(XENLOG_WARNING, " cmd 0x%02lx: %016lx %016lx %016lx %016lx\n", + gdprintk(XENLOG_WARNING, " cmd 0x%" PRIu64 ": %" PRIu64 + "%" PRIu64 "%" PRIu64 "%" PRIu64 "\n", its_cmd_get_command(command), command[0], command[1], command[2], command[3]); } @@ -909,7 +910,7 @@ static void dump_its_command(uint64_t *command) */ static int vgic_its_handle_cmds(struct domain *d, struct virt_its *its) { - paddr_t addr = its->cbaser & GENMASK(51, 12); + paddr_t addr = its->cbaser & GENMASK_ULL(51, 12); uint64_t command[4]; ASSERT(spin_is_locked(&its->vcmd_lock)); @@ -1122,7 +1123,7 @@ read_as_zero_64: read_impl_defined: printk(XENLOG_G_DEBUG - "%pv: vGITS: RAZ on implementation defined register offset %#04lx\n", + "%pv: vGITS: RAZ on implementation defined register offset %" PRIx64 "#04llx\n", v, info->gpa & 0xffff); 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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [RFC PATCH v1 11/12] Arm: GICv3: Define macros to read/write 64 bit Date: Fri, 21 Oct 2022 16:31:27 +0100 Message-ID: <20221021153128.44226-12-ayankuma@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221021153128.44226-1-ayankuma@amd.com> References: <20221021153128.44226-1-ayankuma@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EA:EE_|PH7PR12MB7235:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b8cce88-def7-4af0-afa1-08dab3797bd4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HUIINYLI1+i7t8hUz+WcQmMMKNEXfdBy3olTo7KijNvpqxtPGeZjJTs9J8Hh/bZMMBe3P/6EiY1lhfvBXYBWbPX2SrkNE1Pk31IeOH5sw+9iClEXpvxc50Ldc2PjZu78T0+ODDaGHmYP1PNWeMJii4svX1j6H6zh+XUO3/JtokKMN0B0yI7Z/dmkfHCGXB0OjMvkHSFneFw3aVBn66jveJ9AJLW5/t3lr36ZCaRCgpgRZ58cIB1W1aBoy8sboJmHwmsjEFGxO+l0Qfil/Ffi6LhDCHSNn0ULmmyk3jnHkH0ELAcflLxdvJXTG8FWZiammIuDO9aKpPGFnoELceaf1e1M3z9FxSixqTOKweoCiQrflyER9WGN7v9j08tJASdruo2uLozpyNTi2QDlTlT33nMkrxOeFC2O7JQ38/jti8O7TzHUtCR8PHF0ec//3UO35h7olLAk9YjnUOVzOHvLBgJCsI+LnIb77FXeI6vFp1OaBnqgGn8Tiu5+E61bkJP48i1Sz7Z7haFJlp4sAu2z7mJYYyxvtzo/AAumYwDKESUgw8bSeXV6lqx3yThrXXepxBPnSj03pzaxuTA2wlHyR+1U0fsm+/Qh3ZNzCwUl/Wm9q0x9CDqwZmob5BEdmCndlqnovoP0SQiLUCgxpByoaaxXuuX39uWbgK+Ymu6ad48eFjNVnCXApHCwyspxfnptdjaGCik9bctNEvHRyheH4gp/Ka3QvxtiYD1IlaM2nWm8SNk+8bBB1fGon2UkPbZ4QbXGnXajTn6tjeAB3qLzcdhu7X5zVGIEbhxlGRX7SPKuh5kCT2zvuWQG5z5WiaL0 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(346002)(376002)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(8936002)(316002)(26005)(2616005)(36860700001)(5660300002)(6666004)(336012)(70586007)(4326008)(8676002)(41300700001)(70206006)(1076003)(186003)(2906002)(40480700001)(36756003)(40460700003)(82310400005)(54906003)(81166007)(426003)(6916009)(356005)(47076005)(82740400003)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:37.5203 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b8cce88-def7-4af0-afa1-08dab3797bd4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7235 Defined readq_relaxed()/writeq_relaxed() to read and write 64 bit regs. This in turn calls readl_relaxed()/writel_relaxed() twice for the lower and upper 32 bits. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/include/asm/arm32/io.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/arm/include/asm/arm32/io.h b/xen/arch/arm/include/asm/arm32/io.h index 73a879e9fb..6a5f563fbc 100644 --- a/xen/arch/arm/include/asm/arm32/io.h +++ b/xen/arch/arm/include/asm/arm32/io.h @@ -80,10 +80,14 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) __raw_readw(c)); __r; }) #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ __raw_readl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = (le64_to_cpu(readl_relaxed(c+4)) << 32) | \ + readl_relaxed(c); __r; }) #define writeb_relaxed(v,c) __raw_writeb(v,c) #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) +#define writeq_relaxed(v,c) writel_relaxed(((uint64_t)v&0xffffffff), c); \ + writel_relaxed((((uint64_t)v)>>32), (c+4)); #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 15:32:38.9885 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a17336cc-1fcf-465b-2cc7-08dab3797cab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4934 Refer ARM DDI 0487G.b ID072021, D13.2.86 - ID_PFR1_EL1, AArch32 Processor Feature Register 1 GIC, bits[31:28] == 0b0001 for GIC3.0 on Aarch32 One can now enable GICv3 on AArch32 systems. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/Kconfig | 2 +- xen/arch/arm/include/asm/cpufeature.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 1fe5faf847..5eaf21b8e0 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -41,7 +41,7 @@ config ARM_EFI config GICV3 bool "GICv3 driver" - depends on ARM_64 && !NEW_VGIC + depends on (ARM_64 || ARM_32) && !NEW_VGIC default y ---help--- diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h index c86a2e7f29..c8ca09d1c3 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -31,6 +31,7 @@ #define cpu_has_jazelle (boot_cpu_feature32(jazelle) > 0) #define cpu_has_thumbee (boot_cpu_feature32(thumbee) == 1) #define cpu_has_aarch32 (cpu_has_arm || cpu_has_thumb) +#define cpu_has_gicv3 (boot_cpu_feature32(gic) >= 1) #ifdef CONFIG_ARM_32 #define cpu_has_gentimer (boot_cpu_feature32(gentimer) == 1)