From patchwork Sun Oct 23 14:33:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 653EFECAAA1 for ; Sun, 23 Oct 2022 14:33:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230184AbiJWOdg (ORCPT ); Sun, 23 Oct 2022 10:33:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230125AbiJWOdf (ORCPT ); Sun, 23 Oct 2022 10:33:35 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 551FC1032; Sun, 23 Oct 2022 07:33:34 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id bu30so11847941wrb.8; Sun, 23 Oct 2022 07:33:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UT0ZSJttMO+IN7qAwXeIN59Jy0agrsi51doQcQVju30=; b=a4R41X2eIL3ukRmoZio82gBdHf1RipQIToHH1XoKU3wVW61b9R8bZ2B9FnJPaaMC+N EYBvlP5agU5pbx5jgmaT3golS5rSSFTKyRns8NvC5zP2DonVnHtoGe6eTgKPlW+ZnaJr tCBTXCM2niXy3frrsfQ9vUIvFUR/oe3QWesIB5EyJc1QvACAyzfz1j9LHiHeiiessVZm Uxr1n1nd+3eKlDfP7YvuOq6gEG+FkWXoaxdp7Azn6v9v32FT33VCFdJ8auptHYDlHHWT DfdY0z4B9rMKPX39CPMoj0vv4wQKNISpojmcLGTyhgTYu6NS8T828O1hptghMVlieq8u OjcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UT0ZSJttMO+IN7qAwXeIN59Jy0agrsi51doQcQVju30=; b=pyIX9I645VoFxpgDMiNfvphGY+RrbbYRIHhmtG4vhlTbw5h6n6K7pIFE0ppExu78iJ pjiXZY27P6M1zI5D+Yb+Cdr3RhdO5Slcj+1s69YC/VTk/2cgMQq7m1HB1hXrN3icZfUJ Hb6Tb9cESW6bKk0Ds+Z4AkObve6ctovHzE5ikwG7l9bVZClvkHgJFFqohG6iOiTBes+j 8Dt9FxQOc/BZEs3bXdBxmnHz0K+I3VdI1qL16acBpfD56gC3xj5ceVgdfsBJy8RTegx0 E4kGOFmgevbQe0RjV5yeIhPxthVUtg31uVMhoTnbrwcLQwSIJdIN7YAXvDf6eCRswV/L CKXw== X-Gm-Message-State: ACrzQf32Tu+YF8ZMC7XIf80Vc0dgzLD7LSg/+NLL/qNOTwnPqWI1TEoV YpnJ1nYlN2w/1exrZ11wkdM= X-Google-Smtp-Source: AMsMyM4b1TfpWpauU5EEm47KOxNOzxuoX31aAUHykGuhBW0PTbFZhN5faExd22+r1cuOe4l2UjJkVg== X-Received: by 2002:a05:6000:4084:b0:22e:5b99:4c4a with SMTP id da4-20020a056000408400b0022e5b994c4amr19057178wrb.538.1666535612756; Sun, 23 Oct 2022 07:33:32 -0700 (PDT) Received: from localhost (94.197.10.75.threembb.co.uk. [94.197.10.75]) by smtp.gmail.com with ESMTPSA id c1-20020adfed81000000b00226dba960b4sm24235577wro.3.2022.10.23.07.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:33:32 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/9] ASoC: jz4740-i2s: Handle independent FIFO flush bits Date: Sun, 23 Oct 2022 15:33:20 +0100 Message-Id: <20221023143328.160866-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> References: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On the JZ4740, there is a single bit that flushes (empties) both the transmit and receive FIFO. Later SoCs have independent flush bits for each FIFO. Independent FIFOs can be flushed before the snd_soc_dai_active() check because it won't disturb other active streams. This ensures that the FIFO we're about to use is always flushed before starting up. With shared FIFOs we can't do that because if another substream is active, flushing its FIFO would cause underrun errors. This also fixes a bug: since we were only setting the JZ4740's flush bit, which corresponds to the TX FIFO flush bit on other SoCs, other SoCs were not having their RX FIFO flushed at all. Fixes: 967beb2e8777 ("ASoC: jz4740: Add jz4780 support") Reviewed-by: Paul Cercueil Cc: stable@vger.kernel.org Signed-off-by: Aidan MacDonald --- v5 -> v6: Cc'd stable. sound/soc/jz4740/jz4740-i2s.c | 39 ++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index c4c1e89b47c1..83cb81999c6f 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -55,7 +55,8 @@ #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) -#define JZ_AIC_CTRL_FLUSH BIT(8) +#define JZ_AIC_CTRL_TFLUSH BIT(8) +#define JZ_AIC_CTRL_RFLUSH BIT(7) #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) @@ -90,6 +91,8 @@ enum jz47xx_i2s_version { struct i2s_soc_info { enum jz47xx_i2s_version version; struct snd_soc_dai_driver *dai; + + bool shared_fifo_flush; }; struct jz4740_i2s { @@ -116,19 +119,44 @@ static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s, writel(value, i2s->base + reg); } +static inline void jz4740_i2s_set_bits(const struct jz4740_i2s *i2s, + unsigned int reg, uint32_t bits) +{ + uint32_t value = jz4740_i2s_read(i2s, reg); + value |= bits; + jz4740_i2s_write(i2s, reg, value); +} + static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - uint32_t conf, ctrl; + uint32_t conf; int ret; + /* + * When we can flush FIFOs independently, only flush the FIFO + * that is starting up. We can do this when the DAI is active + * because it does not disturb other active substreams. + */ + if (!i2s->soc_info->shared_fifo_flush) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); + else + jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH); + } + if (snd_soc_dai_active(dai)) return 0; - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); - ctrl |= JZ_AIC_CTRL_FLUSH; - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); + /* + * When there is a shared flush bit for both FIFOs, the TFLUSH + * bit flushes both FIFOs. Flushing while the DAI is active would + * cause FIFO underruns in other active substreams so we have to + * guard this behind the snd_soc_dai_active() check. + */ + if (i2s->soc_info->shared_fifo_flush) + jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); ret = clk_prepare_enable(i2s->clk_i2s); if (ret) @@ -443,6 +471,7 @@ static struct snd_soc_dai_driver jz4740_i2s_dai = { static const struct i2s_soc_info jz4740_i2s_soc_info = { .version = JZ_I2S_JZ4740, .dai = &jz4740_i2s_dai, + .shared_fifo_flush = true, }; static const struct i2s_soc_info jz4760_i2s_soc_info = { From patchwork Sun Oct 23 14:33:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016276 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2BF1FA373F for ; Sun, 23 Oct 2022 14:33:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230201AbiJWOdh (ORCPT ); Sun, 23 Oct 2022 10:33:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230206AbiJWOdg (ORCPT ); Sun, 23 Oct 2022 10:33:36 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B79B61B31; Sun, 23 Oct 2022 07:33:35 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id v1so11821384wrt.11; Sun, 23 Oct 2022 07:33:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ua+FwbDcAn/zYyqw249yK6lna19o3nAvvkXKqxMQ6wo=; b=BE0N5+F3cEOaEJky6hm6Cpk+6yOJ45QkDTbBkv1Ii5xVrzVrMrf4MArmIyMXwXJVrv mz20bkYR82oQh3vU2moZ7QVoCXFNkO4Wab8ZMEuMr5iBowwZcblJjmVUBixUkypCM0ei yHOxMZGri40QmmkTJ6r5QFgzzMga5aACumugo/AkfcZPCSlPawR+DpqcnHIGcp9C4wLb AoHydIdGPQGQp3xxnSHSXzlX+cHn5gj/FZX8dpQRqJpcgjmVXAK2wBkMY+k3uOT75SZc ox00CVEQOAmWKkte9BGazsq5Zxdppz9OBwGx9CV5LaNtkAEa3p4FSK0EHHYKu+/oQ47n 0+fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ua+FwbDcAn/zYyqw249yK6lna19o3nAvvkXKqxMQ6wo=; b=SEDkBLzcHzrbuyesezGSy3aiiYktCXinZJRhMGg5DClpUdSjx32aABfIwi1PfSuOgJ JZ/uLdzG95mFjs556498tlvp30pW4euhciZgAM9X40JshdWWpBWPtPigoaD/8Vv8K4Ms OYoTlRk/u1O63JFFBnGbVS75dfJMzu0fNlYf93ZN+WE0yyS3eAH2OSiCjF3CAMR0bXeg we8GA1P5mH5+qWK0CZr2CdDnWKn8wG+6pmO1XKF0UZgTTWDvxmLVu5K0dhoYfvZx4qOT 7Q51++Oe/EIAOXzw+Au/4b7zvCLBRMq4Zi794A06y17q3KZTyt6VQVZmcD9gW+qJtvR/ Fz0g== X-Gm-Message-State: ACrzQf31UKXo66ohpKOTSpIq40oS7o+Q7EPT+y8kp05VP60b+hQ3F6N4 Ob8zVJRvEKXrjBmnZ/eutR4= X-Google-Smtp-Source: AMsMyM4Ki7MRh46upU/1k/r7VHIaOL9Zp92nKlN25TXoHMRIEOUeJ8vNgM0Ggv5DDTNm0qfbaVscnQ== X-Received: by 2002:a5d:5a82:0:b0:224:f744:1799 with SMTP id bp2-20020a5d5a82000000b00224f7441799mr18328050wrb.582.1666535614087; Sun, 23 Oct 2022 07:33:34 -0700 (PDT) Received: from localhost (94.197.10.75.threembb.co.uk. [94.197.10.75]) by smtp.gmail.com with ESMTPSA id iv13-20020a05600c548d00b003b4fdbb6319sm5679489wmb.21.2022.10.23.07.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:33:33 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 2/9] ASoC: jz4740-i2s: Convert to regmap API Date: Sun, 23 Oct 2022 15:33:21 +0100 Message-Id: <20221023143328.160866-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> References: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Using regmap for accessing the AIC registers makes the driver a little easier to read, and later refactors can take advantage of regmap APIs to further simplify the driver. Reviewed-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/Kconfig | 1 + sound/soc/jz4740/jz4740-i2s.c | 106 ++++++++++++---------------------- 2 files changed, 39 insertions(+), 68 deletions(-) diff --git a/sound/soc/jz4740/Kconfig b/sound/soc/jz4740/Kconfig index e72f826062e9..dd3b4507fbe6 100644 --- a/sound/soc/jz4740/Kconfig +++ b/sound/soc/jz4740/Kconfig @@ -3,6 +3,7 @@ config SND_JZ4740_SOC_I2S tristate "SoC Audio (I2S protocol) for Ingenic JZ4740 SoC" depends on MIPS || COMPILE_TEST depends on HAS_IOMEM + select REGMAP_MMIO select SND_SOC_GENERIC_DMAENGINE_PCM help Say Y if you want to use I2S protocol and I2S codec on Ingenic JZ4740 diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 83cb81999c6f..f3c0d7c0415e 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -96,7 +97,7 @@ struct i2s_soc_info { }; struct jz4740_i2s { - void __iomem *base; + struct regmap *regmap; struct clk *clk_aic; struct clk *clk_i2s; @@ -107,31 +108,10 @@ struct jz4740_i2s { const struct i2s_soc_info *soc_info; }; -static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s, - unsigned int reg) -{ - return readl(i2s->base + reg); -} - -static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s, - unsigned int reg, uint32_t value) -{ - writel(value, i2s->base + reg); -} - -static inline void jz4740_i2s_set_bits(const struct jz4740_i2s *i2s, - unsigned int reg, uint32_t bits) -{ - uint32_t value = jz4740_i2s_read(i2s, reg); - value |= bits; - jz4740_i2s_write(i2s, reg, value); -} - static int jz4740_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - uint32_t conf; int ret; /* @@ -141,9 +121,9 @@ static int jz4740_i2s_startup(struct snd_pcm_substream *substream, */ if (!i2s->soc_info->shared_fifo_flush) { if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); else - jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH); + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH); } if (snd_soc_dai_active(dai)) @@ -156,16 +136,13 @@ static int jz4740_i2s_startup(struct snd_pcm_substream *substream, * guard this behind the snd_soc_dai_active() check. */ if (i2s->soc_info->shared_fifo_flush) - jz4740_i2s_set_bits(i2s, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); ret = clk_prepare_enable(i2s->clk_i2s); if (ret) return ret; - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf |= JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); - + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); return 0; } @@ -173,14 +150,11 @@ static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - uint32_t conf; if (snd_soc_dai_active(dai)) return; - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf &= ~JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); clk_disable_unprepare(i2s->clk_i2s); } @@ -189,8 +163,6 @@ static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - - uint32_t ctrl; uint32_t mask; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) @@ -198,38 +170,30 @@ static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd, else mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA; - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); - switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - ctrl |= mask; + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - ctrl &= ~mask; + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); break; default: return -EINVAL; } - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); - return 0; } static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - - uint32_t format = 0; - uint32_t conf; - - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - - conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER); + const unsigned int conf_mask = JZ_AIC_CONF_BIT_CLK_MASTER | + JZ_AIC_CONF_SYNC_CLK_MASTER; + unsigned int conf = 0, format = 0; switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { case SND_SOC_DAIFMT_BP_FP: @@ -265,8 +229,8 @@ static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) return -EINVAL; } - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); - jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format); + regmap_update_bits(i2s->regmap, JZ_REG_AIC_CONF, conf_mask, conf); + regmap_write(i2s->regmap, JZ_REG_AIC_I2S_FMT, format); return 0; } @@ -279,9 +243,9 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, uint32_t ctrl, div_reg; int div; - ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); + regmap_read(i2s->regmap, JZ_REG_AIC_CTRL, &ctrl); + regmap_read(i2s->regmap, JZ_REG_AIC_CLK_DIV, &div_reg); - div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV); div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); switch (params_format(params)) { @@ -318,8 +282,8 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, } } - jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); - jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg); + regmap_write(i2s->regmap, JZ_REG_AIC_CTRL, ctrl); + regmap_write(i2s->regmap, JZ_REG_AIC_CLK_DIV, div_reg); return 0; } @@ -356,13 +320,9 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, static int jz4740_i2s_suspend(struct snd_soc_component *component) { struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - uint32_t conf; if (snd_soc_component_active(component)) { - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf &= ~JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); - + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); clk_disable_unprepare(i2s->clk_i2s); } @@ -374,7 +334,6 @@ static int jz4740_i2s_suspend(struct snd_soc_component *component) static int jz4740_i2s_resume(struct snd_soc_component *component) { struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - uint32_t conf; int ret; ret = clk_prepare_enable(i2s->clk_aic); @@ -388,9 +347,7 @@ static int jz4740_i2s_resume(struct snd_soc_component *component) return ret; } - conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF); - conf |= JZ_AIC_CONF_ENABLE; - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); } return 0; @@ -423,8 +380,8 @@ static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) JZ_AIC_CONF_INTERNAL_CODEC; } - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); - jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf); + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, conf); return 0; } @@ -523,11 +480,19 @@ static const struct of_device_id jz4740_of_matches[] = { }; MODULE_DEVICE_TABLE(of, jz4740_of_matches); +static const struct regmap_config jz4740_i2s_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = JZ_REG_AIC_FIFO, +}; + static int jz4740_i2s_dev_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct jz4740_i2s *i2s; struct resource *mem; + void __iomem *regs; int ret; i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); @@ -536,9 +501,9 @@ static int jz4740_i2s_dev_probe(struct platform_device *pdev) i2s->soc_info = device_get_match_data(dev); - i2s->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); - if (IS_ERR(i2s->base)) - return PTR_ERR(i2s->base); + regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); + if (IS_ERR(regs)) + return PTR_ERR(regs); i2s->playback_dma_data.maxburst = 16; i2s->playback_dma_data.addr = mem->start + JZ_REG_AIC_FIFO; @@ -554,6 +519,11 @@ static int jz4740_i2s_dev_probe(struct platform_device *pdev) if (IS_ERR(i2s->clk_i2s)) return PTR_ERR(i2s->clk_i2s); + i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, + &jz4740_i2s_regmap_config); + if (IS_ERR(i2s->regmap)) + return PTR_ERR(i2s->regmap); + platform_set_drvdata(pdev, i2s); ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component, From patchwork Sun Oct 23 14:33:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8D02C3A59D for ; Sun, 23 Oct 2022 14:33:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230267AbiJWOdq (ORCPT ); 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[94.197.10.75]) by smtp.gmail.com with ESMTPSA id j11-20020a05600c190b00b003b47e8a5d22sm5603903wmq.23.2022.10.23.07.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:33:34 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/9] ASoC: jz4740-i2s: Simplify using regmap fields Date: Sun, 23 Oct 2022 15:33:22 +0100 Message-Id: <20221023143328.160866-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> References: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The differences between register fields on different SoC versions can be abstracted away using the regmap field API. This is easier to understand and extend than comparisons based on the version ID. Since the version IDs are unused after this change, remove them at the same time, and remove unused macros. Reviewed-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 135 +++++++++++++++++++--------------- 1 file changed, 77 insertions(+), 58 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index f3c0d7c0415e..b0bbcd025241 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -34,8 +34,6 @@ #define JZ_REG_AIC_CLK_DIV 0x30 #define JZ_REG_AIC_FIFO 0x34 -#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12) -#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8) #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) #define JZ_AIC_CONF_I2S BIT(4) @@ -44,11 +42,6 @@ #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) #define JZ_AIC_CONF_ENABLE BIT(0) -#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12 -#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8 -#define JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24 -#define JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16 - #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19) #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16) #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) @@ -76,29 +69,25 @@ #define JZ_AIC_I2S_STATUS_BUSY BIT(2) -#define JZ_AIC_CLK_DIV_MASK 0xf -#define I2SDIV_DV_SHIFT 0 -#define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT) -#define I2SDIV_IDV_SHIFT 8 -#define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT) - -enum jz47xx_i2s_version { - JZ_I2S_JZ4740, - JZ_I2S_JZ4760, - JZ_I2S_JZ4770, - JZ_I2S_JZ4780, -}; - struct i2s_soc_info { - enum jz47xx_i2s_version version; struct snd_soc_dai_driver *dai; + struct reg_field field_rx_fifo_thresh; + struct reg_field field_tx_fifo_thresh; + struct reg_field field_i2sdiv_capture; + struct reg_field field_i2sdiv_playback; + bool shared_fifo_flush; }; struct jz4740_i2s { struct regmap *regmap; + struct regmap_field *field_rx_fifo_thresh; + struct regmap_field *field_tx_fifo_thresh; + struct regmap_field *field_i2sdiv_capture; + struct regmap_field *field_i2sdiv_playback; + struct clk *clk_aic; struct clk *clk_i2s; @@ -239,12 +228,12 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); + struct regmap_field *div_field; unsigned int sample_size; - uint32_t ctrl, div_reg; + uint32_t ctrl; int div; regmap_read(i2s->regmap, JZ_REG_AIC_CTRL, &ctrl); - regmap_read(i2s->regmap, JZ_REG_AIC_CLK_DIV, &div_reg); div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params)); @@ -267,23 +256,16 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, else ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO; - div_reg &= ~I2SDIV_DV_MASK; - div_reg |= (div - 1) << I2SDIV_DV_SHIFT; + div_field = i2s->field_i2sdiv_playback; } else { ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK; ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET; - if (i2s->soc_info->version >= JZ_I2S_JZ4770) { - div_reg &= ~I2SDIV_IDV_MASK; - div_reg |= (div - 1) << I2SDIV_IDV_SHIFT; - } else { - div_reg &= ~I2SDIV_DV_MASK; - div_reg |= (div - 1) << I2SDIV_DV_SHIFT; - } + div_field = i2s->field_i2sdiv_capture; } regmap_write(i2s->regmap, JZ_REG_AIC_CTRL, ctrl); - regmap_write(i2s->regmap, JZ_REG_AIC_CLK_DIV, div_reg); + regmap_field_write(div_field, div - 1); return 0; } @@ -356,7 +338,6 @@ static int jz4740_i2s_resume(struct snd_soc_component *component) static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - uint32_t conf; int ret; ret = clk_prepare_enable(i2s->clk_aic); @@ -366,22 +347,14 @@ static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, &i2s->capture_dma_data); - if (i2s->soc_info->version >= JZ_I2S_JZ4760) { - conf = (7 << JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | - (8 << JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | - JZ_AIC_CONF_OVERFLOW_PLAY_LAST | - JZ_AIC_CONF_I2S | - JZ_AIC_CONF_INTERNAL_CODEC; - } else { - conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) | - (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) | - JZ_AIC_CONF_OVERFLOW_PLAY_LAST | - JZ_AIC_CONF_I2S | - JZ_AIC_CONF_INTERNAL_CODEC; - } - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, conf); + + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, + JZ_AIC_CONF_OVERFLOW_PLAY_LAST | + JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); + + regmap_field_write(i2s->field_rx_fifo_thresh, 7); + regmap_field_write(i2s->field_tx_fifo_thresh, 8); return 0; } @@ -426,14 +399,20 @@ static struct snd_soc_dai_driver jz4740_i2s_dai = { }; static const struct i2s_soc_info jz4740_i2s_soc_info = { - .version = JZ_I2S_JZ4740, - .dai = &jz4740_i2s_dai, - .shared_fifo_flush = true, + .dai = &jz4740_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 12, 15), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 8, 11), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .shared_fifo_flush = true, }; static const struct i2s_soc_info jz4760_i2s_soc_info = { - .version = JZ_I2S_JZ4760, - .dai = &jz4740_i2s_dai, + .dai = &jz4740_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), }; static struct snd_soc_dai_driver jz4770_i2s_dai = { @@ -455,13 +434,19 @@ static struct snd_soc_dai_driver jz4770_i2s_dai = { }; static const struct i2s_soc_info jz4770_i2s_soc_info = { - .version = JZ_I2S_JZ4770, - .dai = &jz4770_i2s_dai, + .dai = &jz4770_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), }; static const struct i2s_soc_info jz4780_i2s_soc_info = { - .version = JZ_I2S_JZ4780, - .dai = &jz4770_i2s_dai, + .dai = &jz4770_i2s_dai, + .field_rx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 24, 27), + .field_tx_fifo_thresh = REG_FIELD(JZ_REG_AIC_CONF, 16, 20), + .field_i2sdiv_capture = REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), + .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), }; static const struct snd_soc_component_driver jz4740_i2s_component = { @@ -480,6 +465,36 @@ static const struct of_device_id jz4740_of_matches[] = { }; MODULE_DEVICE_TABLE(of, jz4740_of_matches); +static int jz4740_i2s_init_regmap_fields(struct device *dev, + struct jz4740_i2s *i2s) +{ + i2s->field_rx_fifo_thresh = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_rx_fifo_thresh); + if (IS_ERR(i2s->field_rx_fifo_thresh)) + return PTR_ERR(i2s->field_rx_fifo_thresh); + + i2s->field_tx_fifo_thresh = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_tx_fifo_thresh); + if (IS_ERR(i2s->field_tx_fifo_thresh)) + return PTR_ERR(i2s->field_tx_fifo_thresh); + + i2s->field_i2sdiv_capture = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_i2sdiv_capture); + if (IS_ERR(i2s->field_i2sdiv_capture)) + return PTR_ERR(i2s->field_i2sdiv_capture); + + i2s->field_i2sdiv_playback = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->soc_info->field_i2sdiv_playback); + if (IS_ERR(i2s->field_i2sdiv_playback)) + return PTR_ERR(i2s->field_i2sdiv_playback); + + return 0; +} + static const struct regmap_config jz4740_i2s_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -524,6 +539,10 @@ static int jz4740_i2s_dev_probe(struct platform_device *pdev) if (IS_ERR(i2s->regmap)) return PTR_ERR(i2s->regmap); + ret = jz4740_i2s_init_regmap_fields(dev, i2s); + if (ret) + return ret; + platform_set_drvdata(pdev, i2s); ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component, From patchwork Sun Oct 23 14:33:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F7B2ECAAA1 for ; Sun, 23 Oct 2022 14:33:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230235AbiJWOdk (ORCPT ); Sun, 23 Oct 2022 10:33:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230216AbiJWOdi (ORCPT ); Sun, 23 Oct 2022 10:33:38 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 143F061B39; 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[94.197.10.75]) by smtp.gmail.com with ESMTPSA id c17-20020a5d4cd1000000b002362f6fcaf5sm2925381wrt.48.2022.10.23.07.33.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:33:36 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/9] ASoC: jz4740-i2s: Use FIELD_PREP() macros in hw_params callback Date: Sun, 23 Oct 2022 15:33:23 +0100 Message-Id: <20221023143328.160866-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> References: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Get rid of a couple of macros and improve readability by using FIELD_PREP() and GENMASK() for the sample size setting. Acked-by: Paul Cercueil Reviewed-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index b0bbcd025241..4767abea425f 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -3,6 +3,7 @@ * Copyright (C) 2010, Lars-Peter Clausen */ +#include #include #include #include @@ -42,8 +43,8 @@ #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) #define JZ_AIC_CONF_ENABLE BIT(0) -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19) -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16) +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) @@ -59,9 +60,6 @@ #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19 -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16 - #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) #define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) @@ -249,8 +247,9 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK; - ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET; + ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE; + ctrl |= FIELD_PREP(JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE, sample_size); + if (params_channels(params) == 1) ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO; else @@ -258,8 +257,8 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, div_field = i2s->field_i2sdiv_playback; } else { - ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK; - ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET; + ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE; + ctrl |= FIELD_PREP(JZ_AIC_CTRL_INPUT_SAMPLE_SIZE, sample_size); div_field = i2s->field_i2sdiv_capture; } From patchwork Sun Oct 23 14:33:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016278 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46321FA373F for ; Sun, 23 Oct 2022 14:33:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230273AbiJWOdr (ORCPT ); Sun, 23 Oct 2022 10:33:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230226AbiJWOdj (ORCPT ); Sun, 23 Oct 2022 10:33:39 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47B2D61D4B; Sun, 23 Oct 2022 07:33:38 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id v1so11821505wrt.11; Sun, 23 Oct 2022 07:33:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZPVuUDMde4iT9AFYS7nsIkkUonhoCr0Fb8M7bh3R14c=; b=axlbN88z42NeyE9gww1dFYP+qpXMECN3tXcq/dmWjoR7QBfnKv8sAf7zy6oqZpkGJK fS4+Fb50bYSBaJxYSKsFYgh6aOqJBl2eVfDlQxFg3nygMMN0zpLGY1NH6v+9ueEaObih GvRXstIvxK22ja+OuKvM1KszAOLGI+ffJD8Tn4X42APvrxRqo1ARkmLdNXpWFktwYbuy ivWm8xJFmcZB0aSorqYMakPU3QnEtZ3G4M8Pq7gdiLFMVGI/H2mEH6C5SFAuekUQ7sam we+cvj4ThPxB70kRh+LNxFGkWga0SHGP0txJVZIICeo648JL0fWxzgZ/6ZFBdLwRaqis licw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZPVuUDMde4iT9AFYS7nsIkkUonhoCr0Fb8M7bh3R14c=; b=kRsqrprjDH6Q/W7y07UaYsd0SVBkwZS39J9XGFM0VxgCilMrt5W9S5IPNySG/tY+DS 7/TEqpxNZL5ZmS7wq8o3j0XGm86sD4MmkQIJu4J24sIE6xq2tJSHHAY2BJEktPyDsop0 z+KSy0fGFq1xKT2QpmzgcHi50fpVKu7riMwxT6MIPBjWxVksZyeX0Nznvu/PVyo8noAS mkMI1+2wjUke0C3diTdGy4iFZnZqZ6IcNzUv23utl5gcIcPYooSzfaMhMEEsWk+8qCIP mM1cJE2qY+MReRTKY571J06adCOh6LTxA1nvONwHXmMjGpehyXr6AN9e85ZdqsDO7uML S3Zg== X-Gm-Message-State: ACrzQf27TuyJBLRdPC1mloGrLwyfOfMZvA5voWKyEL6dvB93aVrDSxPr oWzf/xXXlTLwF6Q1Lhw3410= X-Google-Smtp-Source: AMsMyM6nByUQJewaeg4c+zis+6VAd98GbK2NlqxFod153k4DlVNEl6Kut045sy5mkB/eZajarZzoDQ== X-Received: by 2002:a5d:42c5:0:b0:236:60ed:9abf with SMTP id t5-20020a5d42c5000000b0023660ed9abfmr4416189wrr.454.1666535617850; Sun, 23 Oct 2022 07:33:37 -0700 (PDT) Received: from localhost (94.197.10.75.threembb.co.uk. [94.197.10.75]) by smtp.gmail.com with ESMTPSA id hg16-20020a05600c539000b003c6b70a4d69sm8300046wmb.42.2022.10.23.07.33.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:33:37 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 5/9] ASoC: jz4740-i2s: Align macro values and sort includes Date: Sun, 23 Oct 2022 15:33:24 +0100 Message-Id: <20221023143328.160866-6-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> References: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Some purely cosmetic changes: line up all the macro values to make things easier to read and sort the includes alphabetically. Acked-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 66 +++++++++++++++++------------------ 1 file changed, 32 insertions(+), 34 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 4767abea425f..c3235e993ffb 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -4,6 +4,9 @@ */ #include +#include +#include +#include #include #include #include @@ -13,11 +16,6 @@ #include #include -#include -#include - -#include - #include #include #include @@ -35,37 +33,37 @@ #define JZ_REG_AIC_CLK_DIV 0x30 #define JZ_REG_AIC_FIFO 0x34 -#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) -#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) -#define JZ_AIC_CONF_I2S BIT(4) -#define JZ_AIC_CONF_RESET BIT(3) -#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) -#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) -#define JZ_AIC_CONF_ENABLE BIT(0) - -#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) -#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) -#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) -#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) -#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) -#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) -#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) +#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6) +#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5) +#define JZ_AIC_CONF_I2S BIT(4) +#define JZ_AIC_CONF_RESET BIT(3) +#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2) +#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1) +#define JZ_AIC_CONF_ENABLE BIT(0) + +#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE GENMASK(21, 19) +#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE GENMASK(18, 16) +#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15) +#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14) +#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11) +#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10) +#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9) #define JZ_AIC_CTRL_TFLUSH BIT(8) #define JZ_AIC_CTRL_RFLUSH BIT(7) -#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) -#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) -#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) -#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) -#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) -#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) -#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) - -#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) -#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) -#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) -#define JZ_AIC_I2S_FMT_MSB BIT(0) - -#define JZ_AIC_I2S_STATUS_BUSY BIT(2) +#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6) +#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5) +#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4) +#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3) +#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2) +#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1) +#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0) + +#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12) +#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13) +#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4) +#define JZ_AIC_I2S_FMT_MSB BIT(0) + +#define JZ_AIC_I2S_STATUS_BUSY BIT(2) struct i2s_soc_info { struct snd_soc_dai_driver *dai; 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[94.197.10.75]) by smtp.gmail.com with ESMTPSA id f18-20020adff452000000b0022584c82c80sm23726047wrp.19.2022.10.23.07.33.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:33:38 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 6/9] ASoC: jz4740-i2s: Support S20_LE and S24_LE sample formats Date: Sun, 23 Oct 2022 15:33:25 +0100 Message-Id: <20221023143328.160866-7-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> References: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The audio controller on JZ47xx SoCs can transfer 20- and 24-bit samples in the FIFO, so allow those formats to be used with the I2S driver. Although the FIFO doesn't care about the in-memory sample format, we only support 4-byte format variants because the DMA controller on these SoCs cannot transfer in 3-byte multiples. Reviewed-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index c3235e993ffb..fd35a8a51f60 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -237,9 +237,15 @@ static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream, case SNDRV_PCM_FORMAT_S8: sample_size = 0; break; - case SNDRV_PCM_FORMAT_S16: + case SNDRV_PCM_FORMAT_S16_LE: sample_size = 1; break; + case SNDRV_PCM_FORMAT_S20_LE: + sample_size = 3; + break; + case SNDRV_PCM_FORMAT_S24_LE: + sample_size = 4; + break; default: return -EINVAL; } @@ -374,7 +380,9 @@ static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { }; #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \ - SNDRV_PCM_FMTBIT_S16_LE) + SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S20_LE | \ + SNDRV_PCM_FMTBIT_S24_LE) static struct snd_soc_dai_driver jz4740_i2s_dai = { .probe = jz4740_i2s_dai_probe, From patchwork Sun Oct 23 14:33:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED98DFA373E for ; Sun, 23 Oct 2022 14:33:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230261AbiJWOdy (ORCPT ); Sun, 23 Oct 2022 10:33:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230256AbiJWOdp (ORCPT ); Sun, 23 Oct 2022 10:33:45 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C43DD61D65; Sun, 23 Oct 2022 07:33:41 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id m29-20020a05600c3b1d00b003c6bf423c71so8348950wms.0; Sun, 23 Oct 2022 07:33:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pvKXzpxFzZWAwh4ulfZ9nH6QQVrhwgz8YLgYLKE7oQk=; b=MiAv+zhVnlxmLdsRupQuYxZ+FUIDw9Fj/el8pUwCqfG4qpwFptaKXOgIZ3I2VqjkjZ biPuyIRR20VekRI4LcN+B89C4XYiGOmLicys+PnEUSFspnnqkDUJiK5yW8GhA1GPe0SV xkQsFftWaV3+6oOAvUIqUqJLlinN2RypA76M9QbkIo/regxEFAyvc35MIatgg0kR8tLf PxNpcjmFvCbtn1avOhGUn3eam5WA9Yf3TlUdKoLQXIxkrBUZoJBnqQKCJoQ1bO/8b6N8 JgiWjxgbJ5kvOxcHUUUDO7ul8vG87dAiK7hptPQe1rovWUJBRHa8iXzcyCGhdkfMps26 j9/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pvKXzpxFzZWAwh4ulfZ9nH6QQVrhwgz8YLgYLKE7oQk=; b=mcs9S2hr34bVlIdaBgOeqZsGeKdduXgXFNRHEzznOrLzOD75LGjDGZn3eqroraM6Nc VrgHkCSsRJDwcq9bTim0hI+j8qdrsooDsYaGMYw19qaTUs3FYN+9l2O1fFLwIhTkvD6z oyJTKjUVhszqwDztkoZ4SnoaCwe41Xs5TitkIXZetuXgstLwTkhmJDzdQnsamZS9zdrs fsU8g3fau4n4HSmwXazMZrj6VbrRYwpK5KKwHRyK31uLi4zIbWasof3VI3FYUQ0l833s 7ZGqBGiy5loptNW5C2oxubwWqLhk5EvEjjTgwGh6FFEe2hzS/p2Z1mmuBPy8VEVWp4BL ziSw== X-Gm-Message-State: ACrzQf3C7mzFvvKAC8W/TmgEAFMb+/4jyUBtD0eQdJScVqVSaCqhLbhK 9B581JyRJgM9Cr39t23DGeIDh2vYLTo= X-Google-Smtp-Source: AMsMyM4Jr8bpSn4dBiYu8xvawkAvOdkOXBkSzIVXVHX5h6ly2AgTR60eJ8BpaVu5+s3ByLfKeFZqXg== X-Received: by 2002:a05:600c:358f:b0:3c6:da94:66f9 with SMTP id p15-20020a05600c358f00b003c6da9466f9mr18888398wmq.142.1666535620335; Sun, 23 Oct 2022 07:33:40 -0700 (PDT) Received: from localhost (94.197.10.75.threembb.co.uk. [94.197.10.75]) by smtp.gmail.com with ESMTPSA id l24-20020a1c7918000000b003b50428cf66sm8463974wme.33.2022.10.23.07.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:33:39 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 7/9] ASoC: jz4740-i2s: Support continuous sample rate Date: Sun, 23 Oct 2022 15:33:26 +0100 Message-Id: <20221023143328.160866-8-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> References: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The I2S controller on JZ47xx SoCs doesn't impose restrictions on sample rate and the driver doesn't make any assumptions about it, so the DAI should advertise a continuous sample rate range. Acked-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index fd35a8a51f60..201368f828ff 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -390,13 +390,13 @@ static struct snd_soc_dai_driver jz4740_i2s_dai = { .playback = { .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .capture = { .channels_min = 2, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .symmetric_rate = 1, @@ -426,13 +426,13 @@ static struct snd_soc_dai_driver jz4770_i2s_dai = { .playback = { .channels_min = 1, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .capture = { .channels_min = 2, .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, + .rates = SNDRV_PCM_RATE_CONTINUOUS, .formats = JZ4740_I2S_FMTS, }, .ops = &jz4740_i2s_dai_ops, From patchwork Sun Oct 23 14:33:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016282 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C691C3A59D for ; Sun, 23 Oct 2022 14:34:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230335AbiJWOeK (ORCPT ); Sun, 23 Oct 2022 10:34:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230266AbiJWOdq (ORCPT ); Sun, 23 Oct 2022 10:33:46 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EF98625F9; Sun, 23 Oct 2022 07:33:43 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id jb18so1680273wmb.4; Sun, 23 Oct 2022 07:33:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iboSBornxxq5IGUmNwjcHJMSvR6JYlZCJH/3I/odZvU=; b=a0DWRLL2JY+JO6dqzjcB2ClTvgkWANjY32AL4ej94RFeRL2DR4yLJU5Ipl7ijWc5+Q HvylTzAJXnREsUmtZnWTse1fmSC3mej7u2CcEQMxQ25Dr9o7Tlar6iRmG4G2DSpUHDQy xZ0YThOx9tX3gALv7DdT/TOjk/O4nF04jN491r7vLGOUFJEKVpZYdcBf24sHLLJ0QoVX 5VyChncf0aZGHuAsLJXRl+eiMa/gWfBVcvFe4h/Vp7ILOca0BIPmaLz2pc8xuqEKoI66 axspR8iYJhkvddtzbSVExcoGoTQXf4PjmoUAGtDIormS5Uoc/tvOdFl0maAcEOZFI8GV h7XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iboSBornxxq5IGUmNwjcHJMSvR6JYlZCJH/3I/odZvU=; b=ZI9waAoFpyi59H5jZ0C0Cf2fUwSFa5TtFzMYLatNBIh8QxSRDdpJA4odM4M7xiiVRq /a2uqTtwl3cqzw0E0fYKe5wd+sANbNHBaQ0T5hgIl8gS+yooBW85+NsUbsl8yTReckok V1dyJnrjgZMjSG7iDtUmQie9XK/mWow64VIQ7N2pkvKwhuo5FiFMiLWY6fZQe7SEgVuS gXbg8pc877qKiObbnl9/DN/2y0a49BbwgCoGYzPWrImqDdQN3PGZYMRfkG7SUsvgfKYS 6zxa1Jcc6P3u4wc8rVPztTHqmhZD4gN5TMeYlQLptr0FOieVHtfmuiqtOSnou1J+BLc6 0pEQ== X-Gm-Message-State: ACrzQf1/0pIpn+jQmHmisEjYW0OXi+osj21CCYZZpCGvAD6BT4tSbYvc z5C6Bia7d5feSmBqzYiOGVDJy1Inv9Y= X-Google-Smtp-Source: AMsMyM7DlAGa7a2TLSa3QPg8ZAlyQYGmx4u/u3+GoUMF45yau24RIk4RLOslbpLSt+vgtP9nqoRrTA== X-Received: by 2002:a05:600c:3147:b0:3c6:f871:1fec with SMTP id h7-20020a05600c314700b003c6f8711fecmr19700599wmo.71.1666535621633; Sun, 23 Oct 2022 07:33:41 -0700 (PDT) Received: from localhost (94.197.10.75.threembb.co.uk. [94.197.10.75]) by smtp.gmail.com with ESMTPSA id b13-20020a5d4d8d000000b0023660f6cecfsm3702290wru.80.2022.10.23.07.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:33:41 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 8/9] ASoC: jz4740-i2s: Move component functions near the component driver Date: Sun, 23 Oct 2022 15:33:27 +0100 Message-Id: <20221023143328.160866-9-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> References: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Move the component suspend/resume functions near the definition of the component driver to emphasize that they're unrelated to the DAI functions. Acked-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 72 +++++++++++++++++------------------ 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 201368f828ff..ac04b17c2787 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -302,42 +302,6 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, return ret; } -static int jz4740_i2s_suspend(struct snd_soc_component *component) -{ - struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - - if (snd_soc_component_active(component)) { - regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); - clk_disable_unprepare(i2s->clk_i2s); - } - - clk_disable_unprepare(i2s->clk_aic); - - return 0; -} - -static int jz4740_i2s_resume(struct snd_soc_component *component) -{ - struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); - int ret; - - ret = clk_prepare_enable(i2s->clk_aic); - if (ret) - return ret; - - if (snd_soc_component_active(component)) { - ret = clk_prepare_enable(i2s->clk_i2s); - if (ret) { - clk_disable_unprepare(i2s->clk_aic); - return ret; - } - - regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); - } - - return 0; -} - static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); @@ -454,6 +418,42 @@ static const struct i2s_soc_info jz4780_i2s_soc_info = { .field_i2sdiv_playback = REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), }; +static int jz4740_i2s_suspend(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + + if (snd_soc_component_active(component)) { + regmap_clear_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); + clk_disable_unprepare(i2s->clk_i2s); + } + + clk_disable_unprepare(i2s->clk_aic); + + return 0; +} + +static int jz4740_i2s_resume(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + int ret; + + ret = clk_prepare_enable(i2s->clk_aic); + if (ret) + return ret; + + if (snd_soc_component_active(component)) { + ret = clk_prepare_enable(i2s->clk_i2s); + if (ret) { + clk_disable_unprepare(i2s->clk_aic); + return ret; + } + + regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); + } + + return 0; +} + static const struct snd_soc_component_driver jz4740_i2s_component = { .name = "jz4740-i2s", .suspend = jz4740_i2s_suspend, From patchwork Sun Oct 23 14:33:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 13016283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45985ECAAA1 for ; Sun, 23 Oct 2022 14:34:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230226AbiJWOeL (ORCPT ); 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[94.197.10.75]) by smtp.gmail.com with ESMTPSA id o13-20020adfcf0d000000b0022cce7689d3sm7614395wrj.36.2022.10.23.07.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Oct 2022 07:33:42 -0700 (PDT) From: Aidan MacDonald To: paul@crapouillou.net, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com Cc: zhouyu@wanyeetech.com, linux-mips@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 9/9] ASoC: jz4740-i2s: Refactor DAI probe/remove ops as component ops Date: Sun, 23 Oct 2022 15:33:28 +0100 Message-Id: <20221023143328.160866-10-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> References: <20221023143328.160866-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Move most of the DAI probe/remove logic into component ops. This makes things more consistent because the AIC clock is now managed solely from the component side. And it makes it easier to add codec switching support later on. Reviewed-by: Paul Cercueil Signed-off-by: Aidan MacDonald --- sound/soc/jz4740/jz4740-i2s.c | 54 +++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 24 deletions(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index ac04b17c2787..b620d4462d90 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -305,32 +305,10 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai) { struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - int ret; - - ret = clk_prepare_enable(i2s->clk_aic); - if (ret) - return ret; snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data, &i2s->capture_dma_data); - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); - - regmap_write(i2s->regmap, JZ_REG_AIC_CONF, - JZ_AIC_CONF_OVERFLOW_PLAY_LAST | - JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); - - regmap_field_write(i2s->field_rx_fifo_thresh, 7); - regmap_field_write(i2s->field_tx_fifo_thresh, 8); - - return 0; -} - -static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai) -{ - struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai); - - clk_disable_unprepare(i2s->clk_aic); return 0; } @@ -350,7 +328,6 @@ static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = { static struct snd_soc_dai_driver jz4740_i2s_dai = { .probe = jz4740_i2s_dai_probe, - .remove = jz4740_i2s_dai_remove, .playback = { .channels_min = 1, .channels_max = 2, @@ -386,7 +363,6 @@ static const struct i2s_soc_info jz4760_i2s_soc_info = { static struct snd_soc_dai_driver jz4770_i2s_dai = { .probe = jz4740_i2s_dai_probe, - .remove = jz4740_i2s_dai_remove, .playback = { .channels_min = 1, .channels_max = 2, @@ -454,8 +430,38 @@ static int jz4740_i2s_resume(struct snd_soc_component *component) return 0; } +static int jz4740_i2s_probe(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + int ret; + + ret = clk_prepare_enable(i2s->clk_aic); + if (ret) + return ret; + + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET); + + regmap_write(i2s->regmap, JZ_REG_AIC_CONF, + JZ_AIC_CONF_OVERFLOW_PLAY_LAST | + JZ_AIC_CONF_I2S | JZ_AIC_CONF_INTERNAL_CODEC); + + regmap_field_write(i2s->field_rx_fifo_thresh, 7); + regmap_field_write(i2s->field_tx_fifo_thresh, 8); + + return 0; +} + +static void jz4740_i2s_remove(struct snd_soc_component *component) +{ + struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component); + + clk_disable_unprepare(i2s->clk_aic); +} + static const struct snd_soc_component_driver jz4740_i2s_component = { .name = "jz4740-i2s", + .probe = jz4740_i2s_probe, + .remove = jz4740_i2s_remove, .suspend = jz4740_i2s_suspend, .resume = jz4740_i2s_resume, .legacy_dai_naming = 1,