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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:41:42.3958 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af504a6a-3b1e-445b-01a4-08dab59331c0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT087.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5188 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Extend the Tegra XUSB controller device tree binding with Tegra234 support. Signed-off-by: Wayne Chang --- .../bindings/usb/nvidia,tegra-xudc.yaml | 24 ++++++++++++------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index fd6e7c81426e..517fb692f199 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -22,6 +22,7 @@ properties: - nvidia,tegra210-xudc # For Tegra210 - nvidia,tegra186-xudc # For Tegra186 - nvidia,tegra194-xudc # For Tegra194 + - nvidia,tegra234-xudc # For Tegra234 reg: minItems: 2 @@ -90,21 +91,27 @@ properties: phys: minItems: 1 + maxItems: 8 description: Must contain an entry for each entry in phy-names. See ../phy/phy-bindings.txt for details. phy-names: minItems: 1 + maxItems: 8 items: - - const: usb2-0 - - const: usb2-1 - - const: usb2-2 - - const: usb2-3 - - const: usb3-0 - - const: usb3-1 - - const: usb3-2 - - const: usb3-3 + anyOf: + - const: usb2-0 + - const: usb2-1 + - const: usb2-2 + - const: usb2-3 + - const: usb3-0 + - const: usb3-1 + - const: usb3-2 + - const: usb3-3 + + dma-coherent: + type: boolean avddio-usb-supply: description: PCIe/USB3 analog logic power supply. Must supply 1.05 V. @@ -153,6 +160,7 @@ allOf: enum: - nvidia,tegra186-xudc - nvidia,tegra194-xudc + - nvidia,tegra234-xudc then: properties: reg: From patchwork Mon Oct 24 07:41:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 13016781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07441FA373D for ; Mon, 24 Oct 2022 07:42:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229944AbiJXHl7 (ORCPT ); Mon, 24 Oct 2022 03:41:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229915AbiJXHlz (ORCPT ); Mon, 24 Oct 2022 03:41:55 -0400 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2047.outbound.protection.outlook.com [40.107.243.47]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA6955BC8A; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:41:45.4371 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc1604bd-489e-4d03-4e0c-08dab593338b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT096.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7671 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add device-tree binding documentation for the XUSB host controller present on Tegra194 and Tegra234 SoC. This controller supports the USB 3.1 specification. Signed-off-by: Wayne Chang --- .../bindings/usb/nvidia,tegra-xhci.yaml | 213 ++++++++++++++++++ 1 file changed, 213 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml new file mode 100644 index 000000000000..d261a419a04f --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.yaml @@ -0,0 +1,213 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/nvidia,tegra-xhci.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree binding for NVIDIA Tegra XUSB host controller + +description: + The Tegra XHCI controller supports both USB 2.0 HighSpeed/FullSpeed and + USB 3.1 SuperSpeed protocols. + +maintainers: + - Wayne Chang + +properties: + compatible: + items: + - enum: + - nvidia,tegra194-xusb # For Tegra194 + - nvidia,tegra234-xusb # For Tegra234 + + reg: + minItems: 2 + items: + - description: XUSB host controller registers + - description: XUSB host PCI Config registers + - description: XUSB host bar2 registers + + reg-names: + minItems: 2 + items: + - const: hcd + - const: fpci + - const: bar2 + + interrupts: + items: + - description: Must contain the XUSB host interrupt. + - description: Must contain the XUSB mbox interrupt. + + clocks: + items: + - description: Clock to enable core XUSB host clock. + - description: Clock to enable XUSB falcon clock. + - description: Clock to enable XUSB super speed clock. + - description: Clock to enable XUSB super speed dev clock. + - description: Clock to enable XUSB high speed dev clock. + - description: Clock to enable XUSB full speed dev clock. + - description: Clock to enable XUSB UTMI PLL clock. + - description: Clock to enable core XUSB dev clock. + - description: Clock to enable XUSB PLLE clock. + + clock-names: + items: + - const: xusb_host + - const: xusb_falcon_src + - const: xusb_ss + - const: xusb_ss_src + - const: xusb_hs_src + - const: xusb_fs_src + - const: pll_u_480m + - const: clk_m + - const: pll_e + + interconnects: + items: + - description: memory read client + - description: memory write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + power-domains: + items: + - description: XUSBC(host) power-domain + - description: XUSBA(superspeed) power-domain + + power-domain-names: + items: + - const: xusb_host + - const: xusb_ss + + nvidia,xusb-padctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the XUSB pad controller that is used to configure the USB pads + used by the XUDC controller. + + phys: + minItems: 1 + maxItems: 8 + description: + Must contain an entry for each entry in phy-names. + See ../phy/phy-bindings.txt for details. + + phy-names: + minItems: 1 + maxItems: 8 + items: + anyOf: + - const: usb2-0 + - const: usb2-1 + - const: usb2-2 + - const: usb2-3 + - const: usb3-0 + - const: usb3-1 + - const: usb3-2 + - const: usb3-3 + + dma-coherent: + type: boolean + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - power-domains + - power-domain-names + - nvidia,xusb-padctl + - phys + - phy-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-xusb + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + clocks: + minItems: 9 + clock-names: + minItems: 9 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-xusb + then: + properties: + reg: + minItems: 3 + reg-names: + minItems: 3 + clocks: + minItems: 9 + clock-names: + minItems: 9 + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + usb@3610000 { + compatible = "nvidia,tegra234-xusb"; + reg = <0x03610000 0x40000>, + <0x03600000 0x10000>, + <0x03650000 0x10000>; + reg-names = "hcd", "fpci", "bar2"; + + interrupts = , + ; + + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA234_CLK_XUSB_FALCON>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_XUSB_FS>, + <&bpmp TEGRA234_CLK_UTMIP_PLL>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + + phys = <&pad_lanes_usb2_0>; + phy-names = "usb2-0"; + + }; From patchwork Mon Oct 24 07:41:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 13016782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5757AFA373F for ; Mon, 24 Oct 2022 07:42:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229994AbiJXHmU (ORCPT ); Mon, 24 Oct 2022 03:42:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229954AbiJXHmJ (ORCPT ); Mon, 24 Oct 2022 03:42:09 -0400 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam07on2043.outbound.protection.outlook.com [40.107.212.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C082860E85; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:01.7153 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98d1f769-0bd6-4fc5-c54a-08dab5933d3c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7654 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org add device-tree binding documentation for Cypress cypd4226 type-C controller's I2C interface. It is a standard i2c slave with GPIO input as IRQ interface. Signed-off-by: Wayne Chang --- .../bindings/usb/cypress,cypd4226.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml diff --git a/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml b/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml new file mode 100644 index 000000000000..5ac28ab4e7a1 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cypress,cypd4226.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cypress cypd4226 UCSI I2C Type-C Controller + +maintainers: + - Wayne Chang + +description: | + The Cypress cypd4226 UCSI I2C type-C controller is a I2C interface type-C + controller. + +properties: + compatible: + const: cypress,cypd4226 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + const: 0x08 + + interrupts: + maxItems: 1 + + cypress,firmware-build: + enum: + - nv + - gn + description: | + the name of the CCGx firmware built for product series. + should be set one of following: + - "nv" for the RTX product series + - "gn" for the Jetson product series + +patternProperties: + '^connector@[0-9a-f]+$': + $ref: /schemas/connector/usb-connector.yaml# + properties: + reg: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: true + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <2>; + + ucsi_ccg: ucsi_ccg@8 { + compatible = "cypress,cypd4226"; + interrupt-parent = <&gpio_aon>; + interrupts = ; + reg = <0x08>; + cypress,firmware-build = "gn"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + ccg_typec_con0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "dual"; + port { + ucsi_ccg_p0: endpoint { + remote-endpoint = <&usb_role_switch0>; + }; + }; + }; + }; + }; From patchwork Mon Oct 24 07:41:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 13016790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE653FA373F for ; Mon, 24 Oct 2022 07:44:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230082AbiJXHob (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:07.7031 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2cc9531a-2032-4b9b-9702-08dab59340d5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4223 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org This commit enables XUSB host, device, and pad controller on Jetson AGX Orin. Signed-off-by: Wayne Chang --- .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 48 +++++ .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 184 ++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 170 ++++++++++++++++ 3 files changed, 402 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index 9e4d72cfa69f..8acef87a5398 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -61,6 +61,29 @@ mmc@3460000 { non-removable; }; + padctl@3520000 { + vclamp-usb-supply = <&vdd_ao_1v8>; + avdd-usb-supply = <&vdd_ao_3v3>; + + ports { + usb2-0 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-1 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-2 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-3 { + vbus-supply = <&vdd_5v0_sys>; + }; + }; + }; + rtc@c2a0000 { status = "okay"; }; @@ -69,4 +92,29 @@ pmc@c360000 { nvidia,invert-interrupt; }; }; + + vdd_5v0_sys: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VIN_SYS_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ao_1v8: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vdd-AO-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_ao_3v3: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vdd-AO-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 57ab75328814..b4630280bb32 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2011,6 +2011,190 @@ hda@3510000 { nvidia,model = "NVIDIA Jetson AGX Orin HDA"; status = "okay"; }; + + padctl@3520000 { + status = "okay"; + + pads { + usb2 { + lanes { + usb2-0 { + status = "okay"; + }; + + usb2-1 { + status = "okay"; + }; + + usb2-2 { + status = "okay"; + }; + + usb2-3 { + status = "okay"; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + status = "okay"; + }; + + usb3-1 { + status = "okay"; + }; + + usb3-2 { + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + mode = "otg"; + usb-role-switch; + status = "okay"; + port { + hs_typec_p1: endpoint { + remote-endpoint = <&hs_ucsi_ccg_p1>; + }; + }; + }; + + usb2-1 { + mode = "host"; + status = "okay"; + port { + hs_typec_p0: endpoint { + remote-endpoint = <&hs_ucsi_ccg_p0>; + }; + }; + }; + + usb2-2 { + mode = "host"; + status = "okay"; + }; + + usb2-3 { + mode = "host"; + status = "okay"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + status = "okay"; + port { + ss_typec_p0: endpoint { + remote-endpoint = <&ss_ucsi_ccg_p0>; + }; + }; + }; + + usb3-1 { + nvidia,usb2-companion = <0>; + status = "okay"; + port { + ss_typec_p1: endpoint { + remote-endpoint = <&ss_ucsi_ccg_p1>; + }; + }; + }; + + usb3-2 { + nvidia,usb2-companion = <3>; + status = "okay"; + }; + }; + }; + + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb3-1"; + }; + + usb@3610000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", + "usb3-0", "usb3-1", "usb3-2"; + }; + + i2c@c240000 { + status = "okay"; + ucsi_ccg: ucsi_ccg@8 { + compatible = "cypress,cypd4226"; + cypress,firmware-build = "gn"; + interrupt-parent = <&gpio>; + interrupts = ; + reg = <0x08>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + ccg_typec_con0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "host"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + hs_ucsi_ccg_p0: endpoint { + remote-endpoint = <&hs_typec_p0>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + ss_ucsi_ccg_p0: endpoint { + remote-endpoint = <&ss_typec_p0>; + }; + }; + }; + ccg_typec_con1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "USB-C"; + data-role = "dual"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + hs_ucsi_ccg_p1: endpoint { + remote-endpoint = <&hs_typec_p1>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + ss_ucsi_ccg_p1: endpoint { + remote-endpoint = <&ss_typec_p1>; + }; + }; + }; + }; + }; }; chosen { diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 0170bfa8a467..27635d459e4c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -942,6 +942,174 @@ hda@3510000 { status = "disabled"; }; + xusb_padctl: padctl@3520000 { + compatible = "nvidia,tegra234-xusb-padctl"; + reg = <0x03520000 0x20000>, + <0x03540000 0x10000>; + reg-names = "padctl", "ao"; + interrupts = ; + + resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + status = "disabled"; + + pads { + usb2 { + clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + status = "disabled"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; + + usb@3550000 { + compatible = "nvidia,tegra234-xudc"; + reg = <0x03550000 0x8000>, + <0x03558000 0x8000>; + reg-names = "base", "fpci"; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; + status = "disabled"; + }; + + usb@3610000 { + compatible = "nvidia,tegra234-xusb"; + reg = <0x03610000 0x40000>, + <0x03600000 0x10000>, + <0x03650000 0x10000>; + reg-names = "hcd", "fpci", "bar2"; + + interrupts = , + ; + + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA234_CLK_XUSB_FALCON>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_XUSB_FS>, + <&bpmp TEGRA234_CLK_UTMIP_PLL>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; + status = "disabled"; + }; + fuse@3810000 { compatible = "nvidia,tegra234-efuse"; reg = <0x03810000 0x10000>; @@ -1470,6 +1638,8 @@ gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; reg = <0xc240000 0x100>; interrupts = ; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C2 From patchwork Mon Oct 24 07:41:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 13016784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C29E8FA373D for ; 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Mon, 24 Oct 2022 00:41:52 -0700 From: Wayne Chang To: , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH 05/11] usb: typec: ucsi_ccg: Add OF support Date: Mon, 24 Oct 2022 15:41:22 +0800 Message-ID: <20221024074128.1113554-6-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024074128.1113554-1-waynec@nvidia.com> References: <20221024074128.1113554-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT041:EE_|LV2PR12MB5822:EE_ X-MS-Office365-Filtering-Correlation-Id: df9f90be-f8b8-40bc-7594-08dab5933fdf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: u/KFS+WBNTkE4Ut33q5VMEVgR81wuoLN7FqrBYG3Ot5J3iXI2tiV6nYkz0GLmyNy60rrqfGwsZYwN/N2fOdDSYU5p8eoKDjsdVk78uC+BqzSd6nP5NtXqVxSQQhiu/r8hTmQyhjWZHFFj464/QK9Ez6vXJSneWDaSf3G0dJuNDYMRXkbTgFWFOI/Fa+MeuFbZfF6DRaYX/XwR96PepzSdt8FJhSLuBa6Gvo0Y61bi7bBmf1iuVm7ek0M2wQwKEK47Rd9J8j73Xzm6zBSr+oUjJ86Zcp3dDPXHFtyZZJhnaCgHtPz7QUnggFv4ET4cWP+Obyvj2pJqpFx10XQAU2xfVJ8WsKPloi2GZYOnUqmiUZ8L4NotP/VCGjXw2w6IhUMA6PIWWHCvQ8/bz2GByAdcyaE+Duswua+o+n7hCJU0IDHfqvwpvJtGcZFeg9zkZtyF3i62/YBn4LPkGMqY4vn5Ow+3jVrPsgYTobzuAijv7npAc8lGLwNnegBucejWOqH1Q7qo0Ney0Mrql455iHXdDSilA4nArWFojwwrF3J2l3pijiB7KMq41JlW+NRBfZsFzho2cXPf7yyhdFNte8MFhhx8MML7bWrEc3ZTyX2qs7q08eCut+J8AxpDcqpxAuMAw0/GuWE/Bbkp2H/Y7rRujSfApDmYtCEGWcIxi9oxVDfVjVFEw/mx36cbs5aO59oB9cn9yatf2hivjrfjGLhkQlSQf3Vsj4DWcsr0iS0ltKdhbpJcZw9L5aRua6Bmr3Kwh2ctBIq12BCNEuYlaYbsUt+qf6x4CC1ps6LGcC93mo= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(346002)(39860400002)(396003)(376002)(451199015)(36840700001)(46966006)(40470700004)(8936002)(2616005)(54906003)(40460700003)(186003)(7696005)(36860700001)(426003)(47076005)(26005)(6666004)(40480700001)(7416002)(1076003)(6636002)(5660300002)(82310400005)(316002)(70586007)(110136005)(70206006)(41300700001)(478600001)(8676002)(4326008)(83380400001)(336012)(2906002)(921005)(36756003)(82740400003)(86362001)(7636003)(356005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:06.1213 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df9f90be-f8b8-40bc-7594-08dab5933fdf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5822 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The change enables the device tree infrastructure support. Signed-off-by: Wayne Chang --- drivers/usb/typec/ucsi/ucsi_ccg.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/typec/ucsi/ucsi_ccg.c b/drivers/usb/typec/ucsi/ucsi_ccg.c index 835f1c4372ba..139707a2f3d6 100644 --- a/drivers/usb/typec/ucsi/ucsi_ccg.c +++ b/drivers/usb/typec/ucsi/ucsi_ccg.c @@ -643,7 +643,7 @@ static int ccg_request_irq(struct ucsi_ccg *uc) { unsigned long flags = IRQF_ONESHOT; - if (!has_acpi_companion(uc->dev)) + if (!dev_fwnode(uc->dev)) flags |= IRQF_TRIGGER_HIGH; return request_threaded_irq(uc->irq, NULL, ccg_irq_handler, flags, dev_name(uc->dev), uc); @@ -1427,6 +1427,12 @@ static void ucsi_ccg_remove(struct i2c_client *client) free_irq(uc->irq, uc); } +static const struct of_device_id ucsi_ccg_of_match_table[] = { + { .compatible = "cypress,cypd4226", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ucsi_ccg_of_match_table); + static const struct i2c_device_id ucsi_ccg_device_id[] = { {"ccgx-ucsi", 0}, {} @@ -1481,6 +1487,7 @@ static struct i2c_driver ucsi_ccg_driver = { .pm = &ucsi_ccg_pm, .dev_groups = ucsi_ccg_groups, .acpi_match_table = amd_i2c_ucsi_match, + .of_match_table = ucsi_ccg_of_match_table, }, .probe = ucsi_ccg_probe, .remove = ucsi_ccg_remove, From patchwork Mon Oct 24 07:41:23 2022 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:08.5118 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02e7cddf-5bf6-4740-c1b5-08dab5934155 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6863 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org ccgx is refer to the cypress cypd4226 typec controller. Replace ccgx to well-known regex "cypress". Signed-off-by: Wayne Chang --- drivers/usb/typec/ucsi/ucsi_ccg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/typec/ucsi/ucsi_ccg.c b/drivers/usb/typec/ucsi/ucsi_ccg.c index 139707a2f3d6..5d3099e6eb77 100644 --- a/drivers/usb/typec/ucsi/ucsi_ccg.c +++ b/drivers/usb/typec/ucsi/ucsi_ccg.c @@ -1358,7 +1358,7 @@ static int ucsi_ccg_probe(struct i2c_client *client, INIT_WORK(&uc->pm_work, ccg_pm_workaround_work); /* Only fail FW flashing when FW build information is not provided */ - status = device_property_read_u16(dev, "ccgx,firmware-build", + status = device_property_read_u16(dev, "cypress,firmware-build", &uc->fw_build); if (status) dev_err(uc->dev, "failed to get FW build information\n"); From patchwork Mon Oct 24 07:41:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 13016785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E27ECC38A2D for ; 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Mon, 24 Oct 2022 00:41:59 -0700 From: Wayne Chang To: , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH 07/11] i2c: nvidia-gpu: Replace ccgx to well-known regex Date: Mon, 24 Oct 2022 15:41:24 +0800 Message-ID: <20221024074128.1113554-8-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024074128.1113554-1-waynec@nvidia.com> References: <20221024074128.1113554-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT087:EE_|CH2PR12MB4199:EE_ X-MS-Office365-Filtering-Correlation-Id: 821a76a5-297f-4167-afd3-08dab593422d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: awsvsxhX3GX0baoJMZfFpPwrQe0P3DTdUEESirzhPYV8PnxkUoSIVEWT6a+3eEYXQ7YU6KpWbOAcFI/Yog0mLJ2QmulK6GFjjXRdO6/YWkABf57DlnPC4rv7h0p0dxQF20y6tU4Clvyd3BPCQXRd5Tuyei+jY6iXyZuhoswwzpkvHaYQUdfrLrT/m3OnKA05/nwU5njEErPzkRfRIJhLvZBABUutkbbcYvLzbDt5H19NhXXUp14qkuemgWo2z9gzffjekMkBTsqEGUI2jovG480Mp5cHBOxnSHolyyFA+8QOZnRv1QcOjjnQ+pAJJhsg53gbqvGQc0K0lQnlHAeRygwHTP0ydNJWPxrbHqbSm10Gj0aq6TWDy3XpB1dj/nO2qTHiDswz/dN0hFreyGojRZQ9P1ttLuFsN6YAEgraEwKHZ92RmEisI6lUqb6UM9MxDEXoyfRj9TG3SLO+tgRSkXugjKlGDasPssuuFRs04oiHLpiKCLDjWbYJkTTUy/hKi/HCEqsj/33/+nnBod5UDwR0C59rcBEXPUNCNlWeWgW5olBoqpy7rN+B4xpI8hk1Ea0GtfFQZCZ8mKNaWoir3RRLzO2SIukWzQ+OJiMq3kDAD52VcCImVwwXrXHItwKq7xTzfqAFw7Os6riEKRXIs8tRMmSEFEKqSRNhmwTaGNKLyfyJ9qNYTt+LItHm15EpUTXzfMRLUA8usR1mxdI+lxQ/fnL3IaT10nLtJzMwaObOAeqJ+b9Kqe54VFyZ8PVfALpKhPPb0yUkhoslvfn8qYoQAbChKee+n9odnx1fTok= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(376002)(396003)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(6666004)(2616005)(26005)(7696005)(1076003)(36860700001)(426003)(47076005)(336012)(186003)(83380400001)(4744005)(2906002)(7416002)(40480700001)(40460700003)(82310400005)(6636002)(54906003)(110136005)(316002)(478600001)(41300700001)(5660300002)(8936002)(70206006)(70586007)(4326008)(8676002)(86362001)(36756003)(82740400003)(921005)(7636003)(356005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:10.0050 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 821a76a5-297f-4167-afd3-08dab593422d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT087.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4199 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org ccgx is refer to the cypress cypd4226 typec controller. Replace ccgx to well-known regex "cypress". Signed-off-by: Wayne Chang --- drivers/i2c/busses/i2c-nvidia-gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-nvidia-gpu.c b/drivers/i2c/busses/i2c-nvidia-gpu.c index 12e330cd7635..0934f8ad7f49 100644 --- a/drivers/i2c/busses/i2c-nvidia-gpu.c +++ b/drivers/i2c/busses/i2c-nvidia-gpu.c @@ -260,7 +260,7 @@ MODULE_DEVICE_TABLE(pci, gpu_i2c_ids); static const struct property_entry ccgx_props[] = { /* Use FW built for NVIDIA (nv) only */ - PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'), + PROPERTY_ENTRY_U16("cypress,firmware-build", ('n' << 8) | 'v'), { } }; From patchwork Mon Oct 24 07:41:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 13016789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60ECCFA374C for ; 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Mon, 24 Oct 2022 00:42:03 -0700 From: Wayne Chang To: , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH 08/11] phy: tegra: xusb: Disable trk clk when not using Date: Mon, 24 Oct 2022 15:41:25 +0800 Message-ID: <20221024074128.1113554-9-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024074128.1113554-1-waynec@nvidia.com> References: <20221024074128.1113554-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT072:EE_|BY5PR12MB4131:EE_ X-MS-Office365-Filtering-Correlation-Id: 855dc428-fa93-43d2-dc96-08dab5934897 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ASfFp+QFYC7IKUX6CfH+Ge6bN7obcRYYg11RmgdFsOTJrtV2HjTBELvV9hKK5z1yMltFFFZkgZG9SpBAcAEIUNQlgRs/jcG3flo3Nz7ZXmQ0vYF/2ifz9WeEmv+7ubA+MXKcyDqmI1RAi7uBgxJGlBZ2Oq7lxrcb8sNgOwu9fGWorN4Gl/qKEdjhA+JMJF10zstEc13ZaoEzZAbQ22KQicOBIOUIpKirbMV1HGXWaT0Eoyzl5g+/wMKy7ps5I1x+4J1767P7YE17tUEj1Li9rfz0IKvvAADTUZoQj38Pv069+dRHnVl80X3BDOC4D0ILSZiyzBmIGIQTo7Hu7hurbQX54rNO76W8wSYDLpyWMFGWAXVvIoF0qc51ZLJg8nhTF4svUub54TAroCz7LuxYvJR3agL0DsKXKtxViVaDDoyfFIt+R4xShZ16kH7zewW/Mtuy+DLo+yzhnQQ4Rgh6Edy8j2WnKm3ipkKW9T3LZRPiC03AphRXh/Q6RlvG0R19hhRZfNb5V9T0QBK/UCdOf2isRnRxGe7n7lBmv8Ln0iB0U2TUUH3EReqbwmhUdxevk4aAXg3Nl9GSJ0do3XbBv4EE3wT6MrNn5t7GSgZzE+IMEBlGa7UbRu6p/X552I4aaMtdjs7kyplvsTt1OeOC1cEsTqbzrTdGIDxtUCBRx03i3X391gKbIqdjmVO3OMd+x4zjNtv2G0tTx/FdwaNwnDEzX3JoWxcLXIlLZvxHqWPlpb+chLMMxFno1I74j3vnkwRdEBDWz4rFwqH4UlSZmy/kURFvgyZ2GxY3Tq2Twxs= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(376002)(346002)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(82310400005)(40480700001)(2906002)(8936002)(82740400003)(47076005)(426003)(5660300002)(6636002)(7636003)(356005)(921005)(2616005)(7416002)(41300700001)(110136005)(54906003)(26005)(316002)(6666004)(36756003)(186003)(1076003)(36860700001)(86362001)(336012)(83380400001)(7696005)(478600001)(70206006)(70586007)(8676002)(4326008)(40460700003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:20.7203 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 855dc428-fa93-43d2-dc96-08dab5934897 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT072.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4131 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The change fixes an issue that the pad tracking is a one-time calibration for Tegra186 and Tegra194. We should disable the clk when it is done. The 100us delay is for HW recording the calibration value. Signed-off-by: Wayne Chang --- drivers/phy/tegra/xusb-tegra186.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index 0996ede63387..f121b4ffbbfd 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -609,6 +609,10 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) value &= ~USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + udelay(100); + + clk_disable_unprepare(priv->usb2_trk_clk); + mutex_unlock(&padctl->lock); } @@ -633,8 +637,6 @@ static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) value |= USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - clk_disable_unprepare(priv->usb2_trk_clk); - mutex_unlock(&padctl->lock); } From patchwork Mon Oct 24 07:41:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 13016787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5189AFA3748 for ; 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Mon, 24 Oct 2022 00:42:06 -0700 From: Wayne Chang To: , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH 09/11] phy: tegra: xusb: Add Tegra234 support Date: Mon, 24 Oct 2022 15:41:26 +0800 Message-ID: <20221024074128.1113554-10-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024074128.1113554-1-waynec@nvidia.com> References: <20221024074128.1113554-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT015:EE_|CH2PR12MB5020:EE_ X-MS-Office365-Filtering-Correlation-Id: bf6e61b6-4eb1-48e9-2657-08dab5934920 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NVLixrIzIppHSasxMK9iD8GLgNcrzZP7v2V/aYF9yNuYzQK5YZQsg68z7oX2XDo0nRAcPTSBlK2VOTNtAs5bXcsSVE/cQmjKo2HZM+Cr3sAkuZnRn/njipBIg+61gDSE4FixFviTnR8F4r5B1uuw1SzqRnGlj39NDNQlaV5loxTLG/SclZkPAEJgBhbeSgz7JWezvrao0MqNaTY/6/3KxkDviegF/B9X9j8hqt42mxyGpzGNPTDhkyO0cAdeROK8U4gDpVCk/Ym1SVWjJTBCFCrIUAe7hZ6yvnPgAyV5nTRBXtcqtArEFoHF0v+pOf6Wt/+WnBhC2T5xpOjaE2EoHozzcGfSjrambDVAYPWI9N8Bp3XWdnDJ03iHzH3kWgzYpRtBkoaPcLXHPzl4rMHAKSkbQOX5kylunWCh4uIDXE+EyXfUIhwRDCiyiHfnuKs39HBTTAyaWfSqBuUR/CI4ekU6kwPgEtzGOHidUKPqAlutGDGKsJu4XeYcZKZqUk6GW+qkFkbTNbK8OSUEt1972VjLtHd7JkGUYBWoGaUa1z7VFg9k6FPTvArI92zEMIpqMICmnHYB1Q7XIqQYRUXfBuf3m8dkViLKNMQK56cGyW3cslZXmVBGQRpE54GpFtzU2yzCTBN9iExMWOwzSuF5KAC1VMslZH6/1ZIRiu0+ZiiQzF0FpvyZ6YsEnVf5Nt51a3fwdsdtyNFpP8XhOLHtRTOkBlst2qerEMuB2u2C+75ByF7kkoAIWB1ldOyB4m+npjtneH1rQwuFzEcqxNXUlxZzZOtN8pxeBNQflO++5EA= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(396003)(346002)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(47076005)(426003)(186003)(1076003)(336012)(40480700001)(6666004)(2906002)(86362001)(356005)(921005)(7636003)(36756003)(40460700003)(82740400003)(82310400005)(83380400001)(7696005)(26005)(4326008)(36860700001)(2616005)(316002)(8676002)(478600001)(6636002)(41300700001)(110136005)(70586007)(5660300002)(7416002)(8936002)(54906003)(70206006);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:21.6604 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf6e61b6-4eb1-48e9-2657-08dab5934920 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB5020 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sing-Han Chen Add support for the XUSB pad controller found on Tegra234 SoCs. It is mostly similar to the same IP found on Tegra194, because most of the Tegra234 XUSB PADCTL registers definition and programming sequence are the same as Tegra194, Tegra234 XUSB PADCTL can share the same driver with Tegra186 and Tegra194 XUSB PADCTL. Introduce a new feature, USB2 HW tracking, for Tegra234. The feature is to enable HW periodical PAD tracking which measure and capture the electric parameters of USB2.0 PAD. Signed-off-by: Sing-Han Chen Co-developed-by: Wayne Chang Signed-off-by: Wayne Chang --- drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 65 +++++++++++++++++++++++++++++-- drivers/phy/tegra/xusb.c | 6 +++ drivers/phy/tegra/xusb.h | 23 +++++++++++ 4 files changed, 92 insertions(+), 3 deletions(-) diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile index 89b84067cb4c..eeeea72de117 100644 --- a/drivers/phy/tegra/Makefile +++ b/drivers/phy/tegra/Makefile @@ -7,4 +7,5 @@ phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_234_SOC) += xusb-tegra186.o obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index f121b4ffbbfd..cc02cea65a21 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -89,6 +89,11 @@ #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12) #define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19) #define USB2_PD_TRK BIT(26) +#define USB2_TRK_COMPLETED BIT(31) + +#define XUSB_PADCTL_USB2_BIAS_PAD_CTL2 0x28c +#define USB2_TRK_HW_MODE BIT(0) +#define CYA_TRK_CODE_UPDATE_ON_IDLE BIT(31) #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20) #define HSIC_PD_TX_DATA0 BIT(1) @@ -609,9 +614,32 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) value &= ~USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); - udelay(100); + if (padctl->soc->poll_trk_completed) { + err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, + USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, 100); + if (err) { + /* The failure with polling on trk complete will not + * cause the failure of powering on the bias pad. + */ + dev_warn(dev, "failed to poll USB2 trk completed: %d\n", + err); + } - clk_disable_unprepare(priv->usb2_trk_clk); + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + value |= USB2_TRK_COMPLETED; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + } else { + udelay(100); + } + + if (padctl->soc->trk_hw_mode) { + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + value |= USB2_TRK_HW_MODE; + value &= ~CYA_TRK_CODE_UPDATE_ON_IDLE; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + } else { + clk_disable_unprepare(priv->usb2_trk_clk); + } mutex_unlock(&padctl->lock); } @@ -637,6 +665,13 @@ static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) value |= USB2_PD_TRK; padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + if (padctl->soc->trk_hw_mode) { + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + value &= ~USB2_TRK_HW_MODE; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2); + clk_disable_unprepare(priv->usb2_trk_clk); + } + mutex_unlock(&padctl->lock); } @@ -1560,7 +1595,8 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc); #endif -#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) +#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ + IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) static const char * const tegra194_xusb_padctl_supply_names[] = { "avdd-usb", "vclamp-usb", @@ -1616,8 +1652,31 @@ const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = { .supply_names = tegra194_xusb_padctl_supply_names, .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names), .supports_gen2 = true, + .poll_trk_completed = true, }; EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc); + +const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = { + .num_pads = ARRAY_SIZE(tegra194_pads), + .pads = tegra194_pads, + .ports = { + .usb2 = { + .ops = &tegra186_usb2_port_ops, + .count = 4, + }, + .usb3 = { + .ops = &tegra186_usb3_port_ops, + .count = 4, + }, + }, + .ops = &tegra186_xusb_padctl_ops, + .supply_names = tegra194_xusb_padctl_supply_names, + .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names), + .supports_gen2 = true, + .poll_trk_completed = true, + .trk_hw_mode = true, +}; +EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc); #endif MODULE_AUTHOR("JC Kuo "); diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 95091876c422..23d179b1a5b5 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -71,6 +71,12 @@ static const struct of_device_id tegra_xusb_padctl_of_match[] = { .compatible = "nvidia,tegra194-xusb-padctl", .data = &tegra194_xusb_padctl_soc, }, +#endif +#if defined(CONFIG_ARCH_TEGRA_234_SOC) + { + .compatible = "nvidia,tegra234-xusb-padctl", + .data = &tegra234_xusb_padctl_soc, + }, #endif { } }; diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index 8cfbbdbd6e0c..ec0b5b023ad1 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -8,6 +8,7 @@ #define __PHY_TEGRA_XUSB_H #include +#include #include #include @@ -433,6 +434,8 @@ struct tegra_xusb_padctl_soc { unsigned int num_supplies; bool supports_gen2; bool need_fake_usb3_port; + bool poll_trk_completed; + bool trk_hw_mode; }; struct tegra_xusb_padctl { @@ -475,6 +478,23 @@ static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, return value; } +static inline u32 padctl_readl_poll(struct tegra_xusb_padctl *padctl, + unsigned long offset, u32 val, u32 mask, int us) +{ + u32 regval; + int err; + + err = readl_poll_timeout_atomic(padctl->regs + offset, regval, + (regval & mask) == val, 1, us); + dev_dbg(padctl->dev, "%08lx poll > %08x\n", offset, regval); + if (err) { + dev_err(padctl->dev, "%08lx poll timeout > %08x\n", offset, + regval); + } + + return err; +} + struct tegra_xusb_lane *tegra_xusb_find_lane(struct tegra_xusb_padctl *padctl, const char *name, unsigned int index); @@ -491,5 +511,8 @@ extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc; #if defined(CONFIG_ARCH_TEGRA_194_SOC) extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc; #endif +#if defined(CONFIG_ARCH_TEGRA_234_SOC) +extern const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc; +#endif #endif /* __PHY_TEGRA_XUSB_H */ From patchwork Mon Oct 24 07:41:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 13016786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F4EAFA3740 for ; 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Mon, 24 Oct 2022 00:42:10 -0700 From: Wayne Chang To: , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH 10/11] usb: host: xhci-tegra: Add Tegra234 XHCI support Date: Mon, 24 Oct 2022 15:41:27 +0800 Message-ID: <20221024074128.1113554-11-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024074128.1113554-1-waynec@nvidia.com> References: <20221024074128.1113554-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT015:EE_|CY8PR12MB7660:EE_ X-MS-Office365-Filtering-Correlation-Id: 9dafc26c-4ba8-4add-7b7c-08dab59349fb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ds2WlqMIfMQaeEZa/obxTxNLWfToujyF+i00BNUcOrTh/D+ASqLDkdZOOk87Jc0nNEz87Hn+Y0DUdjJk9asYhpO+XpEOsyVIKb80Y1B9nlkB6X2GZ6sWArM4Mk4HUxCS5c9aUr4qKDyDT/f+FeUscrmkFlrNXj/Vem9DVtUwpH5ATvixv8VH6tbAANsJ+YD78GqVlEp8HDK8Le8Xx+XxksMBe54zvQrOjqJw+TqxoAQdLOFiUfewzZdX33ZI363BfWY+NRhobhozbpbauNeXZWqG1tDo9aXfXkqcx+KFdZuhKBZZRNGdTUnHCtwi69KXuiGj4WXAr8AJO1IgMm/1kpWqiH5wHdXI1/Cv1BGP5mKsKVDdCiML9ixr9ABWJtBvDBJpNgGmAPl0qiWuiKFzOvkOfbsI19Uno9EpsqNp9IDwl1nJYhpxcE4NjEgCgQzdEKl1ti7yNR2EUzX9x7+m41ReM8/WfS/MysN8UsgTT2ZP0XNYshNp/MWRAAr7dRgJG09AAOMdM4IfPLlyKgrNrX+p0vJ3nWKOBxsORyXVjI9RAPSw3GiOCymNfw1GC2p8QGETINl+TpQkVe3RXwgHJyOupcQgzNgaB3/lRI1yVHFftsF/v7BVjPpfTyyN9xDTLhw3ByBzWtex7OoiPhiFag1zviBS9ooC2boUUkNz4JPYeuKt7BYuTdIR+b/Lzr+hhaH7flTGVfNfAs5IDu8IvJObIULrBQzKwfHzgtzZa/scxfkn9UNVkh6br244q/TyD7lYSfr80YFm9BLEd8Y0KtTDAjEtRNc/ucrWW7I5e+o= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(346002)(136003)(39860400002)(396003)(451199015)(36840700001)(46966006)(40470700004)(41300700001)(7416002)(6636002)(921005)(36756003)(30864003)(316002)(54906003)(6666004)(110136005)(70586007)(70206006)(4326008)(8936002)(36860700001)(47076005)(5660300002)(7696005)(7636003)(82740400003)(1076003)(426003)(40480700001)(186003)(2616005)(8676002)(82310400005)(356005)(336012)(86362001)(83380400001)(478600001)(2906002)(26005)(40460700003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:23.0978 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9dafc26c-4ba8-4add-7b7c-08dab59349fb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7660 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sing-Han Chen This change adds Tegra234 XUSB host mode controller support. In Tegra234, some of the registers have moved to bar2 space. The new soc variable has_bar2 indicates the chip with bar2 area. This patch adds new reg helper to let the driver reuse the same code for those chips with bar2 support. The new soc variables has_ifr indicates the chip with IFR FW loading support. IFR registers would be configured in MB1, and FW loading will be triggered in MB2. Signed-off-by: Sing-Han Chen Co-developed-by: Wayne Chang Signed-off-by: Wayne Chang --- drivers/usb/host/xhci-tegra.c | 277 +++++++++++++++++++++++++++++----- 1 file changed, 237 insertions(+), 40 deletions(-) diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c index bdb776553826..86036eeece43 100644 --- a/drivers/usb/host/xhci-tegra.c +++ b/drivers/usb/host/xhci-tegra.c @@ -44,6 +44,9 @@ #define XUSB_CFG_4 0x010 #define XUSB_BASE_ADDR_SHIFT 15 #define XUSB_BASE_ADDR_MASK 0x1ffff +#define XUSB_CFG_7 0x01c +#define XUSB_BASE2_ADDR_SHIFT 16 +#define XUSB_BASE2_ADDR_MASK 0xffff #define XUSB_CFG_16 0x040 #define XUSB_CFG_24 0x060 #define XUSB_CFG_AXI_CFG 0x0f8 @@ -75,6 +78,20 @@ #define MBOX_SMI_INTR_FW_HANG BIT(1) #define MBOX_SMI_INTR_EN BIT(3) +/* BAR2 registers */ +#define XUSB_BAR2_ARU_MBOX_CMD 0x004 +#define XUSB_BAR2_ARU_MBOX_DATA_IN 0x008 +#define XUSB_BAR2_ARU_MBOX_DATA_OUT 0x00c +#define XUSB_BAR2_ARU_MBOX_OWNER 0x010 +#define XUSB_BAR2_ARU_SMI_INTR 0x014 +#define XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0 0x01c +#define XUSB_BAR2_ARU_IFRDMA_CFG0 0x0e0 +#define XUSB_BAR2_ARU_IFRDMA_CFG1 0x0e4 +#define XUSB_BAR2_ARU_IFRDMA_STREAMID_FIELD 0x0e8 +#define XUSB_BAR2_ARU_C11_CSBRANGE 0x9c +#define XUSB_BAR2_ARU_FW_SCRATCH 0x1000 +#define XUSB_BAR2_CSB_BASE_ADDR 0x2000 + /* IPFS registers */ #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4 @@ -111,6 +128,9 @@ #define IMFILLRNG1_TAG_HI_SHIFT 16 #define XUSB_FALC_IMFILLCTL 0x158 +/* CSB ARU registers */ +#define XUSB_CSB_ARU_SCRATCH0 0x100100 + /* MP CSB registers */ #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 @@ -131,6 +151,9 @@ #define IMEM_BLOCK_SIZE 256 +#define FW_IOCTL_TYPE_SHIFT (24) +#define FW_IOCTL_CFGTBL_READ (17) + struct tegra_xusb_fw_header { __le32 boot_loadaddr_in_imem; __le32 boot_codedfi_offset; @@ -175,6 +198,7 @@ struct tegra_xusb_mbox_regs { u16 data_in; u16 data_out; u16 owner; + u16 smi_intr; }; struct tegra_xusb_context_soc { @@ -189,6 +213,7 @@ struct tegra_xusb_context_soc { } fpci; }; +struct tegra_xusb_soc_ops; struct tegra_xusb_soc { const char *firmware; const char * const *supply_names; @@ -205,11 +230,15 @@ struct tegra_xusb_soc { } ports; struct tegra_xusb_mbox_regs mbox; + struct tegra_xusb_soc_ops *ops; bool scale_ss_clock; bool has_ipfs; bool lpm_support; bool otg_reset_sspi; + + bool has_bar2; + bool has_ifr; }; struct tegra_xusb_context { @@ -230,6 +259,8 @@ struct tegra_xusb { void __iomem *ipfs_base; void __iomem *fpci_base; + void __iomem *bar2_base; + resource_size_t bar2_start; const struct tegra_xusb_soc *soc; @@ -276,6 +307,17 @@ struct tegra_xusb { struct tegra_xusb_context context; }; +struct tegra_xusb_soc_ops { + u32 (*mbox_reg_readl)(struct tegra_xusb *tegra, + unsigned int offset); + void (*mbox_reg_writel)(struct tegra_xusb *tegra, + u32 value, unsigned int offset); + u32 (*csb_reg_readl)(struct tegra_xusb *tegra, + unsigned int offset); + void (*csb_reg_writel)(struct tegra_xusb *tegra, + u32 value, unsigned int offset); +}; + static struct hc_driver __read_mostly tegra_xhci_hc_driver; static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) @@ -300,7 +342,33 @@ static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, writel(value, tegra->ipfs_base + offset); } +static inline u32 bar2_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + return readl(tegra->bar2_base + offset); +} + +static inline void bar2_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + writel(value, tegra->bar2_base + offset); +} + static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + struct tegra_xusb_soc_ops *ops = tegra->soc->ops; + + return ops->csb_reg_readl(tegra, offset); +} + +static void csb_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + struct tegra_xusb_soc_ops *ops = tegra->soc->ops; + + ops->csb_reg_writel(tegra, value, offset); +} + +static u32 fpci_csb_readl(struct tegra_xusb *tegra, unsigned int offset) { u32 page = CSB_PAGE_SELECT(offset); u32 ofs = CSB_PAGE_OFFSET(offset); @@ -310,7 +378,7 @@ static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); } -static void csb_writel(struct tegra_xusb *tegra, u32 value, +static void fpci_csb_writel(struct tegra_xusb *tegra, u32 value, unsigned int offset) { u32 page = CSB_PAGE_SELECT(offset); @@ -320,6 +388,26 @@ static void csb_writel(struct tegra_xusb *tegra, u32 value, fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); } +static u32 bar2_csb_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + u32 page = CSB_PAGE_SELECT(offset); + u32 ofs = CSB_PAGE_OFFSET(offset); + + bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); + + return bar2_readl(tegra, XUSB_BAR2_CSB_BASE_ADDR + ofs); +} + +static void bar2_csb_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + u32 page = CSB_PAGE_SELECT(offset); + u32 ofs = CSB_PAGE_OFFSET(offset); + + bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); + bar2_writel(tegra, value, XUSB_BAR2_CSB_BASE_ADDR + ofs); +} + static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, unsigned long rate) { @@ -451,6 +539,7 @@ static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, const struct tegra_xusb_mbox_msg *msg) { + struct tegra_xusb_soc_ops *ops = tegra->soc->ops; bool wait_for_idle = false; u32 value; @@ -459,15 +548,15 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, * ACK/NAK messages. */ if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_NONE) { dev_err(tegra->dev, "mailbox is busy\n"); return -EBUSY; } - fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); + ops->mbox_reg_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_SW) { dev_err(tegra->dev, "failed to acquire mailbox\n"); return -EBUSY; @@ -477,17 +566,17 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, } value = tegra_xusb_mbox_pack(msg); - fpci_writel(tegra, value, tegra->soc->mbox.data_in); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.data_in); - value = fpci_readl(tegra, tegra->soc->mbox.cmd); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); value |= MBOX_INT_EN | MBOX_DEST_FALC; - fpci_writel(tegra, value, tegra->soc->mbox.cmd); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); if (wait_for_idle) { unsigned long timeout = jiffies + msecs_to_jiffies(250); while (time_before(jiffies, timeout)) { - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value == MBOX_OWNER_NONE) break; @@ -495,7 +584,7 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, } if (time_after(jiffies, timeout)) - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_NONE) return -ETIMEDOUT; @@ -507,11 +596,12 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) { struct tegra_xusb *tegra = data; + struct tegra_xusb_soc_ops *ops = tegra->soc->ops; u32 value; /* clear mailbox interrupts */ - value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR); - fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.smi_intr); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.smi_intr); if (value & MBOX_SMI_INTR_FW_HANG) dev_err(tegra->dev, "controller firmware hang\n"); @@ -664,6 +754,7 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) { struct tegra_xusb *tegra = data; + struct tegra_xusb_soc_ops *ops = tegra->soc->ops; struct tegra_xusb_mbox_msg msg; u32 value; @@ -672,16 +763,16 @@ static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) if (pm_runtime_suspended(tegra->dev) || tegra->suspended) goto out; - value = fpci_readl(tegra, tegra->soc->mbox.data_out); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.data_out); tegra_xusb_mbox_unpack(&msg, value); - value = fpci_readl(tegra, tegra->soc->mbox.cmd); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); value &= ~MBOX_DEST_SMI; - fpci_writel(tegra, value, tegra->soc->mbox.cmd); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); /* clear mailbox owner if no ACK/NAK is required */ if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) - fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); + ops->mbox_reg_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); tegra_xusb_mbox_handle(tegra, &msg); @@ -709,6 +800,15 @@ static void tegra_xusb_config(struct tegra_xusb *tegra) value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); fpci_writel(tegra, value, XUSB_CFG_4); + /* Program BAR2 space */ + if (tegra->soc->has_bar2) { + value = fpci_readl(tegra, XUSB_CFG_7); + value &= ~(XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); + value |= tegra->bar2_start & + (XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); + fpci_writel(tegra, value, XUSB_CFG_7); + } + usleep_range(100, 200); /* Enable bus master */ @@ -881,21 +981,36 @@ static int tegra_xusb_request_firmware(struct tegra_xusb *tegra) return 0; } +static int tegra_xusb_wait_for_falcon(struct tegra_xusb *tegra) +{ + struct xhci_cap_regs __iomem *cap_regs; + struct xhci_op_regs __iomem *op_regs; + int ret; + u32 val; + + cap_regs = tegra->regs; + op_regs = tegra->regs + HC_LENGTH(readl(&cap_regs->hc_capbase)); + + ret = readl_poll_timeout(&op_regs->status, val, !(val & STS_CNR), 1000, 200000); + + if (ret) + dev_err(tegra->dev, "XHCI Controller not ready. Falcon state: 0x%x\n", + csb_readl(tegra, XUSB_FALC_CPUCTL)); + + return ret; +} + static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) { unsigned int code_tag_blocks, code_size_blocks, code_blocks; - struct xhci_cap_regs __iomem *cap = tegra->regs; struct tegra_xusb_fw_header *header; struct device *dev = tegra->dev; - struct xhci_op_regs __iomem *op; - unsigned long timeout; time64_t timestamp; u64 address; u32 value; int err; header = (struct tegra_xusb_fw_header *)tegra->fw.virt; - op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase)); if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { dev_info(dev, "Firmware already loaded, Falcon state %#x\n", @@ -968,26 +1083,43 @@ static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */ csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); - timeout = jiffies + msecs_to_jiffies(200); + if (tegra_xusb_wait_for_falcon(tegra)) + return -EIO; - do { - value = readl(&op->status); - if ((value & STS_CNR) == 0) - break; + timestamp = le32_to_cpu(header->fwimg_created_time); - usleep_range(1000, 2000); - } while (time_is_after_jiffies(timeout)); + dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); + + return 0; +} - value = readl(&op->status); - if (value & STS_CNR) { - value = csb_readl(tegra, XUSB_FALC_CPUCTL); - dev_err(dev, "XHCI controller not read: %#010x\n", value); +static u32 tegra_xusb_read_firmware_header(struct tegra_xusb *tegra, u32 offset) +{ + /* + * We only accept reading the firmware config table + * The offset should not exceed the fw header structure + */ + if (offset >= sizeof(struct tegra_xusb_fw_header)) + return 0; + + bar2_writel(tegra, (FW_IOCTL_CFGTBL_READ << FW_IOCTL_TYPE_SHIFT) | offset, + XUSB_BAR2_ARU_FW_SCRATCH); + return bar2_readl(tegra, XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0); +} + +static int tegra_xusb_init_ifr_firmware(struct tegra_xusb *tegra) +{ + time64_t timestamp; + + if (tegra_xusb_wait_for_falcon(tegra)) return -EIO; - } - timestamp = le32_to_cpu(header->fwimg_created_time); +#define offsetof_32(X, Y) ((u8)(offsetof(X, Y) / sizeof(__le32))) + timestamp = tegra_xusb_read_firmware_header(tegra, + offsetof_32(struct tegra_xusb_fw_header, + fwimg_created_time) << 2); - dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); + dev_info(tegra->dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); return 0; } @@ -1403,7 +1535,7 @@ static int tegra_xusb_probe(struct platform_device *pdev) struct of_phandle_args args; struct tegra_xusb *tegra; struct device_node *np; - struct resource *regs; + struct resource *res, *regs; struct xhci_hcd *xhci; unsigned int i, j, k; struct phy *phy; @@ -1435,6 +1567,11 @@ static int tegra_xusb_probe(struct platform_device *pdev) tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2); if (IS_ERR(tegra->ipfs_base)) return PTR_ERR(tegra->ipfs_base); + } else if (tegra->soc->has_bar2) { + tegra->bar2_base = devm_platform_get_and_ioremap_resource(pdev, 2, &res); + if (IS_ERR(tegra->bar2_base)) + return PTR_ERR(tegra->bar2_base); + tegra->bar2_start = res->start; } tegra->xhci_irq = platform_get_irq(pdev, 0); @@ -1651,10 +1788,13 @@ static int tegra_xusb_probe(struct platform_device *pdev) goto disable_phy; } - err = tegra_xusb_request_firmware(tegra); - if (err < 0) { - dev_err(&pdev->dev, "failed to request firmware: %d\n", err); - goto disable_phy; + if (!tegra->soc->has_ifr) { + err = tegra_xusb_request_firmware(tegra); + if (err < 0) { + dev_err(&pdev->dev, + "failed to request firmware: %d\n", err); + goto disable_phy; + } } err = tegra_xusb_unpowergate_partitions(tegra); @@ -1663,7 +1803,10 @@ static int tegra_xusb_probe(struct platform_device *pdev) tegra_xusb_config(tegra); - err = tegra_xusb_load_firmware(tegra); + if (tegra->soc->has_ifr) + err = tegra_xusb_init_ifr_firmware(tegra); + else + err = tegra_xusb_load_firmware(tegra); if (err < 0) { dev_err(&pdev->dev, "failed to load firmware: %d\n", err); goto powergate; @@ -2070,7 +2213,10 @@ static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool runtime) tegra_xusb_config(tegra); tegra_xusb_restore_context(tegra); - err = tegra_xusb_load_firmware(tegra); + if (tegra->soc->has_ifr) + err = tegra_xusb_init_ifr_firmware(tegra); + else + err = tegra_xusb_load_firmware(tegra); if (err < 0) { dev_err(tegra->dev, "failed to load firmware: %d\n", err); goto disable_phy; @@ -2271,6 +2417,13 @@ static const struct tegra_xusb_context_soc tegra124_xusb_context = { }, }; +static struct tegra_xusb_soc_ops tegra124_ops = { + .mbox_reg_readl = &fpci_readl, + .mbox_reg_writel = &fpci_writel, + .csb_reg_readl = &fpci_csb_readl, + .csb_reg_writel = &fpci_csb_writel, +}; + static const struct tegra_xusb_soc tegra124_soc = { .firmware = "nvidia/tegra124/xusb.bin", .supply_names = tegra124_supply_names, @@ -2286,11 +2439,13 @@ static const struct tegra_xusb_soc tegra124_soc = { .scale_ss_clock = true, .has_ipfs = true, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, }; MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); @@ -2322,11 +2477,13 @@ static const struct tegra_xusb_soc tegra210_soc = { .scale_ss_clock = false, .has_ipfs = true, .otg_reset_sspi = true, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, }; MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); @@ -2363,11 +2520,13 @@ static const struct tegra_xusb_soc tegra186_soc = { .scale_ss_clock = false, .has_ipfs = false, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, .lpm_support = true, }; @@ -2394,21 +2553,59 @@ static const struct tegra_xusb_soc tegra194_soc = { .scale_ss_clock = false, .has_ipfs = false, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0x68, .data_in = 0x6c, .data_out = 0x70, .owner = 0x74, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, .lpm_support = true, }; MODULE_FIRMWARE("nvidia/tegra194/xusb.bin"); +static struct tegra_xusb_soc_ops tegra234_ops = { + .mbox_reg_readl = &bar2_readl, + .mbox_reg_writel = &bar2_writel, + .csb_reg_readl = &bar2_csb_readl, + .csb_reg_writel = &bar2_csb_writel, +}; + +static const struct tegra_xusb_soc tegra234_soc = { + .firmware = "nvidia/tegra234/xusb.bin", + .supply_names = tegra194_supply_names, + .num_supplies = ARRAY_SIZE(tegra194_supply_names), + .phy_types = tegra194_phy_types, + .num_types = ARRAY_SIZE(tegra194_phy_types), + .context = &tegra186_xusb_context, + .ports = { + .usb3 = { .offset = 0, .count = 4, }, + .usb2 = { .offset = 4, .count = 4, }, + }, + .scale_ss_clock = false, + .has_ipfs = false, + .otg_reset_sspi = false, + .ops = &tegra234_ops, + .mbox = { + .cmd = XUSB_BAR2_ARU_MBOX_CMD, + .data_in = XUSB_BAR2_ARU_MBOX_DATA_IN, + .data_out = XUSB_BAR2_ARU_MBOX_DATA_OUT, + .owner = XUSB_BAR2_ARU_MBOX_OWNER, + .smi_intr = XUSB_BAR2_ARU_SMI_INTR, + }, + .lpm_support = true, + .has_bar2 = true, + .has_ifr = true, +}; +MODULE_FIRMWARE("nvidia/tegra234/xusb.bin"); + static const struct of_device_id tegra_xusb_of_match[] = { { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc }, { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc }, + { .compatible = "nvidia,tegra234-xusb", .data = &tegra234_soc }, { }, }; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2022 07:42:24.0354 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 233c5e8a-88cf-4bd0-8d27-08dab5934a8a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT087.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5241 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sing-Han Chen This commit adds support for XUSB device mode controller support on Tegra234 SoC. This is very similar to the existing Tegra194 XUDC. Signed-off-by: Sing-Han Chen Signed-off-by: Wayne Chang --- drivers/usb/gadget/udc/tegra-xudc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index 76919d7570d2..ff697190469b 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -3660,6 +3660,19 @@ static struct tegra_xudc_soc tegra194_xudc_soc_data = { .has_ipfs = false, }; +static struct tegra_xudc_soc tegra234_xudc_soc_data = { + .clock_names = tegra186_xudc_clock_names, + .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), + .num_phys = 4, + .u1_enable = true, + .u2_enable = true, + .lpm_enable = true, + .invalid_seq_num = false, + .pls_quirk = false, + .port_reset_quirk = false, + .has_ipfs = false, +}; + static const struct of_device_id tegra_xudc_of_match[] = { { .compatible = "nvidia,tegra210-xudc", @@ -3673,6 +3686,10 @@ static const struct of_device_id tegra_xudc_of_match[] = { .compatible = "nvidia,tegra194-xudc", .data = &tegra194_xudc_soc_data }, + { + .compatible = "nvidia,tegra234-xudc", + .data = &tegra234_xudc_soc_data + }, { } }; MODULE_DEVICE_TABLE(of, tegra_xudc_of_match);