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Wed, 26 Oct 2022 15:39:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 26 Oct 2022 15:39:50 +0800 From: Eddie Huang To: Asutosh Das , , , , CC: , , , , , Eddie Huang Subject: [PATCH v1 1/2] ufs: core: mcq: Add config_mcq_resource vops Date: Wed, 26 Oct 2022 15:39:42 +0800 Message-ID: <20221026073943.22111-2-eddie.huang@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20221026073943.22111-1-eddie.huang@mediatek.com> References: <20221026073943.22111-1-eddie.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221026_004033_733711_CEB88DDD X-CRM114-Status: GOOD ( 13.10 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org SoCs vendor config MCQ register address resource in config_mcq_resource vops Signed-off-by: Eddie Huang --- drivers/ufs/core/ufs-mcq.c | 3 +++ drivers/ufs/core/ufshcd-priv.h | 8 ++++++++ include/ufs/ufshcd.h | 1 + 3 files changed, 12 insertions(+) diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index b51ba35..1fdb45a 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -173,6 +173,9 @@ static int ufshcd_mcq_config_resource(struct ufs_hba *hba) struct resource *res_mem, *res_mcq; int i, ret = 0; + if (ufshcd_mcq_vops_config_resource(hba) == 0) + return 0; + memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); for (i = 0; i < RES_MAX; i++) { diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index 6e9bec6..2f71b0e 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -257,6 +257,14 @@ static inline int ufshcd_vops_get_outstanding_cqs(struct ufs_hba *hba, return -EOPNOTSUPP; } +static inline int ufshcd_mcq_vops_config_resource(struct ufs_hba *hba) +{ + if (hba->vops && hba->vops->config_mcq_resource) + return hba->vops->config_mcq_resource(hba); + + return -EOPNOTSUPP; +} + extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; /** diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 506fc6e..be323c9 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -339,6 +339,7 @@ struct ufs_hba_variant_ops { int (*op_runtime_config)(struct ufs_hba *hba); int (*get_outstanding_cqs)(struct ufs_hba *hba, unsigned long *ocqs); + int (*config_mcq_resource)(struct ufs_hba *hba); }; /* clock gating state */ From patchwork Wed Oct 26 07:39:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?RWRkaWUgSHVhbmcgKOm7g+aZuuWCkSk=?= X-Patchwork-Id: 13020307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30EEBC38A2D for ; Wed, 26 Oct 2022 08:10:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:CC:To:From:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Wed, 26 Oct 2022 15:39:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 26 Oct 2022 15:39:50 +0800 From: Eddie Huang To: Asutosh Das , , , , CC: , , , , , Eddie Huang Subject: [PATCH v1 2/2] ufs: mtk-host: Add MCQ feature Date: Wed, 26 Oct 2022 15:39:43 +0800 Message-ID: <20221026073943.22111-3-eddie.huang@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20221026073943.22111-1-eddie.huang@mediatek.com> References: <20221026073943.22111-1-eddie.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221026_011039_016592_8EEE06A9 X-CRM114-Status: GOOD ( 13.05 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add Mediatek mcq resource and runtime configuration function to support MCQ capability Signed-off-by: Eddie Huang --- drivers/ufs/host/ufs-mediatek.c | 37 +++++++++++++++++++++++++++++++++++++ drivers/ufs/host/ufs-mediatek.h | 7 +++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index c958279..3f5fc05 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -31,6 +31,8 @@ #define CREATE_TRACE_POINTS #include "ufs-mediatek-trace.h" +#define MCQ_QUEUE_OFFSET(c) ((((c) >> 16) & 0xFF) * 0x200) + static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = { { .wmanufacturerid = UFS_ANY_VENDOR, .model = UFS_ANY_MODEL, @@ -833,6 +835,8 @@ static int ufs_mtk_init(struct ufs_hba *hba) host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER); + hba->caps |= UFSHCD_CAP_MCQ_EN; + goto out; out_variant_clear: @@ -1314,6 +1318,37 @@ static void ufs_mtk_event_notify(struct ufs_hba *hba, trace_ufs_mtk_event(evt, val); } +static int ufs_mtk_op_runtime_config(struct ufs_hba *hba) +{ + struct ufshcd_mcq_opr_info_t *opr; + int i; + + for (i = 0; i < OPR_MAX; i++) { + opr = &hba->mcq_opr[i]; + opr->stride = REG_UFS_MCQ_STRIDE; + } + + hba->mcq_opr[OPR_SQD].offset = REG_UFS_MTK_SQD; + hba->mcq_opr[OPR_SQIS].offset = REG_UFS_MTK_SQIS; + hba->mcq_opr[OPR_CQD].offset = REG_UFS_MTK_CQD; + hba->mcq_opr[OPR_CQIS].offset = REG_UFS_MTK_CQIS; + + hba->mcq_opr[OPR_SQD].base = hba->mmio_base + REG_UFS_MTK_SQD; + hba->mcq_opr[OPR_SQIS].base = hba->mmio_base + REG_UFS_MTK_SQIS; + hba->mcq_opr[OPR_CQD].base = hba->mmio_base + REG_UFS_MTK_CQD; + hba->mcq_opr[OPR_CQIS].base = hba->mmio_base + REG_UFS_MTK_CQIS; + + return 0; +} + +static int ufs_mtk_config_mcq_resource(struct ufs_hba *hba) +{ + hba->mcq_base = hba->mmio_base + + MCQ_QUEUE_OFFSET(hba->mcq_capabilities); + + return 0; +} + /* * struct ufs_hba_mtk_vops - UFS MTK specific variant operations * @@ -1335,6 +1370,8 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = { .dbg_register_dump = ufs_mtk_dbg_register_dump, .device_reset = ufs_mtk_device_reset, .event_notify = ufs_mtk_event_notify, + .op_runtime_config = ufs_mtk_op_runtime_config, + .config_mcq_resource = ufs_mtk_config_mcq_resource, }; /** diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h index aa26d41..febf702 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -26,6 +26,13 @@ #define REG_UFS_DEBUG_SEL_B2 0x22D8 #define REG_UFS_DEBUG_SEL_B3 0x22DC +#define REG_UFS_MTK_SQD 0x2800 +#define REG_UFS_MTK_SQIS 0x2814 +#define REG_UFS_MTK_CQD 0x281C +#define REG_UFS_MTK_CQIS 0x2824 + +#define REG_UFS_MCQ_STRIDE 0x30 + /* * Ref-clk control *