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Dropped deprecated compatibles and properties described in txt file. Signed-off-by: Vadym Kochan --- v5: 1) Get back "label" and "partitions" properties but without ref to the "partition.yaml" which was wrongly used. 2) Add "additionalProperties: false" for nand@ because all possible properties are described. v4: 1) Remove "label" and "partitions" properties 2) Use 2 clocks for A7K/8K platform which is a requirement v3: 1) Remove txt version from the MAINTAINERS list 2) Use enum for some of compatible strings 3) Drop: #address-cells #size-cells: as they are inherited from the nand-controller.yaml 4) Add restriction to use 2 clocks for A8K SoC 5) Dropped description for clock-names and extend it with minItems: 1 6) Drop description for "dmas" 7) Use "unevalautedProperties: false" 8) Drop quites from yaml refs. 9) Use 4-space indentation for the example section v2: 1) Fixed warning by yamllint with incorrect indentation for compatible list .../bindings/mtd/marvell,nand-controller.yaml | 195 ++++++++++++++++++ .../devicetree/bindings/mtd/marvell-nand.txt | 126 ----------- MAINTAINERS | 1 - 3 files changed, 195 insertions(+), 127 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml delete mode 100644 Documentation/devicetree/bindings/mtd/marvell-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml new file mode 100644 index 000000000000..544e98ed12bb --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml @@ -0,0 +1,195 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell NAND Flash Controller (NFC) + +maintainers: + - Miquel Raynal + +properties: + compatible: + oneOf: + - items: + - const: marvell,armada-8k-nand-controller + - const: marvell,armada370-nand-controller + - enum: + - marvell,armada370-nand-controller + - marvell,pxa3xx-nand-controller + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + description: + Shall reference the NAND controller clocks, the second one is + is only needed for the Armada 7K/8K SoCs + + clock-names: + items: + - const: core + - const: reg + + dmas: + maxItems: 1 + + dma-names: + items: + - const: rxtx + + marvell,system-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: Syscon node that handles NAND controller related registers + +patternProperties: + "^nand@[0-3]$": + type: object + properties: + reg: + minimum: 0 + maximum: 3 + + nand-rb: + minimum: 0 + maximum: 1 + + nand-ecc-strength: + enum: [1, 4, 8] + + nand-on-flash-bbt: true + + nand-ecc-mode: true + + nand-ecc-algo: + description: | + This property is essentially useful when not using hardware ECC. + Howerver, it may be added when using hardware ECC for clarification + but will be ignored by the driver because ECC mode is chosen depending + on the page size and the strength required by the NAND chip. + This value may be overwritten with nand-ecc-strength property. + + nand-ecc-step-size: + description: | + Marvell's NAND flash controller does use fixed strength + (1-bit for Hamming, 16-bit for BCH), so the actual step size + will shrink or grow in order to fit the required strength. + Step sizes are not completely random for all and follow certain + patterns described in AN-379, "Marvell SoC NFC ECC". + + label: + $ref: /schemas/types.yaml#/definitions/string + + partitions: + type: object + + marvell,nand-keep-config: + description: | + Orders the driver not to take the timings from the core and + leaving them completely untouched. Bootloader timings will then + be used. + $ref: /schemas/types.yaml#/definitions/flag + + marvell,nand-enable-arbiter: + description: | + To enable the arbiter, all boards blindly used it, + this bit was set by the bootloader for many boards and even if + it is marked reserved in several datasheets, it might be needed to set + it (otherwise it is harmless) so whether or not this property is set, + the bit is selected by the driver. + $ref: /schemas/types.yaml#/definitions/flag + deprecated: true + + additionalProperties: false + + required: + - reg + - nand-rb + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + +allOf: + - $ref: nand-controller.yaml# + + - if: + properties: + compatible: + contains: + const: marvell,pxa3xx-nand-controller + then: + required: + - dmas + - dma-names + else: + properties: + dmas: false + dma-names: false + + - if: + properties: + compatible: + contains: + const: marvell,armada-8k-nand-controller + then: + required: + - marvell,system-controller + properties: + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + minItems: 2 + else: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + marvell,system-controller: false + +examples: + - | + #include + nand_controller: nand-controller@d0000 { + compatible = "marvell,armada370-nand-controller"; + reg = <0xd0000 0x54>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&coredivclk 0>; + + nand@0 { + reg = <0>; + label = "main-storage"; + nand-rb = <0>; + nand-ecc-mode = "hw"; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Rootfs"; + reg = <0x00000000 0x40000000>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/marvell-nand.txt b/Documentation/devicetree/bindings/mtd/marvell-nand.txt deleted file mode 100644 index a2d9a0f2b683..000000000000 --- a/Documentation/devicetree/bindings/mtd/marvell-nand.txt +++ /dev/null @@ -1,126 +0,0 @@ -Marvell NAND Flash Controller (NFC) - -Required properties: -- compatible: can be one of the following: - * "marvell,armada-8k-nand-controller" - * "marvell,armada370-nand-controller" - * "marvell,pxa3xx-nand-controller" - * "marvell,armada-8k-nand" (deprecated) - * "marvell,armada370-nand" (deprecated) - * "marvell,pxa3xx-nand" (deprecated) - Compatibles marked deprecated support only the old bindings described - at the bottom. -- reg: NAND flash controller memory area. -- #address-cells: shall be set to 1. Encode the NAND CS. -- #size-cells: shall be set to 0. -- interrupts: shall define the NAND controller interrupt. -- clocks: shall reference the NAND controller clocks, the second one is - is only needed for the Armada 7K/8K SoCs -- clock-names: mandatory if there is a second clock, in this case there - should be one clock named "core" and another one named "reg" -- marvell,system-controller: Set to retrieve the syscon node that handles - NAND controller related registers (only required with the - "marvell,armada-8k-nand[-controller]" compatibles). - -Optional properties: -- label: see partition.txt. New platforms shall omit this property. -- dmas: shall reference DMA channel associated to the NAND controller. - This property is only used with "marvell,pxa3xx-nand[-controller]" - compatible strings. -- dma-names: shall be "rxtx". - This property is only used with "marvell,pxa3xx-nand[-controller]" - compatible strings. - -Optional children nodes: -Children nodes represent the available NAND chips. - -Required properties: -- reg: shall contain the native Chip Select ids (0-3). -- nand-rb: see nand-controller.yaml (0-1). - -Optional properties: -- marvell,nand-keep-config: orders the driver not to take the timings - from the core and leaving them completely untouched. Bootloader - timings will then be used. -- label: MTD name. -- nand-on-flash-bbt: see nand-controller.yaml. -- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified. -- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when - not using hardware ECC. Howerver, it may be added when using hardware - ECC for clarification but will be ignored by the driver because ECC - mode is chosen depending on the page size and the strength required by - the NAND chip. This value may be overwritten with nand-ecc-strength - property. -- nand-ecc-strength: see nand-controller.yaml. -- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does - use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual - step size will shrink or grow in order to fit the required strength. - Step sizes are not completely random for all and follow certain - patterns described in AN-379, "Marvell SoC NFC ECC". - -See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on -generic bindings. - - -Example: -nand_controller: nand-controller@d0000 { - compatible = "marvell,armada370-nand-controller"; - reg = <0xd0000 0x54>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&coredivclk 0>; - - nand@0 { - reg = <0>; - label = "main-storage"; - nand-rb = <0>; - nand-ecc-mode = "hw"; - marvell,nand-keep-config; - nand-on-flash-bbt; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "Rootfs"; - reg = <0x00000000 0x40000000>; - }; - }; - }; -}; - - -Note on legacy bindings: One can find, in not-updated device trees, -bindings slightly different than described above with other properties -described below as well as the partitions node at the root of a so -called "nand" node (without clear controller/chip separation). - -Legacy properties: -- marvell,nand-enable-arbiter: To enable the arbiter, all boards blindly - used it, this bit was set by the bootloader for many boards and even if - it is marked reserved in several datasheets, it might be needed to set - it (otherwise it is harmless) so whether or not this property is set, - the bit is selected by the driver. -- num-cs: Number of chip-select lines to use, all boards blindly set 1 - to this and for a reason, other values would have failed. The value of - this property is ignored. - -Example: - - nand0: nand@43100000 { - compatible = "marvell,pxa3xx-nand"; - reg = <0x43100000 90>; - interrupts = <45>; - dmas = <&pdma 97 0>; - dma-names = "rxtx"; - #address-cells = <1>; - marvell,nand-keep-config; - marvell,nand-enable-arbiter; - num-cs = <1>; - /* Partitions (optional) */ - }; diff --git a/MAINTAINERS b/MAINTAINERS index d7d76760ef93..9b165112be3e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12344,7 +12344,6 @@ MARVELL NAND CONTROLLER DRIVER M: Miquel Raynal L: linux-mtd@lists.infradead.org S: Maintained -F: Documentation/devicetree/bindings/mtd/marvell-nand.txt F: drivers/mtd/nand/raw/marvell_nand.c MARVELL OCTEONTX2 PHYSICAL FUNCTION DRIVER From patchwork Wed Oct 26 13:45:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vadym Kochan X-Patchwork-Id: 13020655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40637C38A2D for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gtO1ETzXcHhcxqzzlNP31pjJ6RMOsMEeFYRMWUWPxqXa1S6AvkowvMzGv+JQ2eFL36qBrmzs9V5hpG5rAliK/Olkl5nvGTNLK8QGA5Dr5vtHof16fpGkWtW2QMbYJRT2kAs/X262EMFbqC1s2CDVQBepdh9oCdniWZe6SY1SLcXJm+WU4RH/3egtmmYJy8JzGSXGWGTmfce4F+29i9jwBs67GLdvtsu/MBabCA8vGx3LL+gQTCYPk5agVpu2b3QtUdp4iHlEjK5NMk5z8Gysr135EPOzpV5eFiy1n0avlJc/QuJp6SuNf8CXlL0ETXT2aBAAK9W7VfbA3sLOU6k6V2E3Hkg0u9D4QJu4P1oe5dlKi7UPyXU+3sddW9tex01vbGSjFITesvkHzFbCRFpKE86XmX+xhqrUsWkmje/dmBStV9SozhyrYihGlYSa2IJPD+AqkIv7xq8USVTnWJggo+z14UhzmaB+Z7T3xlb1Ik+Uy/Brr8DJ1RMyS76u4vo5Dz5K/ai+hl0gBpzqDQIMZ/snAFCSCKXCnzVOGEUvgoI/BfHmvusH4YZJZyRcLxEZRUo/fbFZP/nLPa+mIGkb3wVL6i07lBIXd+W5aQYbo6fO12kg9gXgTZrfKep+Ag3AVXi8DN5WFJpAPiqBdxd6PP2+zRmlxwXOyqX8h6dOSEaC4uHKRRmuYzn+5SNvYYGWj3s+uMFitL39yVq3uVAkv5qPvOdQrcbwdY/zNX2nHMuyOE1/sU//KRjWNfvOahopOqPyCi4Y0lyYY6FFXb0h7oraWOXJQP1Sm/rk+z0zWxzsInHrhBwUgg9rBPrMF2hSnuwhWm1k9VxynXJbLc0o2WxB44it1GeBvSKnTO+dGrL5AYCKYjOrXRUG7vody4vCX3pkhRgn3A5ZQWllaJo0Ur+sLwVkJL14dre58ZxTTbfSDASkFKJkLm1aGrPsUdO4VLoRo7xIhu/qW8Y702Ah34BAFoaloadG0W4odgyZHFe9p6OAUpG0f671vEnQsmWLyZpvGgBpDSeLHPt+6+GtlodkqxKDm9N4rfAWXAATAr24T31HAcX4HFIGO/i7yMFyQc33WDFu85QVuNp2cAN/XolIV47PziQUmmLXeHKlFoCKW+47hQlmM9sq2ZT34gR787iAo99pbekdR4QcCO1aGAo14T2ooGzk91DDb0kruy7XXzxCTgIjv1JGnlPDql/BvGB8G8Y66sRWcfMWmT9Q+OgR7T1nwzXF2AUbewOGSQ2bGg46G8n2XJw3FIpRPVawMzcBQdeVm3EgsawGWgOTCHBeOqLHKotRF/czgVT4VHdq0JjK5gnCW9XDpkcidDlC9McMcuLZCkJfP6oP6L7k+EfBpSKCQkA7sbwWzSJNrb+jKHV9GWreEyd72L4PyqGoW81L6DbS/zM9htzW+YPG+zWGEfpRdD0k1I6o+0El6mCrjj2BKgn8uaWe+PGFz8H7V188jDGJ+qW+pxxZresfmltKwT/GBq1nuRYnt5IqFN4xuxHysgnZeM4e9afLkbPheJMtvB2etccRs9IH74PA1+0MNREkDB1immA0iuIybsFqcUIRb7S7V5aVh54lnOvsjYwhVbGJGGnT5dfeHZ+BFA== X-OriginatorOrg: plvision.eu X-MS-Exchange-CrossTenant-Network-Message-Id: b50f3ce8-3b30-432e-a531-08dab7586eb9 X-MS-Exchange-CrossTenant-AuthSource: VI1P190MB0317.EURP190.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Oct 2022 13:46:07.0578 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 03707b74-30f3-46b6-a0e0-ff0a7438c9c4 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: H936NggjYPpqVs4DffXRlS+AxfOIab2cF/hiHnZEX9IkJvpLbnls7tK5k0WOo4UcMYwhFAQaEHkjOKwn3yRksW9tTMkkzLUgNwb6tAQYarQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1P190MB0941 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221026_064613_514919_A05F34C7 X-CRM114-Status: GOOD ( 11.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Marvell NAND controller has now YAML to validate it's DT bindings, so change the node name of cp11x DTSI as it is required by nand-controller.yaml Signed-off-by: Vadym Kochan --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 7d0043824f2a..982b180b33e6 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -468,7 +468,7 @@ status = "disabled"; }; - CP11X_LABEL(nand_controller): nand@720000 { + CP11X_LABEL(nand_controller): nand-controller@720000 { /* * Due to the limitation of the pins available * this controller is only usable on the CPM