From patchwork Wed Oct 26 20:15:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9F96C38A2D for ; Wed, 26 Oct 2022 20:19:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmoc-0001A5-83; Wed, 26 Oct 2022 16:15:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmoY-0000jL-QJ for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:15:50 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmoV-00031A-O8 for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:15:50 -0400 Received: by mail-pl1-x632.google.com with SMTP id f23so15289555plr.6 for ; Wed, 26 Oct 2022 13:15:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Amj+vSFcdbQnaoWcuLvjNhpGRqy42M12Pln3+46OKr0=; b=ZE1JZrUWlSVyyv7z5B66/69C7T/6qgHzQxMzN3rCwAMCID/PiiMPG08cJUHASiL8V5 s7scyDfoHnxs/2n/077RFwr3rNZebF7t9pud1glKU/N4Ft+PUIytg2K8ZO4Xif727uZs O7BiGFRWjoS3WbC1CAvFxtea1i+MnqJIrax8I9h0JyKHYx3z3/LXmha9vqXPcPOLZsYb wKAx+Zke7qCiNFm8nPtMqhyVci6SK4xzk57yl9XStl52mQo8urOsCGwdn7i3q3iphkpS XeDenQjaz10Nr9+tkflkgswSu0VyQsptcNjnsDLj6D2Q2wt+5fMa+AAN6pvWbtsJBu3d oxRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Amj+vSFcdbQnaoWcuLvjNhpGRqy42M12Pln3+46OKr0=; b=Xe6c1pygiwPjlC5agAFzCfhzw4/ojS5Di4P13wv/dxbD7pa6TuMNHjYIenTLGEQVPi u0m9YCdE+IFkrb0ufiQ6U6Wz1uglwqdxmjw2Qk3bgEMHAe/+72v6UXs8ZhYJfLg9ti7k 45oU4KDD0PGHH1FhkqBS/FeQEKcFd0TwPJZgKK9VLCoCLF8gK+W7IZvoe+vBMyanf5k6 jwPscCCSE3bpX/6afVn6V42U2yXVQcwBNcgVGeVmwwNCS4/5Pv02BbUkPdXFH2ewYFb4 Uea8236CAbGq9076XlCt08+/wsQHKX7aF3w/vrd4xvlNcSLBD/o0/0/Hvzkc5PTB6Kn5 GQUA== X-Gm-Message-State: ACrzQf28CmZEnzQhMGg6TeTWO/e7Z5KP13u0E37l9/7Og53IZeH9dXnC DUV6hJFwGmByjq8011Be9IOIuQ== X-Google-Smtp-Source: AMsMyM45wESGhYVkVWWm/iyZx0t8abNp3MQe38oZo7uCaj0S3RmgYgUZYawI/hw+/jEBcazX1DJPxw== X-Received: by 2002:a17:902:ab89:b0:186:7cfc:cde8 with SMTP id f9-20020a170902ab8900b001867cfccde8mr29415167plr.9.1666815345324; Wed, 26 Oct 2022 13:15:45 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.15.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:15:44 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 01/16] pci: Allow to omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:12 +0900 Message-Id: <20221026201527.24063-2-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::632; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org pci_add_capability appears most PCI devices. Its error handling required lots of code, and led to inconsistent behaviors such as: - passing error_abort - passing error_fatal - asserting the returned value - propagating the error to the caller - skipping the rest of the function - just ignoring The code generating errors in pci_add_capability had a comment which says: > Verify that capabilities don't overlap. Note: device assignment > depends on this check to verify that the device is not broken. > Should never trigger for emulated devices, but it's helpful for > debugging these. Indeed vfio has some code that passes capability offsets and sizes from a physical device, but it explicitly pays attention so that the capabilities never overlap. Therefore, we can always assert that capabilities never overlap when pci_add_capability is called, resolving these inconsistencies. Such an implementation of pci_add_capability will not have errp parameter. However, there are so many callers of pci_add_capability that it does not make sense to amend all of them at once to match with the new signature. Instead, this change will allow callers of pci_add_capability to omit errp as the first step. Signed-off-by: Akihiko Odaki --- hw/pci/pci.c | 8 ++++---- include/hw/pci/pci.h | 13 ++++++++++--- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 2f450f6a72..8ee2171011 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2513,14 +2513,14 @@ static void pci_del_option_rom(PCIDevice *pdev) } /* - * On success, pci_add_capability() returns a positive value + * On success, pci_add_capability_legacy() returns a positive value * that the offset of the pci capability. * On failure, it sets an error and returns a negative error * code. */ -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp) +int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, + Error **errp) { uint8_t *config; int i, overlapping_cap; diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index b54b6ef88f..51fd106f16 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -2,6 +2,7 @@ #define QEMU_PCI_H #include "exec/memory.h" +#include "qapi/error.h" #include "sysemu/dma.h" /* PCI includes legacy ISA access. */ @@ -390,9 +391,15 @@ void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, void pci_unregister_vga(PCIDevice *pci_dev); pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp); +int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, + Error **errp); + +#define PCI_ADD_CAPABILITY_VA(pdev, cap_id, offset, size, errp, ...) \ + pci_add_capability_legacy(pdev, cap_id, offset, size, errp) + +#define pci_add_capability(...) \ + PCI_ADD_CAPABILITY_VA(__VA_ARGS__, &error_abort) void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); From patchwork Wed Oct 26 20:15:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02F26C38A2D for ; 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Wed, 26 Oct 2022 13:15:50 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:15:49 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 02/16] hw/i386/amd_iommu: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:13 +0900 Message-Id: <20221026201527.24063-3-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::52f; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate heare because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/i386/amd_iommu.c | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 725f69095b..8a88cbea0a 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1539,7 +1539,6 @@ static void amdvi_sysbus_reset(DeviceState *dev) static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) { - int ret = 0; AMDVIState *s = AMD_IOMMU_DEVICE(dev); MachineState *ms = MACHINE(qdev_get_machine()); PCMachineState *pcms = PC_MACHINE(ms); @@ -1553,23 +1552,11 @@ static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) if (!qdev_realize(DEVICE(&s->pci), &bus->qbus, errp)) { return; } - ret = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, - AMDVI_CAPAB_SIZE, errp); - if (ret < 0) { - return; - } - s->capab_offset = ret; + s->capab_offset = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, + AMDVI_CAPAB_SIZE); - ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, - AMDVI_CAPAB_REG_SIZE, errp); - if (ret < 0) { - return; - } - ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, - AMDVI_CAPAB_REG_SIZE, errp); - if (ret < 0) { - return; - } + pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE); + pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_REG_SIZE); /* Pseudo address space under root PCI bus. */ x86ms->ioapic_as = amdvi_host_dma_iommu(bus, s, AMDVI_IOAPIC_SB_DEVID); From patchwork Wed Oct 26 20:15:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2295C38A2D for ; Wed, 26 Oct 2022 20:23:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmpw-00029k-3w; Wed, 26 Oct 2022 16:17:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmok-0001Ru-Ok for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:09 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmoe-00035F-VJ for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:15:58 -0400 Received: by mail-pg1-x536.google.com with SMTP id e129so16026914pgc.9 for ; Wed, 26 Oct 2022 13:15:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T1V32ZG9tKSMT+jultHAIQTiINzO8gq1BfBocAzoeU4=; b=uBZBwW7mjG+fGRI1VuaabJzvkrw+UCgPEzyyz0e7c6Q95YPuX5maaiLgod84GaO23/ 6uQWmyU2Iln6xbOGEQTgKAXPaYPjixmgELAOyCCToFnyvTQe2hrqdjSqSyy3s0MXq4/q hOoYqR8r2asFA5DM4LQ3ONsRERy9LM88Fgme9cAaXkYfZw+e5jsBMcDr5cMwAf0CCoBa cNa3euOfM8jYsUPk75XxvEWwv+Lyd+TEv4JgXdizZS/RaX7FjE6AVViQqYLxZm6JpUiT mTy3sv2ZF7euEyWJQl8weCjTEXmw+YDcM4mhxvtZv2Wx/V/yZ6JVOe8bi4PAOfQjS7Ps /z8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T1V32ZG9tKSMT+jultHAIQTiINzO8gq1BfBocAzoeU4=; b=eJhYyWzpYTfxcRofLxlI+aisvJRbE6yECCDUWlqyDInaMygZ5hW5FM254m2mE+DDa+ qo9G4jlU1jVWj3yDmy1vPNy1KJm/CXgSU2rY0dcFsVPEAmQGar8yphnnR9vuS2yUykmQ yOPfrGKqdxWtUD2Jftp7HcGa8Rg1PruEP7y0gWoRJCVgTW0sDy+whTBU7oJCi4ozN8HI zSSsOK8C+a2+q1IoswkD2T2+AK0dqXhWwJ+wf28sFGzvMezqpudBdcDqDjXkr6IC9Upf PMswEPKjwyvFEQ6ZlNDpLl8fN8eOhS++cg4HUGtjwRK11c/fWoPllaR7lUy/rmKNWjcD Fixw== X-Gm-Message-State: ACrzQf0/Vq10I+G4EMQFRj8k8mTQgl3ZipbF5sns8eGMiYy8Z7o2RTNY bYNGxchCiYq/+udco6ERloKYQQ== X-Google-Smtp-Source: AMsMyM52HRepg9QmAx09FkfC5UIApbYRViJuPzV8OLHMkWWncUAD7DiD02mSLYrSWFtIS1IoVgc8DQ== X-Received: by 2002:a63:6b09:0:b0:453:b1f8:bb3b with SMTP id g9-20020a636b09000000b00453b1f8bb3bmr40340965pgc.36.1666815355811; Wed, 26 Oct 2022 13:15:55 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.15.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:15:55 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 03/16] ahci: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:14 +0900 Message-Id: <20221026201527.24063-4-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::536; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate heare because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/ide/ich.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/ide/ich.c b/hw/ide/ich.c index 1007a51fcb..3b478b01f8 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -106,7 +106,7 @@ static void pci_ich9_ahci_init(Object *obj) static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) { struct AHCIPCIState *d; - int sata_cap_offset; + uint8_t sata_cap_offset; uint8_t *sata_cap; d = ICH9_AHCI(dev); int ret; @@ -130,11 +130,7 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) &d->ahci.mem); sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA, - ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE, - errp); - if (sata_cap_offset < 0) { - return; - } + ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE); sata_cap = dev->config + sata_cap_offset; pci_set_word(sata_cap + SATA_CAP_REV, 0x10); From patchwork Wed Oct 26 20:15:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05229C38A2D for ; Wed, 26 Oct 2022 20:19:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmpx-0002Jx-38; Wed, 26 Oct 2022 16:17:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmou-0001Yu-3C for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:15 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmom-00039Z-DL for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:06 -0400 Received: by mail-pj1-x102f.google.com with SMTP id m14-20020a17090a3f8e00b00212dab39bcdso3926153pjc.0 for ; Wed, 26 Oct 2022 13:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aSwPwUMn6/+jk0nmeTDn1Pce55W9fa1V9DCU5O36Vgs=; b=KJXIpzDUlBFXV0xbJLKgYeDkdK9KskhtH/AIxlIdmyWj+v2YTM/fe0DOK3gmMLMaCU tWDfuiv7aITqkyRffLDhnobSwjgfnEBzHHtAnJlf97H25cuV/yV7Y5x44J/eiFfC8b2/ hb54MUKG6n2588MtfXsfbs3Rm5ywLdFvgVrr2GEl+cK+oR4xJEGE3UAW2Xr/zJKVhaVk ldk0jn1mpnX8KMDcnOSz4V76kvrtHnl83AX5aaMZIpOXSBwX6H44DBX475NTA3mNFcae w2AepTatYaKtSElA9dwOcKSYHd52z4+bVTWLWrJXJ+7NCZAruQDZZRbCtZ/ciTaDLyLk xZ/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aSwPwUMn6/+jk0nmeTDn1Pce55W9fa1V9DCU5O36Vgs=; b=KGlgdL1aONkp1tCmzIcPFVZEqRnrJt8RZNs+uuaTUBs8hwHnPyk8DRand2/FN4Ifyx BxXC0/jwcHHFZ7TXAWhTuKtoVK9zSkn0QC7GAAuLx7CquL6Zw8JucLyaEf/eJZFwUaum PlbZVX5HhDrXtJrd5f3lR7fRyL4ntAcjemLrJvduu2rgO5/MPxmB/Ujj5UF9TGCY7U38 WhqtiZjjK1dLonecbsTvizARtmn2UwmzG8Fk0U4O3UXbSTiIMkOoY/aUxay2xwSM2cFM iiS3nG4XH0m4qQ6mEqxVQhwrUYbIvhILtCAKM+uf4ppNDVyVKVYCgCWr57bToYNh0kvC DIHg== X-Gm-Message-State: ACrzQf1Qe8Us08OS0At/GKM4fZbQzX+EieJIY8qrqfER0WSUVjzQ8P/v h6P1URR4BmAO7lJmrVyNHjJCgQ== X-Google-Smtp-Source: AMsMyM5VeXxjFm5LYbiC56VGNYlecU5lU182CbgvU+P7pPXdwt014fth+sNRtyD9f3nHFxNm1XXPsw== X-Received: by 2002:a17:90b:180e:b0:213:4abf:ed0a with SMTP id lw14-20020a17090b180e00b002134abfed0amr6112040pjb.119.1666815360919; Wed, 26 Oct 2022 13:16:00 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:16:00 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 04/16] e1000e: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:15 +0900 Message-Id: <20221026201527.24063-5-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::102f; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate heare because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/net/e1000e.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index ac96f7665a..e433b8f9a5 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -377,17 +377,10 @@ e1000e_gen_dsn(uint8_t *mac) (uint64_t)(mac[0]) << 56; } -static int +static void e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) { - Error *local_err = NULL; - int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, - PCI_PM_SIZEOF, &local_err); - - if (local_err) { - error_report_err(local_err); - return ret; - } + pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF); pci_set_word(pdev->config + offset + PCI_PM_PMC, PCI_PM_CAP_VER_1_1 | @@ -400,8 +393,6 @@ e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, PCI_PM_CTRL_PME_STATUS); - - return ret; } static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address, @@ -480,10 +471,7 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp) trace_e1000e_msi_init_fail(ret); } - if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset, - PCI_PM_CAP_DSI) < 0) { - hw_error("Failed to initialize PM capability"); - } + e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset, PCI_PM_CAP_DSI); if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset, PCI_ERR_SIZEOF, NULL) < 0) { From patchwork Wed Oct 26 20:15:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021270 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A613CC38A2D for ; Wed, 26 Oct 2022 20:26:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmpy-0002Tj-4q; Wed, 26 Oct 2022 16:17:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmov-0001ZB-4X for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:15 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmoo-00035F-OO for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:09 -0400 Received: by mail-pg1-x536.google.com with SMTP id e129so16027474pgc.9 for ; Wed, 26 Oct 2022 13:16:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MZ0hVa8YtJYr6wiX8WDzq4IS/4ZL7pxBfATieBVFI+M=; b=MA+9RUiQydqT4Ib0KZ98vOFSDziOeoEgNqGx7PAt8EwttVRRCC+rRjydRz+peoYu0A 26fR0PJayLkNBVWcuYa9m7SjBoVWsU07/8ykBZMgurEegOJ1VYoC+QoJYI3Z88bzmKVz LK5ebZj5FlgwZGrOQKkrEJux1ZX7uKX7vrAwfDgURHxEfBAZnOKOT/z9fL6yWsSvPSZI OiO/P85iMZyNGfUzmip1sJ//XmG4mc3kssabC2P6O5J+SRYXK9jcMkYwlSu5ibSCZRzb KMZtEHak+KHTgO1TI2ayQnbhfdIvMvoduhCfbsWJW+aUhAhL19UQw4aWPC/izDhzKIVs +D+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MZ0hVa8YtJYr6wiX8WDzq4IS/4ZL7pxBfATieBVFI+M=; b=P+okfDNLthKEdDXuZVL1i7GOMS0kYVnVGudC/DVboyelxMPN/AcOIbYlyGLGFhdzRt XviXyaHqQAvGFT9NrRE8n7bIrHGeeeTjLHb9VUGmFLE444/XJ7HA26jmbyjCv5Phb5Ew 9Yf1XvW/rd/8QwleyycYEOHDaeQ6/gAIX0PLYldaktVwBI/hO8fPFp9hYQUNGKypK9Pu xD+zjHqLWFpUlCPsz6TeOyJhKzBXdRAvuPmc9bSwniMCtP5eCjWRDSMOwfQh2yp2qlVp UV5e906/oW5SNJUzn5hEeQCKlDtqIz0A/4hP/JnzPuM/gpEEVWBH+Z9tZPkFU1tNExVj 5z2w== X-Gm-Message-State: ACrzQf2ELVHCXdE61aiXWy3TLvX1jYBAFJGcuk71sguUnQjycdW+TsNh g+jQtnibXwjw+FYIWFS352zFqA== X-Google-Smtp-Source: AMsMyM5gjXLTq6nHFyBfKH7unZFbb4xv1JNuuJFR3vSETZ0mArxydC0qEOyyBRLJQFyHtQe61OPI+g== X-Received: by 2002:a65:5ac8:0:b0:463:9c77:285a with SMTP id d8-20020a655ac8000000b004639c77285amr38797068pgt.517.1666815366079; Wed, 26 Oct 2022 13:16:06 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.16.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:16:05 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 05/16] eepro100: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:16 +0900 Message-Id: <20221026201527.24063-6-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::536; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate heare because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/net/eepro100.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 679f52f80f..bf2ecdded9 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -549,12 +549,7 @@ static void e100_pci_reset(EEPRO100State *s, Error **errp) if (info->power_management) { /* Power Management Capabilities */ int cfg_offset = 0xdc; - int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM, - cfg_offset, PCI_PM_SIZEOF, - errp); - if (r < 0) { - return; - } + pci_add_capability(&s->dev, PCI_CAP_ID_PM, cfg_offset, PCI_PM_SIZEOF); pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); #if 0 /* TODO: replace dummy code for power management emulation. */ From patchwork Wed Oct 26 20:15:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2FF1ECDFA1 for ; Wed, 26 Oct 2022 20:23:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmqF-0002sx-Gw; Wed, 26 Oct 2022 16:17:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmoy-0001b3-Sy for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:17 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmov-00031x-2w for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:16 -0400 Received: by mail-pg1-x52f.google.com with SMTP id g129so14407194pgc.7 for ; Wed, 26 Oct 2022 13:16:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ec4i6BMee4yKTkO53ipp611zEYxfjKiuSx03CvbSML0=; b=30HmOr60VoamG2tDcWNTs6baR/BdFbL1BKuBqa+96nOidHAiBiwXAp78axFoeNOnLp UrjKKN3Hgs76/ARZCwkbpgAnMWU0ia7pc9KbEkSwO9H+4B6Mp7U9GHsRyFdLRODLEhyx XoN3qbwZB1uAZMIzqMP110lQYTJV/Gil35nTZRTh2Fkg0unL8eg7IYH9AlD13AlVSnXE sexhg98QQZVr24octrjtn3P+btLMZE0LKVi14oUgTsEU5Kla+vYU8IeCRtuAO2ZAxNLq 7ZAPm6ylnTfbsRN+684W/QBDQQzv5U3Vfi0KvOeXGwxIh+jD3E7Azl2vvARBNMUopBSQ ZsMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ec4i6BMee4yKTkO53ipp611zEYxfjKiuSx03CvbSML0=; b=pKWbMDm4+6Hs0OJ+Xe5CJR0y7wXYQhFPaRgjQqFs+qN+2V110BxS69MZwWF/PeH+vd by4Xo1ABcnjSefLlP3R+J9AXL9OWgr45mY9+tnNz3Ut5y4Pi9w+bioqEtNZUhUDkLVLr Krhnc01lrUTm1QmcMIrBihPc1+O0it8q//Lu3jYRMH045f4tenCC852U11C9LrgSLRtx xxS4I3dsj4hfedmC/PyFUeWtWO5Ed239fE/pK3fHJ5smIfkkob74soN49ADunoSR7S0n e+xJChAvL/70AD0OD07IFeZKwo+exfbU71161LzELCvhGeERRErJUhGRe69OmNS616rJ Do4g== X-Gm-Message-State: ACrzQf045eG95jADK2NkVTG5tyHNFqE7A7X+9hR83sI1BRzZSGSvmy4l C+XiC67uDq+bszC72vi1oDsqMg== X-Google-Smtp-Source: AMsMyM6lswdIfNx/yMv74IhQfUsNehspDTH9OoXBMJzEEcCTvehbzT2ESyspxpIkzKVjE4YhR4awqA== X-Received: by 2002:a63:1301:0:b0:457:f3b7:238b with SMTP id i1-20020a631301000000b00457f3b7238bmr38771003pgl.262.1666815371354; Wed, 26 Oct 2022 13:16:11 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:16:10 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 06/16] hw/nvme: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:17 +0900 Message-Id: <20221026201527.24063-7-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::52f; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate heare because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/nvme/ctrl.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 87aeba0564..ff4e2beea6 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -7325,17 +7325,9 @@ static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset) PCI_BASE_ADDRESS_MEM_TYPE_64, bar_size); } -static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) +static void nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) { - Error *err = NULL; - int ret; - - ret = pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, - PCI_PM_SIZEOF, &err); - if (err) { - error_report_err(err); - return ret; - } + pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF); pci_set_word(pci_dev->config + offset + PCI_PM_PMC, PCI_PM_CAP_VER_1_2); @@ -7343,8 +7335,6 @@ static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) PCI_PM_CTRL_NO_SOFT_RESET); pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL, PCI_PM_CTRL_STATE_MASK); - - return 0; } static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) From patchwork Wed Oct 26 20:15:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E6F6C38A2D for ; Wed, 26 Oct 2022 20:20:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmqI-0003BR-2L; Wed, 26 Oct 2022 16:17:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmp2-0001cu-6d for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:21 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmoz-0003BW-On for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:19 -0400 Received: by mail-pj1-x102c.google.com with SMTP id l6so11552175pjj.0 for ; Wed, 26 Oct 2022 13:16:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4pfSqCSZKPH6hPwzrQBqfV/qjUVeTCARV2Lk3Wi9/is=; b=kkO4DBwqFD5a8xdmVKueAI9JMFzgKI+4zAeQhqHfOJ3+deRvEEua6j/GYxWDb8oSjJ 91Lwl4VWIpsBYeTeRau9CqMyBWGQBGf0eIpRHOJxB1+eXStcq8NWexY6+NHEBcTgGV2M rgeBuIDLwtnBkjh42fL563JwO6f9KFv5sFHZPQa+RwsAzVH9e3tbbYXWI8hwm1slvbXW xbYlX3QvM+z6aDBef7TRSuGuiZ475nUBdPSx8G/zPRWHfwN0ggzplTr/exKMA9tJJ+5m 8pAV1CywwD8mv3yMd/JDFmXSDMiYQ3XW9n3+nOQpLgR+UZHK/3Zz/XbjnxSNUGSLIpUY ZHhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4pfSqCSZKPH6hPwzrQBqfV/qjUVeTCARV2Lk3Wi9/is=; b=Bf44SXJ++Jx4274w+UUCDsUhtKdqY0/scwKSh332K4meuDlJ6qaiNTelCF3ySiLWKh iBqSFQ/f7IbxFvX9xC0CzTe79d5tFbo8XY9NU7maYHN7Nwd1TatNT/B3J+W0irweiwEK GSC/aEHsg1hgT6DAyfYupVlribDpNQfw2ooJOKkaDwDlKCoxac4Ccfv0dJ5TXAPS/t+P mpbr8ilRzJBcul49TPwKeMoxx/ogeOoWKFaTc7t3FprZ34jg6tLcJPINPv3H4reM8KWb oF1YlISXbHXzuPdyerITIJKQXzgzw9aJCQqDaAQRYGlxF2Is1oqTQcodM/57VXhRtZbJ YGoA== X-Gm-Message-State: ACrzQf0tpuenWjcA6N8TbMz4e0/Zlzv5DV/ha1F33SBlbfeT7bHmHVts POfRWoyPswAZ1BaN3aZd63mHpQ== X-Google-Smtp-Source: AMsMyM7rpgGr5YspheUalErppOgKMZxQEHP6Yf5tLO5+XdaMl7CvEVWrZ6lHxamg9mDY6iH+fNb18A== X-Received: by 2002:a17:902:968f:b0:180:a7ff:78ba with SMTP id n15-20020a170902968f00b00180a7ff78bamr5193977plp.87.1666815376515; Wed, 26 Oct 2022 13:16:16 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.16.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:16:16 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 07/16] msi: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:18 +0900 Message-Id: <20221026201527.24063-8-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::102c; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of msi_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci/msi.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/hw/pci/msi.c b/hw/pci/msi.c index 058d1d1ef1..5283a08b5a 100644 --- a/hw/pci/msi.c +++ b/hw/pci/msi.c @@ -194,7 +194,6 @@ int msi_init(struct PCIDevice *dev, uint8_t offset, unsigned int vectors_order; uint16_t flags; uint8_t cap_size; - int config_offset; if (!msi_nonbroken) { error_setg(errp, "MSI is not supported by interrupt controller"); @@ -221,13 +220,7 @@ int msi_init(struct PCIDevice *dev, uint8_t offset, } cap_size = msi_cap_sizeof(flags); - config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, - cap_size, errp); - if (config_offset < 0) { - return config_offset; - } - - dev->msi_cap = config_offset; + dev->msi_cap = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size); dev->cap_present |= QEMU_PCI_CAP_MSI; pci_set_word(dev->config + msi_flags_off(dev), flags); From patchwork Wed Oct 26 20:15:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E70F6C38A2D for ; Wed, 26 Oct 2022 20:23:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmqP-0003OU-I4; Wed, 26 Oct 2022 16:17:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmpI-0001j1-89 for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:39 -0400 Received: from mail-qv1-xf2e.google.com ([2607:f8b0:4864:20::f2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmpF-0003Cq-AV for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:36 -0400 Received: by mail-qv1-xf2e.google.com with SMTP id o8so12608859qvw.5 for ; Wed, 26 Oct 2022 13:16:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1STM3PpWdsCtuLQ0E6sPy5DYW3VO2819dTVvZ/ugr5w=; b=h7qJOryfuNJ5pn7JqLmdWxNcu0K4ODEgUVQn+em5Pj7t5SO/MmslcGLjpwKDSFxA2z pwpoS0O40CjWW6IIYYPXVJF7SYD0H2C1/hsl7FDvHYvImOL07gEkUQ1fncpIUVng88nb G7Advy8xp/ybpvuDFo6SlhJ0z0C/znPtyAKw3rBD5UI37np8E6xL1b6M4ke6BfuEAqV8 K3OuiZQoyO/xbf5/O63Yx/hmWORKfb4ErOefugKjLjsJVjRa77B9e2ZMeSQ7yQcwToEg mYlJLiABjFv8bNLCx/eHirPmGBg1U+kR2Kn+O5FzBnY1tt7yYFU8P0FPQfViq/IX+MaA 5ZwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1STM3PpWdsCtuLQ0E6sPy5DYW3VO2819dTVvZ/ugr5w=; b=OFF+QIrS7eEVDDEmJ9+wYLg/eDgvzMpADFBXBOtkx9xzjtbhsKFrvqeuQrINow/nnm Dd5l9R7rAUstxMHaaJ6cbYcOksyg3d2nY7j7SVUafkQ5Np+oFsdIQjx9+sssy+Qsp9Of 5vAeIS8YernKATRMrLn8AE64yQR0VdoVKpzsVa9lglxzFBHyXzre7QnIh4AbmlW3qSap zUl+mDHwKunL+C0tvWW6uQW0o9oypjmT08ydNsT9a4rAPJYB3KMjxLaOvSyAB99HgBa9 A4VL8Sxek4LXD4ca7g3ENcCSyRUyrj848kaSrQeDTcGk3QyzH2IfMGoyqcxgBhqtR5kw gJZw== X-Gm-Message-State: ACrzQf2kA3ZGLzkHKDiPRQl2TCcX2Q2k3kPKkOEJDf6wdSuBSyZWFXTU ipnRzIhwgogc+4ju52+w9pCczOkt0Mn3YWrl X-Google-Smtp-Source: AMsMyM5uT1aHHEmc2q8UJZNrR10qUPUeGLZeilxrMFIHdFzMULyYl6btvvroJdmJU6KNL/cB2uwmwg== X-Received: by 2002:a17:902:c942:b0:180:3f94:2975 with SMTP id i2-20020a170902c94200b001803f942975mr45333654pla.50.1666815381625; Wed, 26 Oct 2022 13:16:21 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.16.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:16:21 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 08/16] hw/pci/pci_bridge: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:19 +0900 Message-Id: <20221026201527.24063-9-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::f2e; envelope-from=akihiko.odaki@daynix.com; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of pci_bridge_ssvid_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci-bridge/i82801b11.c | 14 ++------------ hw/pci-bridge/pcie_root_port.c | 7 +------ hw/pci-bridge/xio3130_downstream.c | 8 ++------ hw/pci-bridge/xio3130_upstream.c | 8 ++------ hw/pci/pci_bridge.c | 21 ++++++--------------- include/hw/pci/pci_bridge.h | 5 ++--- 6 files changed, 15 insertions(+), 48 deletions(-) diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c index f28181e210..f45dcdbacc 100644 --- a/hw/pci-bridge/i82801b11.c +++ b/hw/pci-bridge/i82801b11.c @@ -61,21 +61,11 @@ typedef struct I82801b11Bridge { static void i82801b11_bridge_realize(PCIDevice *d, Error **errp) { - int rc; - pci_bridge_initfn(d, TYPE_PCI_BUS); - rc = pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET, - I82801ba_SSVID_SVID, I82801ba_SSVID_SSID, - errp); - if (rc < 0) { - goto err_bridge; - } + pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET, + I82801ba_SSVID_SVID, I82801ba_SSVID_SSID); pci_config_set_prog_interface(d->config, PCI_CLASS_BRIDGE_PCI_INF_SUB); - return; - -err_bridge: - pci_bridge_exitfn(d); } static const VMStateDescription i82801b11_bridge_dev_vmstate = { diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 460e48269d..a9d8c2adb4 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -74,12 +74,7 @@ static void rp_realize(PCIDevice *d, Error **errp) } pcie_port_init_reg(d); - rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, - rpc->ssid, errp); - if (rc < 0) { - error_append_hint(errp, "Can't init SSV ID, error %d\n", rc); - goto err_bridge; - } + pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, rpc->ssid); if (rpc->interrupts_init) { rc = rpc->interrupts_init(d, errp); diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 05e2b06c0c..eea3d3a2df 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -81,12 +81,8 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) goto err_bridge; } - rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, - XIO3130_SSVID_SVID, XIO3130_SSVID_SSID, - errp); - if (rc < 0) { - goto err_msi; - } + pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, + XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, p->port, errp); diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c index 5ff46ef050..d954906d79 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -71,12 +71,8 @@ static void xio3130_upstream_realize(PCIDevice *d, Error **errp) goto err_bridge; } - rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, - XIO3130_SSVID_SVID, XIO3130_SSVID_SSID, - errp); - if (rc < 0) { - goto err_msi; - } + pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, + XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, p->port, errp); diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index da34c8ebcd..30032fed64 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -42,21 +42,15 @@ #define PCI_SSVID_SVID 4 #define PCI_SSVID_SSID 6 -int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, - uint16_t svid, uint16_t ssid, - Error **errp) +void pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, + uint16_t svid, uint16_t ssid) { - int pos; + uint8_t pos; - pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, - PCI_SSVID_SIZEOF, errp); - if (pos < 0) { - return pos; - } + pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF); pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid); pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid); - return pos; } /* Accessor function to get parent bridge device from pci bus. */ @@ -455,11 +449,8 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, .mem_pref_64 = cpu_to_le64(res_reserve.mem_pref_64) }; - int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, - cap_offset, cap_len, errp); - if (offset < 0) { - return offset; - } + uint8_t offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len); memcpy(dev->config + offset + PCI_CAP_FLAGS, (char *)&cap + PCI_CAP_FLAGS, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ba4bafac7c..e499482972 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -101,9 +101,8 @@ typedef struct PXBDev PXBDev; DECLARE_INSTANCE_CHECKER(PXBDev, PXB_CXL_DEV, TYPE_PXB_CXL_DEVICE) -int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, - uint16_t svid, uint16_t ssid, - Error **errp); +void pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, + uint16_t svid, uint16_t ssid); PCIDevice *pci_bridge_get_device(PCIBus *bus); PCIBus *pci_bridge_get_sec_bus(PCIBridge *br); From patchwork Wed Oct 26 20:15:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E02F4C38A2D for ; Wed, 26 Oct 2022 20:27:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmqN-0003Lh-5P; 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Wed, 26 Oct 2022 13:16:26 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki , Jonathan Cameron Subject: [PATCH v3 09/16] pcie: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:20 +0900 Message-Id: <20221026201527.24063-10-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::430; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of a PCIe function which calls pci_add_capability() in turn is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki Acked-by: Jonathan Cameron (for CXL parts) --- docs/pcie_sriov.txt | 4 +-- hw/display/bochs-display.c | 4 +-- hw/net/e1000e.c | 4 +-- hw/pci-bridge/cxl_downstream.c | 9 ++---- hw/pci-bridge/cxl_upstream.c | 8 ++--- hw/pci-bridge/pcie_pci_bridge.c | 6 +--- hw/pci-bridge/pcie_root_port.c | 9 +----- hw/pci-bridge/xio3130_downstream.c | 7 +--- hw/pci-bridge/xio3130_upstream.c | 7 +--- hw/pci-host/designware.c | 3 +- hw/pci-host/xilinx-pcie.c | 4 +-- hw/pci/pcie.c | 52 ++++++++---------------------- hw/usb/hcd-xhci-pci.c | 3 +- hw/virtio/virtio-pci.c | 3 +- include/hw/pci/pcie.h | 11 +++---- 15 files changed, 35 insertions(+), 99 deletions(-) diff --git a/docs/pcie_sriov.txt b/docs/pcie_sriov.txt index 11158dbf88..728a73ba7b 100644 --- a/docs/pcie_sriov.txt +++ b/docs/pcie_sriov.txt @@ -49,7 +49,7 @@ setting up a BAR for a VF. pci_your_pf_dev_realize( ... ) { ... - int ret = pcie_endpoint_cap_init(d, 0x70); + pcie_endpoint_cap_init(d, 0x70); ... pcie_ari_init(d, 0x100, 1); ... @@ -79,7 +79,7 @@ setting up a BAR for a VF. pci_your_vf_dev_realize( ... ) { ... - int ret = pcie_endpoint_cap_init(d, 0x60); + pcie_endpoint_cap_init(d, 0x60); ... pcie_ari_init(d, 0x100, 1); ... diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c index 8ed734b195..111cabcfb3 100644 --- a/hw/display/bochs-display.c +++ b/hw/display/bochs-display.c @@ -265,7 +265,6 @@ static void bochs_display_realize(PCIDevice *dev, Error **errp) { BochsDisplayState *s = BOCHS_DISPLAY(dev); Object *obj = OBJECT(dev); - int ret; if (s->vgamem < 4 * MiB) { error_setg(errp, "bochs-display: video memory too small"); @@ -302,8 +301,7 @@ static void bochs_display_realize(PCIDevice *dev, Error **errp) } if (pci_bus_is_express(pci_get_bus(dev))) { - ret = pcie_endpoint_cap_init(dev, 0x80); - assert(ret > 0); + pcie_endpoint_cap_init(dev, 0x80); } else { dev->cap_present &= ~QEMU_PCI_CAP_EXPRESS; } diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index e433b8f9a5..aea4305c43 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -462,9 +462,7 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp) e1000e_init_msix(s); - if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) { - hw_error("Failed to initialize PCIe capability"); - } + pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset); ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL); if (ret) { diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index a361e519d0..1980dd9c6c 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -155,12 +155,8 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) goto err_bridge; } - rc = pcie_cap_init(d, CXL_DOWNSTREAM_PORT_EXP_OFFSET, - PCI_EXP_TYPE_DOWNSTREAM, p->port, - errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, CXL_DOWNSTREAM_PORT_EXP_OFFSET, + PCI_EXP_TYPE_DOWNSTREAM, p->port); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); @@ -195,7 +191,6 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) pcie_chassis_del_slot(s); err_pcie_cap: pcie_cap_exit(d); - err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index a83a3e81e4..26f27ba681 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -138,11 +138,8 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) goto err_bridge; } - rc = pcie_cap_init(d, CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET, - PCI_EXP_TYPE_UPSTREAM, p->port, errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET, + PCI_EXP_TYPE_UPSTREAM, p->port); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); @@ -165,7 +162,6 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) err_cap: pcie_cap_exit(d); -err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c index 1cd917a459..df5dfdd139 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -47,10 +47,7 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) goto error; } - rc = pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, errp); - if (rc < 0) { - goto cap_error; - } + pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0); pos = pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); if (pos < 0) { @@ -90,7 +87,6 @@ msi_error: aer_error: pm_error: pcie_cap_exit(d); -cap_error: shpc_cleanup(d, &pcie_br->shpc_bar); error: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index a9d8c2adb4..92cebc7cce 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -83,13 +83,7 @@ static void rp_realize(PCIDevice *d, Error **errp) } } - rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, - p->port, errp); - if (rc < 0) { - error_append_hint(errp, "Can't add Root Port capability, " - "error %d\n", rc); - goto err_int; - } + pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, p->port); pcie_cap_arifwd_init(d); pcie_cap_deverr_init(d); @@ -120,7 +114,6 @@ err: pcie_chassis_del_slot(s); err_pcie_cap: pcie_cap_exit(d); -err_int: if (rpc->interrupts_uninit) { rpc->interrupts_uninit(d); } diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index eea3d3a2df..37307c8c23 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -84,11 +84,7 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); - rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, - p->port, errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, p->port); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); pcie_cap_slot_init(d, s); @@ -113,7 +109,6 @@ err: pcie_chassis_del_slot(s); err_pcie_cap: pcie_cap_exit(d); -err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c index d954906d79..546224d97c 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -74,11 +74,7 @@ static void xio3130_upstream_realize(PCIDevice *d, Error **errp) pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); - rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, - p->port, errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, p->port); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); @@ -92,7 +88,6 @@ static void xio3130_upstream_realize(PCIDevice *d, Error **errp) err: pcie_cap_exit(d); -err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index bde3a343a2..3e4972ad76 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -414,8 +414,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) pcie_port_init_reg(dev); - pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT, - 0, &error_fatal); + pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT, 0); msi_nonbroken = true; msi_init(dev, 0x50, 32, true, true, &error_fatal); diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c index 38d5901a45..49f0ac5e35 100644 --- a/hw/pci-host/xilinx-pcie.c +++ b/hw/pci-host/xilinx-pcie.c @@ -282,9 +282,7 @@ static void xilinx_pcie_root_realize(PCIDevice *pci_dev, Error **errp) pci_bridge_initfn(pci_dev, TYPE_PCI_BUS); - if (pcie_endpoint_cap_v1_init(pci_dev, 0x80) < 0) { - error_setg(errp, "Failed to initialize PCIe capability"); - } + pcie_endpoint_cap_v1_init(pci_dev, 0x80); } static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 68a62da0b5..923ad29c52 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -151,21 +151,15 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) } } -int pcie_cap_init(PCIDevice *dev, uint8_t offset, - uint8_t type, uint8_t port, - Error **errp) +void pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) { /* PCIe cap v2 init */ - int pos; + uint8_t pos; uint8_t *exp_cap; assert(pci_is_express(dev)); - pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, - PCI_EXP_VER2_SIZEOF, errp); - if (pos < 0) { - return pos; - } + pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_SIZEOF); dev->exp.exp_cap = pos; exp_cap = dev->config + pos; @@ -185,38 +179,26 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, /* read-only to behave like a 'NULL' Extended Capability Header */ pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); } - - return pos; } -int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, - uint8_t port) +void pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, + uint8_t port) { /* PCIe cap v1 init */ - int pos; - Error *local_err = NULL; + uint8_t pos; assert(pci_is_express(dev)); - pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, - PCI_EXP_VER1_SIZEOF, &local_err); - if (pos < 0) { - error_report_err(local_err); - return pos; - } + pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_SIZEOF); dev->exp.exp_cap = pos; pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1); - - return pos; } -static int +static void pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) { uint8_t type = PCI_EXP_TYPE_ENDPOINT; - Error *local_err = NULL; - int ret; /* * Windows guests will report Code 10, device cannot start, if @@ -229,26 +211,20 @@ pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) } if (cap_size == PCI_EXP_VER1_SIZEOF) { - return pcie_cap_v1_init(dev, offset, type, 0); + pcie_cap_v1_init(dev, offset, type, 0); } else { - ret = pcie_cap_init(dev, offset, type, 0, &local_err); - - if (ret < 0) { - error_report_err(local_err); - } - - return ret; + pcie_cap_init(dev, offset, type, 0); } } -int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) +void pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) { - return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); + pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); } -int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) +void pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) { - return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); + pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); } void pcie_cap_exit(PCIDevice *dev) diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c index e934b1a5b1..0eba2b36ae 100644 --- a/hw/usb/hcd-xhci-pci.c +++ b/hw/usb/hcd-xhci-pci.c @@ -150,8 +150,7 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp) if (pci_bus_is_express(pci_get_bus(dev)) || xhci_get_flag(&s->xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { - ret = pcie_endpoint_cap_init(dev, 0xa0); - assert(ret > 0); + pcie_endpoint_cap_init(dev, 0xa0); } if (s->msix != ON_OFF_AUTO_OFF) { diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 45327f0b31..c37bdc77ea 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1862,8 +1862,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp) int pos; uint16_t last_pcie_cap_offset = PCI_CONFIG_SPACE_SIZE; - pos = pcie_endpoint_cap_init(pci_dev, 0); - assert(pos > 0); + pcie_endpoint_cap_init(pci_dev, 0); pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 798a262a0a..7a35851ae8 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -92,13 +92,12 @@ struct PCIExpressDevice { #define COMPAT_PROP_PCP "power_controller_present" /* PCI express capability helper functions */ -int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, - uint8_t port, Error **errp); -int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, - uint8_t type, uint8_t port); -int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset); +void pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port); +void pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, + uint8_t type, uint8_t port); +void pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset); void pcie_cap_exit(PCIDevice *dev); -int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset); +void pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset); void pcie_cap_v1_exit(PCIDevice *dev); uint8_t pcie_cap_get_type(const PCIDevice *dev); void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector); From patchwork Wed Oct 26 20:15:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 381DEC433FE for ; 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Wed, 26 Oct 2022 13:16:32 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:16:31 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 10/16] pci/shpc: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:21 +0900 Message-Id: <20221026201527.24063-11-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::102b; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of shpc_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci-bridge/pci_bridge_dev.c | 2 +- hw/pci-bridge/pcie_pci_bridge.c | 2 +- hw/pci/shpc.c | 23 ++++++----------------- include/hw/pci/shpc.h | 3 +-- 4 files changed, 9 insertions(+), 21 deletions(-) diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index 657a06ddbe..4b6d1876eb 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -66,7 +66,7 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp) dev->config[PCI_INTERRUPT_PIN] = 0x1; memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar", shpc_bar_size(dev)); - err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0, errp); + err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0); if (err) { goto shpc_error; } diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c index df5dfdd139..99778e3e24 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -42,7 +42,7 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) d->config[PCI_INTERRUPT_PIN] = 0x1; memory_region_init(&pcie_br->shpc_bar, OBJECT(d), "shpc-bar", shpc_bar_size(d)); - rc = shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp); + rc = shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0); if (rc) { goto error; } diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index e71f3a7483..5b3228c793 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -440,16 +440,11 @@ static void shpc_cap_update_dword(PCIDevice *d) } /* Add SHPC capability to the config space for the device. */ -static int shpc_cap_add_config(PCIDevice *d, Error **errp) +static void shpc_cap_add_config(PCIDevice *d) { uint8_t *config; - int config_offset; - config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC, - 0, SHPC_CAP_LENGTH, - errp); - if (config_offset < 0) { - return config_offset; - } + uint8_t config_offset; + config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC, 0, SHPC_CAP_LENGTH); config = d->config + config_offset; pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0); @@ -459,7 +454,6 @@ static int shpc_cap_add_config(PCIDevice *d, Error **errp) /* Make dword select and data writable. */ pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff); pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff); - return 0; } static uint64_t shpc_mmio_read(void *opaque, hwaddr addr, @@ -584,18 +578,13 @@ void shpc_device_unplug_request_cb(HotplugHandler *hotplug_dev, } /* Initialize the SHPC structure in bridge's BAR. */ -int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, - unsigned offset, Error **errp) +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset) { - int i, ret; + int i; int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */ SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc)); shpc->sec_bus = sec_bus; - ret = shpc_cap_add_config(d, errp); - if (ret) { - g_free(d->shpc); - return ret; - } + shpc_cap_add_config(d); if (nslots < SHPC_MIN_SLOTS) { return 0; } diff --git a/include/hw/pci/shpc.h b/include/hw/pci/shpc.h index d5683b7399..18ab16ec9f 100644 --- a/include/hw/pci/shpc.h +++ b/include/hw/pci/shpc.h @@ -38,8 +38,7 @@ struct SHPCDevice { void shpc_reset(PCIDevice *d); int shpc_bar_size(PCIDevice *dev); -int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, - unsigned off, Error **errp); +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned off); void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar); void shpc_free(PCIDevice *dev); void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len); From patchwork Wed Oct 26 20:15:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E5B4C38A2D for ; Wed, 26 Oct 2022 20:27:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmqS-0003Oh-RM; Wed, 26 Oct 2022 16:17:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmpN-0001lZ-2K for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:45 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmpK-0003Dq-JF for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:40 -0400 Received: by mail-pl1-x630.google.com with SMTP id io19so10336152plb.8 for ; Wed, 26 Oct 2022 13:16:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0BpmH1EK9gEiQYluMG2rP/Xfl8vYE39j2KicJvnukhs=; b=SBMgb4hlM/YGNfBUNlrmyksMpq8jtT6uk10BwzB6RtEfXxZ2CCy45zrdnQewtlaqKh Z6spmXW/UjF44hYMI05NUQF21ZH73zBgnsUqus0VazWGaq3zS2fLWwElyxYxd/2ZBG8q /Cp85AUwWKaZfVbsblyiHhKma3tnxGo5HYIU8RIXYy/bsBkMEi/qUEYLLODXWLN3eYSD HkrIRtFUGxi49Q8lceaxNHjLS7kMGgV1D3NSKUQj6Iv0v8uJNSh+mn3flN8J3w78FBzh K6LSdLj/Dx6oqJCAjSO0Rqk3tDYDvcwXBNbL+IGVw056Ih+TeG67KamkOveEegQHGjiE drtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0BpmH1EK9gEiQYluMG2rP/Xfl8vYE39j2KicJvnukhs=; b=4DznXJe0ew0V7aLCeJkfwwbwtFcBQ6jrs9RUSh+GAKpcG82jAA/WpduHgeGPYWnDgl KBRhZGyniJtjDidJ5Vp5Rt+BrvM8m4GFZiJZmdXIh084R1vLcd7cfM2J94gzw5GIE4hI YA5Q/soT+ZpzV8YymzWTbUsQZSnszFyb3aMMBBDllRRbtnZrQBED3SHIMHLa3xdBD/AM sX5kUTVDNkhXmDd8+tTULOCVokVgnh9HLKWdB3QDEIEn8RmpPYRorVHhEdS358OFzxJo RIxqOmnAspv+0YHh5vzsEdsdQbsDDs/YzZTm3+Gjm0mvFaq3MgldfF//IkLDVlrmmKH3 /MxQ== X-Gm-Message-State: ACrzQf2HWhwmZQatiJcDFFAe71xIT/kbzZJd9ic80fIdzkHmp/bcTGju pFYdzCpQ4b85qDGe3Gh1iKZJ2A== X-Google-Smtp-Source: AMsMyM7QwJMgV8DvKuPNszfsIlXYm55Pn2CWLi/bHM0M1E+F6l/+F9uU1VGiz0idcwmvjFAzqsvMog== X-Received: by 2002:a17:90a:5915:b0:20a:d6d5:31bd with SMTP id k21-20020a17090a591500b0020ad6d531bdmr6017376pji.15.1666815397228; Wed, 26 Oct 2022 13:16:37 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.16.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:16:36 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 11/16] msix: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:22 +0900 Message-Id: <20221026201527.24063-12-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::630; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of msix_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci/msix.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/pci/msix.c b/hw/pci/msix.c index 1e381a9813..28af83403b 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -311,7 +311,7 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries, uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos, Error **errp) { - int cap; + uint8_t cap; unsigned table_size, pba_size; uint8_t *config; @@ -340,11 +340,7 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries, return -EINVAL; } - cap = pci_add_capability(dev, PCI_CAP_ID_MSIX, - cap_pos, MSIX_CAP_LENGTH, errp); - if (cap < 0) { - return cap; - } + cap = pci_add_capability(dev, PCI_CAP_ID_MSIX, cap_pos, MSIX_CAP_LENGTH); dev->msix_cap = cap; dev->cap_present |= QEMU_PCI_CAP_MSIX; From patchwork Wed Oct 26 20:15:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36B12C433FE for ; Wed, 26 Oct 2022 20:24:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmqU-0003Oq-0G; Wed, 26 Oct 2022 16:17:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmpT-0001uH-Nz for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:50 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmpQ-0003Ed-3S for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:46 -0400 Received: by mail-pg1-x534.google.com with SMTP id f193so16093330pgc.0 for ; Wed, 26 Oct 2022 13:16:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xFfGOC+4AClp0N9VqAaA4RDzVVq2bpMfGkuUo72PR3Y=; b=kTRNw7UYBoR1X5DoH1oHShtzL5A5LVlJCpPUO7t2skXJg0PjGq2QE+qMKsUgESxQxN Gp+W77iqWJn3qoeQ18jsqBH/AeHOAlFSrLFmh67AZux1YbJJb82Fg/k0ZVUrfjugmPuZ XUjp4fxHMa3o87mvAv0+hr5bDNf3aoy1XWdVcdRdWWwoPI/pxtOkl+3Orloto+Rj1Lp3 1zhK/WbADZIkP3KzO9KGO1IVEqNzpe4gwoGNTsYuqQT4g8Y7YUet4kII/6J7l+sUlC8q NgeGNmOqyLU9Gdo1jKhOq3rM1E+/bTjHvAUQsrMD9ytK9UQw2bVSGdB5i3mJ86blarn+ LyTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xFfGOC+4AClp0N9VqAaA4RDzVVq2bpMfGkuUo72PR3Y=; b=PLWzjYgxG6pVulZM8r7rmB8bk6pk0kW/puKS7DzM3hvuBwOD/HUzJemoalBS8R2ZSw Cafbeuh/CnncbDBGYxP7UPqBODOWv2qJOduHYsMMnpc1AqUXK688PAVb7FDeIHLkzEaf O1Z7p9fgELL0FTrxqVFf93WbLpHDyw4maLX5ERlQ4h1HAQeIJ1eRcLQLQHqmAz63ZoQw HMxy4ByEHW/Bd1H4CoQ1dGjsvNG9Atx8MpMMFZ2scnhPxytU7XMRoEgB+j8nWKFHIiIu eVf/xmc54Jh13ceyjAy4YgHSAnQOZKJuNecEJTKNPLrw/7JXUxb1ssE6dlTANzx7Zu4q OPbA== X-Gm-Message-State: ACrzQf2HBXgJC+AFExyLftiJ0CdGWYFF+MP03/VIuB77I9C6VgKG5d9g IU+Y2ghlCHXqPnx9tumU0T7pHw== X-Google-Smtp-Source: AMsMyM4ZGUSoWTXZdQmq7yqhQHwdl0qCRuF7raqMG1MDteN/ztetnIAgjwvKimTEy423voirEZ2jdw== X-Received: by 2002:a63:101:0:b0:460:6d90:3f81 with SMTP id 1-20020a630101000000b004606d903f81mr37457659pgb.545.1666815402394; Wed, 26 Oct 2022 13:16:42 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.16.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:16:41 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 12/16] pci/slotid: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:23 +0900 Message-Id: <20221026201527.24063-13-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::534; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of slotid_cap_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci/slotid_cap.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/pci/slotid_cap.c b/hw/pci/slotid_cap.c index 36d021b4a6..5da8c82133 100644 --- a/hw/pci/slotid_cap.c +++ b/hw/pci/slotid_cap.c @@ -12,7 +12,7 @@ int slotid_cap_init(PCIDevice *d, int nslots, unsigned offset, Error **errp) { - int cap; + uint8_t cap; if (!chassis) { error_setg(errp, "Bridge chassis not specified. Each bridge is required" @@ -24,11 +24,7 @@ int slotid_cap_init(PCIDevice *d, int nslots, return -EINVAL; } - cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, - SLOTID_CAP_LENGTH, errp); - if (cap < 0) { - return cap; - } + cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, SLOTID_CAP_LENGTH); /* We make each chassis unique, this way each bridge is First in Chassis */ d->config[cap + PCI_SID_ESR] = PCI_SID_ESR_FIC | (nslots << SLOTID_NSLOTS_SHIFT); From patchwork Wed Oct 26 20:15:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021268 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3FA82C433FE for ; Wed, 26 Oct 2022 20:24:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmqV-0003P1-1W; Wed, 26 Oct 2022 16:17:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmpb-0001w4-AI for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:56 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmpV-0003BV-BM for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:52 -0400 Received: by mail-pl1-x629.google.com with SMTP id y4so15300258plb.2 for ; Wed, 26 Oct 2022 13:16:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+9Hvu5m8f5nzPBzUo9RBA72FD6lUa6YAEOOW8pwxlMM=; b=VgAA/NY+9y1DHEPBzNEOX3h+nRKzNQYByy8Me/I2sR823nVLmLnv3kgIVkRi3alZx9 oi6gkA1bXjsaSS/qU/NUAihD+b3j5/usFn1EOQl4x2cwkiRhL33HeNBRkt3B1k5g1p+d e973f/oRC+5QHjqpEw/G62HdjEOXM+2tQBRdmqRMIY7J8GuR2Q3jOdhAT2ZWzVZkjCmy GZlSRTiJ/BcJUowue6kpKifBEUIXgebxJJF4aThsjH8AnT+hh3SE3LeXESx/xrVL9ewV 5bPvO8LYUbDK9WwYW7I1ybLbjlkw6H1wMXIY3gTsm01B+qR/lR78PH4S9XnfMRCcCO8e GASw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+9Hvu5m8f5nzPBzUo9RBA72FD6lUa6YAEOOW8pwxlMM=; b=n/si3PswPTqpt4/r8TDCAx7ZwL9TLuK+RaJ/+bYSqXHu0SN4uEhWWEygl2GVBlVXeY VCN8idYg0EPVPWjwndeHuCmDUpNlRh6sqzg4cpgl/R2rK/ijculAnffgWT+2Dn7i9QaA ymcfZqJ5Pl2i9C5ZfTatqPRzzunr+K9+swHFbaKMAvmjptyElkrN5/v622HRhGnT9uRd oi2i+yFuhLv13MXh/CdnbxCmRiE0Ngv7oAoIazuyRdy+ODfzIL/AlNkkdBNIyK/NsEdU Ywh8LziGA+bFbtvoO8Gbx8AIh5kPAz8OyxG136TpJdnx6iKjZQxHVlRVw6jtJCCC44g0 hDZg== X-Gm-Message-State: ACrzQf2IiHPvb5aC+WoOzxe8fsteyrnsOlV0dISUolSm1QTB1fVMmpYy mvDnE/RsZ2Ga4+YoEe3c0HbPig== X-Google-Smtp-Source: AMsMyM6M0VFRripvMdvl6e0GCNbjm1qML6PVPTwXHyI/dDWaHyphq/MQdKbjcHr6rzXLxBBRPdROEw== X-Received: by 2002:a17:90b:3882:b0:212:f4e9:ceb0 with SMTP id mu2-20020a17090b388200b00212f4e9ceb0mr5920316pjb.135.1666815407485; Wed, 26 Oct 2022 13:16:47 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.16.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:16:46 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 13/16] hw/pci-bridge/pcie_pci_bridge: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:24 +0900 Message-Id: <20221026201527.24063-14-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::629; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate heare because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/pci-bridge/pcie_pci_bridge.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c index 99778e3e24..1b839465e7 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -35,7 +35,7 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) { PCIBridge *br = PCI_BRIDGE(d); PCIEPCIBridge *pcie_br = PCIE_PCI_BRIDGE_DEV(d); - int rc, pos; + int rc; pci_bridge_initfn(d, TYPE_PCI_BUS); @@ -49,12 +49,8 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0); - pos = pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); - if (pos < 0) { - goto pm_error; - } - d->exp.pm_cap = pos; - pci_set_word(d->config + pos + PCI_PM_PMC, 0x3); + d->exp.pm_cap = pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF); + pci_set_word(d->config + d->exp.pm_cap + PCI_PM_PMC, 0x3); pcie_cap_arifwd_init(d); pcie_cap_deverr_init(d); @@ -85,7 +81,6 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) msi_error: pcie_aer_exit(d); aer_error: -pm_error: pcie_cap_exit(d); shpc_cleanup(d, &pcie_br->shpc_bar); error: From patchwork Wed Oct 26 20:15:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021266 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26AF7C433FE for ; Wed, 26 Oct 2022 20:23:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmqd-0003P5-Ka; Wed, 26 Oct 2022 16:17:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmpd-0001y2-Rw for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:59 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmpa-0003Kh-S0 for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:16:57 -0400 Received: by mail-pj1-x1035.google.com with SMTP id d13-20020a17090a3b0d00b00213519dfe4aso3252188pjc.2 for ; Wed, 26 Oct 2022 13:16:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uZ+rbtMJHioQ9msZsjYArFAk2F7yFVCrTnD/IAdjoug=; b=zqvt772HiKf9DvnOyMFznUjuBDA7I+zzIHvXslbPRzBEsCyNancK0mTZKKN13fxn2u lH/YxWaUXuf0jZRyWjWIAfAB2HeKRFPwQ9JlFdENuxB+UPKu39AXDAbyWo2ZSF6yLaT6 BR4JSNYxIbIWQKUir1wbkTEan92rXGuZP2V99Ni9PEhcqm1EqvnI3d2l3McMdqWLJHWW ++ytVQxcR5hxQBMXVnF/BSGshe68EIE+vM/0aQ01OVrM5a9YDOOc3/rgUT0omfH8nmh3 kbWp91kiHDmV15LAz80oFKbFI4igTUc9DYxkNBVH+Mnc/N29wySHRDHtFYe1bteJaWI7 NjKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uZ+rbtMJHioQ9msZsjYArFAk2F7yFVCrTnD/IAdjoug=; b=cCltSuDanhQbtUxiXkIAlbZgSEFAnkFhyQ2mc3yvHMvMkLfInGxG07P2jacwl1a5Kb h5k34VWmwl3qmgFjMKj77bL18rMCXLfZOpr1tPIHlgkofHa45Mb4W77K6V/ZCkM8bthy QtDRHd0sfa1/uwX7H5VUtCFWWvorxcDMpFHcUCCc+KiYDIoCk4XemISvPHEmW/3JZtJE n7o2YNSeL13DY/2uJ8TnCujGFDf0VTMljzY47LwIjhzFOu6jkTxN+IQInV01ys4qXnmg UvJQ5bNx5cjHtWUBfUlxwOAR+JWzFALkWVc/3FrpabSCV90eoAHxyuPQ662WSCh0NNuG kyBg== X-Gm-Message-State: ACrzQf1alMatbTYofqbuICeqSN1+68EvSWwO8e5J/d+49NoZMRToyqUe 4y5uGvFvtPbhFi3g2UPjqBM/1A== X-Google-Smtp-Source: AMsMyM5dR2Xte2D2ennF96NdArMawAgLItP6t78Atqrr/O1t1QCuEclcPr74fLyMi+QHesCdo42epg== X-Received: by 2002:a17:90a:9902:b0:213:1122:feb9 with SMTP id b2-20020a17090a990200b002131122feb9mr5989086pjp.58.1666815412574; Wed, 26 Oct 2022 13:16:52 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:16:52 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 14/16] hw/vfio/pci: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:25 +0900 Message-Id: <20221026201527.24063-15-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::1035; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The code generating errors in pci_add_capability has a comment which says: > Verify that capabilities don't overlap. Note: device assignment > depends on this check to verify that the device is not broken. > Should never trigger for emulated devices, but it's helpful for > debugging these. Indeed vfio has some code that passes capability offsets and sizes from a physical device, but it explicitly pays attention so that the capabilities never overlap. Therefore, in pci_add_capability(), we can always assert that capabilities never overlap, and that is what happens when omitting errp. Signed-off-by: Akihiko Odaki --- hw/vfio/pci-quirks.c | 15 +++------------ hw/vfio/pci.c | 14 +++++--------- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index f0147a050a..e94fd273ea 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1530,7 +1530,7 @@ const PropertyInfo qdev_prop_nv_gpudirect_clique = { static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp) { PCIDevice *pdev = &vdev->pdev; - int ret, pos = 0xC8; + int pos = 0xC8; if (vdev->nv_gpudirect_clique == 0xFF) { return 0; @@ -1547,11 +1547,7 @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp) return -EINVAL; } - ret = pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add NVIDIA GPUDirect cap: "); - return ret; - } + pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8); memset(vdev->emulated_config_bits + pos, 0xFF, 8); pos += PCI_CAP_FLAGS; @@ -1718,12 +1714,7 @@ static int vfio_add_vmd_shadow_cap(VFIOPCIDevice *vdev, Error **errp) return -EFAULT; } - ret = pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, - VMD_SHADOW_CAP_LEN, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add VMD MEMBAR Shadow cap: "); - return ret; - } + pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, VMD_SHADOW_CAP_LEN); memset(vdev->emulated_config_bits + pos, 0xFF, VMD_SHADOW_CAP_LEN); pos += PCI_CAP_FLAGS; diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 939dcc3d4a..2b653d01e3 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1826,7 +1826,7 @@ static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos, vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); } -static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, +static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, uint8_t pos, uint8_t size, Error **errp) { uint16_t flags; @@ -1943,11 +1943,7 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, 1, PCI_EXP_FLAGS_VERS); } - pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, - errp); - if (pos < 0) { - return pos; - } + pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); vdev->pdev.exp.exp_cap = pos; @@ -2045,14 +2041,14 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp) case PCI_CAP_ID_PM: vfio_check_pm_reset(vdev, pos); vdev->pm_cap = pos; - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; case PCI_CAP_ID_AF: vfio_check_af_flr(vdev, pos); - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; default: - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; } From patchwork Wed Oct 26 20:15:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E1D2C38A2D for ; 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Wed, 26 Oct 2022 13:16:57 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:16:57 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 15/16] virtio-pci: Omit errp for pci_add_capability Date: Thu, 27 Oct 2022 05:15:26 +0900 Message-Id: <20221026201527.24063-16-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::102e; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate heare because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/virtio/virtio-pci.c | 9 ++------- include/hw/virtio/virtio-pci.h | 2 +- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index c37bdc77ea..b393ff01be 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1154,8 +1154,7 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy, PCIDevice *dev = &proxy->pci_dev; int offset; - offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, - cap->cap_len, &error_abort); + offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, cap->cap_len); assert(cap->cap_len >= sizeof *cap); memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len, @@ -1864,11 +1863,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp) pcie_endpoint_cap_init(pci_dev, 0); - pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, - PCI_PM_SIZEOF, errp); - if (pos < 0) { - return; - } + pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF); pci_dev->exp.pm_cap = pos; diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index 2446dcd9ae..9f3736723c 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -141,7 +141,7 @@ struct VirtIOPCIProxy { uint32_t msix_bar_idx; uint32_t modern_io_bar_idx; uint32_t modern_mem_bar_idx; - int config_cap; + uint8_t config_cap; uint32_t flags; bool disable_modern; bool ignore_backend_features; From patchwork Wed Oct 26 20:15:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13021258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9686C38A2D for ; Wed, 26 Oct 2022 20:18:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1onmqi-0003Ze-4P; Wed, 26 Oct 2022 16:18:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1onmpm-00022u-CY for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:17:07 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1onmpk-0003BV-1R for qemu-devel@nongnu.org; Wed, 26 Oct 2022 16:17:05 -0400 Received: by mail-pl1-x629.google.com with SMTP id y4so15300962plb.2 for ; Wed, 26 Oct 2022 13:17:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NqszKtwi0YXXdx0iWSFUDJDEOg8IoBblvu8lJaEmuhg=; b=q7Hq+o3eP6zf4jrVp6qhuK//2yHpTDo+4TFVsk8xmufhdYg0EbA4HXRfwYiIrf6RIi SdIG2o+bN04dMhFHmAErxl1bkehFc9bSgYNPXd4mX706DJBP64+C0DRbaTRU8cN1yrxY PzOm6oII7Si95aWzMrWEyInsq5PYoLEvIgitKmAxyunfWdwPPdiWrJUHmJ5sEj2q06A5 y9hEj13ePO0YMJUt3BrWEzAOvKwhsrkKAoWVG356q0DZlxibU98nGfInQmkRuzgPsCQI DtcWYztLvSRan6XI27Bjp2H0uwfu+1yXlLIfazFAvDd2HmKQqnEi6lKJ4VDwe+okUDDq GU7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NqszKtwi0YXXdx0iWSFUDJDEOg8IoBblvu8lJaEmuhg=; b=AA4xVi5vP9hnN2kVdqAPmA1FTT42QaBLaQqrT9BUGf62yTkCY2ENZ35M7iHmaSBA2y pTBDNRy9hN7o85mHALXVZ6nVIEu3oDSn5kn1ZPA9HnSqYDHG+SeOzwqpqcT3pR3isRvN Hz+cYvYa2WC0+5ncBTKIei1xkk3DzJ+Ylm/a9vmo5x5FkQ9kzyhzFWPQez7lJm1eST01 9QJHSssHAv9Iwb1Doinpzp0O+wBmNXO+gKk1qABFdXniPgrhRLFcI8UoQd/AFEY5M+0J 6Q7a+RcNtEBO+20j811AFm5+pUPnllzLYp3MqS3RdrCgNN+VvFecx56bAGLnBM8BRrz5 NaOQ== X-Gm-Message-State: ACrzQf0GuDIKEqINlt36eDgxHxTOTha8TwTnu5CmiED7lxtwRabtRUVJ 0XL2GatlIut44p3+jzZC1IxfWA== X-Google-Smtp-Source: AMsMyM4+65ZXYnfwyas0ds07t7tBxAMDQLkZ06HDEMbSlw+TqWbq5OYrEqZFgACxybsuzXPGKqR9SA== X-Received: by 2002:a17:90a:6045:b0:212:fe9a:5792 with SMTP id h5-20020a17090a604500b00212fe9a5792mr5934966pjm.178.1666815422831; Wed, 26 Oct 2022 13:17:02 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id y5-20020aa78f25000000b00541c68a0689sm3375770pfr.7.2022.10.26.13.16.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:17:02 -0700 (PDT) From: Akihiko Odaki To: Cc: Alex Williamson , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v3 16/16] pci: Remove legacy errp from pci_add_capability Date: Thu, 27 Oct 2022 05:15:27 +0900 Message-Id: <20221026201527.24063-17-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221026201527.24063-1-akihiko.odaki@daynix.com> References: <20221026201527.24063-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::629; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Akihiko Odaki --- hw/pci/pci.c | 29 +++++++---------------------- include/hw/pci/pci.h | 12 ++---------- 2 files changed, 9 insertions(+), 32 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 8ee2171011..8ff71e4553 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2513,38 +2513,23 @@ static void pci_del_option_rom(PCIDevice *pdev) } /* - * On success, pci_add_capability_legacy() returns a positive value - * that the offset of the pci capability. - * On failure, it sets an error and returns a negative error - * code. + * pci_add_capability() returns a positive value that the offset of the pci + * capability. */ -int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp) +uint8_t pci_add_capability(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size) { uint8_t *config; - int i, overlapping_cap; + int i; if (!offset) { offset = pci_find_space(pdev, size); /* out of PCI config space is programming error */ assert(offset); } else { - /* Verify that capabilities don't overlap. Note: device assignment - * depends on this check to verify that the device is not broken. - * Should never trigger for emulated devices, but it's helpful - * for debugging these. */ + /* Verify that capabilities don't overlap. */ for (i = offset; i < offset + size; i++) { - overlapping_cap = pci_find_capability_at_offset(pdev, i); - if (overlapping_cap) { - error_setg(errp, "%s:%02x:%02x.%x " - "Attempt to add PCI capability %x at offset " - "%x overlaps existing capability %x at offset %x", - pci_root_bus_path(pdev), pci_dev_bus_num(pdev), - PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), - cap_id, offset, overlapping_cap, i); - return -EINVAL; - } + assert(!pci_find_capability_at_offset(pdev, i)); } } diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 51fd106f16..2a5d4b329f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -2,7 +2,6 @@ #define QEMU_PCI_H #include "exec/memory.h" -#include "qapi/error.h" #include "sysemu/dma.h" /* PCI includes legacy ISA access. */ @@ -391,15 +390,8 @@ void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, void pci_unregister_vga(PCIDevice *pci_dev); pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); -int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp); - -#define PCI_ADD_CAPABILITY_VA(pdev, cap_id, offset, size, errp, ...) \ - pci_add_capability_legacy(pdev, cap_id, offset, size, errp) - -#define pci_add_capability(...) \ - PCI_ADD_CAPABILITY_VA(__VA_ARGS__, &error_abort) +uint8_t pci_add_capability(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size); void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);