From patchwork Thu Oct 27 12:34:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 13022034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94E53FA3744 for ; Thu, 27 Oct 2022 12:35:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235692AbiJ0MfC (ORCPT ); Thu, 27 Oct 2022 08:35:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235677AbiJ0Me6 (ORCPT ); Thu, 27 Oct 2022 08:34:58 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C61A2A403 for ; Thu, 27 Oct 2022 05:34:54 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id 13so4146658ejn.3 for ; Thu, 27 Oct 2022 05:34:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=58sYynw6bix2RKRPDkbfBnZH4v9198VFqnJiB91dB9c=; b=Ty/6hZUJ1X2VyFW1MicXfNUTdObwmpOpub6MQ0LNu19jr0Pl7weLAje8hoT6dKs7MO KoWcjlezPL6ZtxyRTBLZim76qPe5c3rLUit4cK5KirwQILB7LZmS8YhvHw28JZS1VkUj hTfQPT8pk+xxJtVdoDnuRR5G6cMzv3yoHmDnOD6iQmKq1MLH0JL4bdtKE5DdQuH1Qxsq GSkUIQd1Lcst0ybP/vStyBxNsUGyOpQtiaqYPP2ujSA0yMq1ZIWrp/Q/CHxZEwMuVkDf aJcK6ynpkDmcFserIj+jiGZ0F12GgxrIblrlD42sA7p+bKQCvyRzubJBzrTza5C4P/8m 0QzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=58sYynw6bix2RKRPDkbfBnZH4v9198VFqnJiB91dB9c=; b=FpBKKp+6MPgy/j311eyXOOjqEga88Rj2J4vibP5E3thrim3RECDau3dk5NZ9uRFRNr T5XUuHDorzK8Eso1zFK7wG/DaREY0q3puQR4zsbVu7x6U6ULhB+YMhphB+Ui3pEaTc5b 0cLY5y5Ro+3BRJ8ck2OQc8UaPU6BgWSnUbZB7ohPJDRAtF7Pj8cEz0hMPrvEIJnZ56v1 uFe0TAoNCPbyWLUwNUsCNVgrgQFIRc6JYYoOoLjTFfUU+1lEWLqykhkKPxsoppdF9+E/ 5ERsyFYKJMACij/+1HrYkXUbI5R1nB6GalWjknSs6HA8DIzIJLwop9UD2POHR9zrsOZ6 v8KQ== X-Gm-Message-State: ACrzQf0/GcOhh7Ntl9YpKXJ0ZJGkj0s7GIKLlx5RHqYW3ifCnLIimeg3 fRShYKdWZGyMU8cr2IlG0jauWg== X-Google-Smtp-Source: AMsMyM7DoKhqR3Dhq01/mKNdjxj0bW8sExFf7e0S3rGOE4W93t2zItOnY1cIYAieejN2cuxGvjSbrA== X-Received: by 2002:a17:907:7ea6:b0:791:81f4:b0e3 with SMTP id qb38-20020a1709077ea600b0079181f4b0e3mr42578813ejc.164.1666874092720; Thu, 27 Oct 2022 05:34:52 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id p22-20020aa7d316000000b00461c1804cdasm942868edq.3.2022.10.27.05.34.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 05:34:49 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss Subject: [PATCH v1 1/5] clk: qcom: dispcc-sm8250: Disable EDP_GTC for sm8350 Date: Thu, 27 Oct 2022 14:34:28 +0200 Message-Id: <20221027123432.1818530-1-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SM8350 does not have the EDP_GTC clock, so let's disable it for this SoC. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 709076f0f9d7..180ac2726f7e 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1330,6 +1330,9 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; disp_cc_pll1.vco_table = lucid_5lpe_vco; + + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL; + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL; } clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); From patchwork Thu Oct 27 12:34:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 13022035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9B6BFA3747 for ; Thu, 27 Oct 2022 12:35:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235686AbiJ0MfD (ORCPT ); Thu, 27 Oct 2022 08:35:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235688AbiJ0MfA (ORCPT ); Thu, 27 Oct 2022 08:35:00 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F44A2E6A5 for ; Thu, 27 Oct 2022 05:34:57 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id n12so4057129eja.11 for ; Thu, 27 Oct 2022 05:34:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VcEVo6Z2/qPT9+/9Yb7zhm6sGgG565lVOHvBECCbpGE=; b=C49XxZlFTYcnQvGECbJgR6sqQErGlpnvl9MoLEC9Gi/QX6VcVT1N5vchIWUAL7S6vA I+uP4w6Pnz+a6sO8d087MKHOw04HxFb2+G6U20f6FAPKku//97yGCJUGrids71sGlP6K 2NIGIhqjELSU7Es1gePzOlL7Tc86z+AcxxsbcCJOshwQKbZ6etPKox4b7ZXFz8MtsC+e SgvYkyOghP/pht4ZtoqBA0ymhCnaPmq+83+hyrrnLDBWIB7UV91WwfnEXS72lk84JO5O mTTbrFkySnOQw4nKJzZlYKFcg9hiWtr1wX+d6K8TQmw4AhSxqdyqK1JientWpHf0DAu9 e1cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VcEVo6Z2/qPT9+/9Yb7zhm6sGgG565lVOHvBECCbpGE=; b=hRM4x6ynRFVlnNFTcXYdzY6s+oXfIWf8T0DICCsJ+fN2ca22MfScELowB2JB/a37Tb UqIpZJdzuWyYnRayIaEieMzkJA6TP+Rz88z3T57zxEV1qLpqE8nsPmqK4hKzg/5f+zgs oJngO7Hko0jAJr59fEuC8JpI7iTQAzPI8ttnGcfobgpe7J4t8nj10f0FklFzo3U1TXyb NKEnGvEQ0mn/H/AXwJIFNfA99y8J2WzNHD4/AToxWRqD4krkTtGm9il+O8DzVLfPkmhO vb9Qd3+y0DJOb4AmMlN028V/lKeSTB05cIbFZRtz0Ny9oCE3/iwCvCkZiBEnFwvVEbyZ /6fA== X-Gm-Message-State: ACrzQf2KPEHL5tHVmQKzplDipBHsDyTfQVm8jzoxuD1XJC4tSRePGpzI XjOrFGu03zQNeVqehrXq4IB/Yw== X-Google-Smtp-Source: AMsMyM5beE+Pn8wyGNJSTHZnazscU3w3YdlTA4dVfNrynbksR2HP0pOhjX6lRbKDF6Ng/EOsGEIcoA== X-Received: by 2002:a17:906:846a:b0:7ad:84cd:f2a9 with SMTP id hx10-20020a170906846a00b007ad84cdf2a9mr5210255ejc.244.1666874095981; Thu, 27 Oct 2022 05:34:55 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id p22-20020aa7d316000000b00461c1804cdasm942868edq.3.2022.10.27.05.34.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 05:34:54 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss Subject: [PATCH v1 2/5] clk: qcom: dispcc-sm8250: Add RETAIN_FF_ENABLE flag for mdss_gdsc Date: Thu, 27 Oct 2022 14:34:29 +0200 Message-Id: <20221027123432.1818530-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027123432.1818530-1-robert.foss@linaro.org> References: <20221027123432.1818530-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org All SoC supported by this driver supports the RETAIN_FF_ENABLE flag, so it should be enabled here. This feature enables registers to maintain their state after dis/re-enabling the GDSC. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/dispcc-sm8250.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 180ac2726f7e..a7606580cf22 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1137,7 +1137,7 @@ static struct gdsc mdss_gdsc = { .name = "mdss_gdsc", }, .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL, + .flags = HW_CTRL | RETAIN_FF_ENABLE, }; static struct clk_regmap *disp_cc_sm8250_clocks[] = { From patchwork Thu Oct 27 12:34:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 13022036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5673FA374B for ; Thu, 27 Oct 2022 12:35:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235677AbiJ0MfF (ORCPT ); Thu, 27 Oct 2022 08:35:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235694AbiJ0MfD (ORCPT ); Thu, 27 Oct 2022 08:35:03 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0AE62A274 for ; Thu, 27 Oct 2022 05:35:00 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id sc25so4061881ejc.12 for ; Thu, 27 Oct 2022 05:35:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GguWBmMxuPAY2KQo1afCUSS9/tVl4wLkJY905lNiYD4=; b=jthoUlFpIsjC/8l5QHbXH0+WvEfyz7zIilqN3bcy5VprOvwCIMtelJbVIcWfJACETr Cmpxw6+aF8Nr5oYX/yHAe9qJpP08bGzg+wckphjBXsF22N57FCxZL5u0bCIQwQ/81ZN+ 8g+i9jkxTegDZu52cSeh2EcTVOXe56ABGu/oqNT725W3qppQgo4yhecet8A6aWVDm7bz DR7RauXB11T+d7K78Y3GqUlt+03M7CQPxh9hc+vveKpXx8yqXIe97Yi1QIqcWoPqX/mM aJO7M+cRcqXykWKQp4EL2i8Y8ruFsLO+3zHkWAPUreNW8yf/k0MBsTM/sA3F2aOZsM2u +Hyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GguWBmMxuPAY2KQo1afCUSS9/tVl4wLkJY905lNiYD4=; b=n/VOfGUcogXo+GEmBqgUWDQvvqoEWCwQ3jtHwL7IlByDPgsYvxv0CPhx4LJ4nCzZEU sBKpawJiAHxSWSNnmPB1wfTXD1gkj27mhsHCxqBwi0CBxVfgqlgD/1t4YY0Fe+RmlQrk 9Q6lvg9olXuacknpDk2ej6EjH3WeYrdMOskI+XiN1pOaquNDFw90FiGG1PJkgKH+em74 pzVUEj8dTu1q+0V0nG92IAAagq7xMJ/jpU5qx8KokRlj6Fp5wbuDOusC+rA+R3+COXxX R5ix3gIurww0c7TPS/yWg+VwOqOWPwgola05krogCKjuthTcDIbNITGxou+m8gui961S Vxjw== X-Gm-Message-State: ACrzQf1L8JMmm9l+rSrZheXZTc9masEW8F7jfFXKVMjkVNOs+0qNu2PF 8w+1xHrdsaaQlTUDA2Imuagt4g== X-Google-Smtp-Source: AMsMyM5dpxxeUjefAGYUGbMX8MzgawlzvmJSVrStgHHjubyrh9IoO/p/m3JQJrULd9gZAQV/iQjfXQ== X-Received: by 2002:a17:906:5dce:b0:78d:e71a:6e0 with SMTP id p14-20020a1709065dce00b0078de71a06e0mr41282781ejv.360.1666874099339; Thu, 27 Oct 2022 05:34:59 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id p22-20020aa7d316000000b00461c1804cdasm942868edq.3.2022.10.27.05.34.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 05:34:57 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss Subject: [PATCH v1 3/5] dt-bindings: clock: dispcc-sm8250: Add EDP_LINK_DIV_CLK_SRC index Date: Thu, 27 Oct 2022 14:34:30 +0200 Message-Id: <20221027123432.1818530-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027123432.1818530-1-robert.foss@linaro.org> References: <20221027123432.1818530-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add this previously missing index, since it is supported by the SoCs targeted by the dispcc-sm8250 driver. Signed-off-by: Robert Foss Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,dispcc-sm8250.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h b/include/dt-bindings/clock/qcom,dispcc-sm8250.h index ce001cbbc27f..767fdb27e514 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sm8250.h +++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h @@ -64,6 +64,7 @@ #define DISP_CC_MDSS_EDP_LINK_INTF_CLK 54 #define DISP_CC_MDSS_EDP_PIXEL_CLK 55 #define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 56 +#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 57 /* DISP_CC Reset */ #define DISP_CC_MDSS_CORE_BCR 0 From patchwork Thu Oct 27 12:34:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 13022037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B4CFECAAA1 for ; Thu, 27 Oct 2022 12:35:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235718AbiJ0MfL (ORCPT ); Thu, 27 Oct 2022 08:35:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235696AbiJ0MfH (ORCPT ); Thu, 27 Oct 2022 08:35:07 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48DE2317E1 for ; Thu, 27 Oct 2022 05:35:04 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id n12so4058362eja.11 for ; Thu, 27 Oct 2022 05:35:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lIJ03Xw0TJ9vybpwIm3D1pwjE8baT2lTF928XHppw+c=; b=UDJHQX5F1+HJfrDukPs3mJ/PyfNV71XB5EAcXSt6rRnM68geyipM6er0gGDj8PJtTY PR9jabiZ01oV1zU2O6bN4md/MhXCoSbu4PXkcaxaC/t3dJg29yWc3hn90f4GFURT9kmO qlHkV4ifi5DiMosbPzDpO990BI6sk7z2831VvQLYWEwAvIzQ19jHpcVeiW3R5EhK+zVi vvLd9uWkwNlGvDQbx4S8lMLymIwZWGRGta3GW9SRvuTwx6PelnyHSKI+X5bZY9hkOhkR FjtKWurGLzuLAcS5TJGATLBIaUTtDJe//VY5vWDbbrQmOVfC1TpUedZQW7obm2TcmXAB fbzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lIJ03Xw0TJ9vybpwIm3D1pwjE8baT2lTF928XHppw+c=; b=00oJ9EZeYgZq5jL6dsfLXK6liAPYNycz6inDuNsvKqeqPiKalMIQVvDCUJ7AC5Y7mg Ed11ShxX+gWmm3I0E8sT7aG28GcK2auxGCDikxqXyJaNfY1fB6YOAxFZJ8luJT7ljD3x EIEGmV0I2dkCF8J99eUgchlcdv14mCa56eZhYWJ8avMzhS8WTrDQ0SQ+ayQs0z3pbpH1 d6Icur9jZ5S6oD0r6KcotU6ZMDZ4a8VsXtViziUamBW8aD+vLoME8XiKcH8lMdCaDQKq E88Co1WGd9UJXnMFcgK40p8+yEgMcEMq6XZhXmLkrLUvI0sejiO2+9VYSyvZepMkVM9k uVfw== X-Gm-Message-State: ACrzQf2K5443vUjHxcUbslO5mhqGn46XWcOVUyg+1Gqc8q37KhbKGmAv 2QnEnhTmMtvMFCCdSYL0V0S54A== X-Google-Smtp-Source: AMsMyM5v+wIehh3xMHkm3Xq4njARTH8MwPQOyhlQaPRd0/CiAivhPlxuCeckHTp1JM6stAj4gVnA6Q== X-Received: by 2002:a17:906:9750:b0:798:9ccc:845d with SMTP id o16-20020a170906975000b007989ccc845dmr32913588ejy.760.1666874104546; Thu, 27 Oct 2022 05:35:04 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id p22-20020aa7d316000000b00461c1804cdasm942868edq.3.2022.10.27.05.34.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 05:35:01 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss Subject: [PATCH v1 4/5] clk: qcom: dispcc-sm8250: Add missing EDP clocks for sm8350 Date: Thu, 27 Oct 2022 14:34:31 +0200 Message-Id: <20221027123432.1818530-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027123432.1818530-1-robert.foss@linaro.org> References: <20221027123432.1818530-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SM8350 supports embedded displayport, but the clocks for this were previously not enabled. Signed-off-by: Robert Foss --- drivers/clk/qcom/dispcc-sm8250.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index a7606580cf22..d2aaa44ed3d4 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -462,6 +462,20 @@ static struct clk_branch disp_cc_mdss_edp_link_clk = { }, }; +static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = { + .reg = 0x2288, + .shift = 0, + .width = 2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_edp_link_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &disp_cc_mdss_edp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_regmap_div_ro_ops, + }, +}; + static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { .halt_reg = 0x2074, .halt_check = BRANCH_HALT, @@ -471,7 +485,7 @@ static struct clk_branch disp_cc_mdss_edp_link_intf_clk = { .hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_edp_link_intf_clk", .parent_hws = (const struct clk_hw*[]){ - &disp_cc_mdss_edp_link_clk_src.clkr.hw, + &disp_cc_mdss_edp_link_div_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_GET_RATE_NOCACHE, @@ -1175,6 +1189,7 @@ static struct clk_regmap *disp_cc_sm8250_clocks[] = { [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr, [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr, [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr, + [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_edp_link_div_clk_src.clkr, [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr, [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr, [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr, @@ -1285,7 +1300,11 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) &disp_cc_mdss_dp_pixel1_clk_src, &disp_cc_mdss_dp_pixel2_clk_src, &disp_cc_mdss_dp_pixel_clk_src, + &disp_cc_mdss_edp_aux_clk_src, + &disp_cc_mdss_edp_link_clk_src, + &disp_cc_mdss_edp_pixel_clk_src, &disp_cc_mdss_esc0_clk_src, + &disp_cc_mdss_esc1_clk_src, &disp_cc_mdss_mdp_clk_src, &disp_cc_mdss_pclk0_clk_src, &disp_cc_mdss_pclk1_clk_src, @@ -1297,6 +1316,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) &disp_cc_mdss_byte1_div_clk_src, &disp_cc_mdss_dp_link1_div_clk_src, &disp_cc_mdss_dp_link_div_clk_src, + &disp_cc_mdss_edp_link_div_clk_src, }; unsigned int i; static bool offset_applied; From patchwork Thu Oct 27 12:34:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 13022038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C50A7FA3744 for ; Thu, 27 Oct 2022 12:35:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235723AbiJ0Mf1 (ORCPT ); Thu, 27 Oct 2022 08:35:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235724AbiJ0MfW (ORCPT ); Thu, 27 Oct 2022 08:35:22 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E1AE3C8C2 for ; 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id p22-20020aa7d316000000b00461c1804cdasm942868edq.3.2022.10.27.05.35.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 05:35:07 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, konrad.dybcio@somainline.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bjorn Andersson , dmitry.baryshkov@linaro.org, Jonathan Marek Cc: Robert Foss Subject: [PATCH v1 5/5] clk: qcom: dispcc-sm8250: Disable link_div_clk_src for sm8150 Date: Thu, 27 Oct 2022 14:34:32 +0200 Message-Id: <20221027123432.1818530-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027123432.1818530-1-robert.foss@linaro.org> References: <20221027123432.1818530-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SM8150 does not have any of the link_div_clk_src clocks, so let's disable them for this SoC. Signed-off-by: Robert Foss --- drivers/clk/qcom/dispcc-sm8250.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index d2aaa44ed3d4..f6f719616f63 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1289,6 +1289,10 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; + + disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL; + disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL; + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL; } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { static struct clk_rcg2 * const rcgs[] = { &disp_cc_mdss_byte0_clk_src,