From patchwork Thu Oct 27 19:20:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 13022610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB47BFA3746 for ; Thu, 27 Oct 2022 19:20:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236438AbiJ0TUh (ORCPT ); Thu, 27 Oct 2022 15:20:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236443AbiJ0TUf (ORCPT ); Thu, 27 Oct 2022 15:20:35 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D3FA61752; Thu, 27 Oct 2022 12:20:34 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id fy4so7490398ejc.5; Thu, 27 Oct 2022 12:20:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EjDda3Lusp/oeaEDqD4vTznnGneLFmIyRWb+1tSU3S0=; b=TM+ybklDQvKacnw4jxjk+JrGqUjq68rPK56yGOE/x7mpjeO8OgUiNm1ShuZc1CFayq XUqb44iDsCqMmRs9yTPaefezGiyhTkxFiTMWERhqIiTH6B8WGplndMa+SCQvq1pbzSt0 kScXPe1tfiuA+enAKNrHz2Yc6pzVpliyTrPS/xpr9/UxREgM1Hn9O91CE0v0WYzZJvB2 vWcloMDGT/9PRuz+0SytwfWHVIRLFCXBEKJw9rKijD2ypoplkaZbsgE1OkAAdmQOm6EP tYlYpAOLA0HK4a+SdvJl4Q3dRdV+64Sgir0S8Bs9y1CqTfuCrmIrA24eBJlX7l/p7u61 Yv2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EjDda3Lusp/oeaEDqD4vTznnGneLFmIyRWb+1tSU3S0=; b=adxJ6z1QSq45Ml+pnT6Zvd2GUZpsfYd7tfXmITeBmk9KfPFebcWsUs+ABwOmc7kZ/X VZ25mjVMp4V+1f4Yh5dgGx66KTIM/fggGivLP+qPahQoQfRAvbtTPZRuf+VuujXC1n5w zDKhHkZ1P419CM+RJn+2op1PyhlFmxZTvXiXCpYfzPiovJCUO3a+GCyf9v0sBXZD8h6B hLj57fJE6CrXPXeq3Ww45a+zyEbmb+OBweUGDoGnXbKqX3rR9YxbGAcU7WAASqgnE+YO LPQw0IjonnAd71ZCK16QORUPg+VxQ+vT4cA0NJiqXxi2lsQ1IHien3BHxiGjr2YOvXwt XWog== X-Gm-Message-State: ACrzQf3AsrR//AYedG1PgPZ177CgDzwZoRNqSF4i38od8CkWarbZzGa6 83tNfy391J4wafKXc+HS5SQ= X-Google-Smtp-Source: AMsMyM58IPDGR1FEjDiX+/eXGN8nqgADvMkqUZZGXNjNnAr5x5wxmxfWiKNf6+H6BXZpBj7Y9V82aA== X-Received: by 2002:a17:907:2723:b0:7ad:4a55:512a with SMTP id d3-20020a170907272300b007ad4a55512amr10373701ejl.608.1666898433081; Thu, 27 Oct 2022 12:20:33 -0700 (PDT) Received: from hp-power-15.localdomain (mm-238-32-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.32.238]) by smtp.gmail.com with ESMTPSA id w18-20020a1709067c9200b007acc5a42e77sm1187006ejo.88.2022.10.27.12.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 12:20:32 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v6 1/3] dt-bindings: ingenic: Add support for the JZ4755 CGU Date: Thu, 27 Oct 2022 22:20:21 +0300 Message-Id: <20221027192024.484320-2-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221027192024.484320-1-lis8215@gmail.com> References: <20221027192024.484320-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add documentation for the clock generation unit (CGU) of the JZ4755 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Siarhei Volkau --- Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml index aa1df03ef..df256ebcd 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml @@ -22,6 +22,7 @@ select: enum: - ingenic,jz4740-cgu - ingenic,jz4725b-cgu + - ingenic,jz4755-cgu - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu @@ -51,6 +52,7 @@ properties: - enum: - ingenic,jz4740-cgu - ingenic,jz4725b-cgu + - ingenic,jz4755-cgu - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu From patchwork Thu Oct 27 19:20:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 13022611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CB2AFA3749 for ; Thu, 27 Oct 2022 19:20:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236545AbiJ0TUj (ORCPT ); Thu, 27 Oct 2022 15:20:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236527AbiJ0TUh (ORCPT ); Thu, 27 Oct 2022 15:20:37 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6452E5F7E8; Thu, 27 Oct 2022 12:20:36 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id b2so7504764eja.6; Thu, 27 Oct 2022 12:20:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wICd/6PuTpid08ZKJYuwFfQs4b4ZSUfrEfLUDuMq7r4=; b=c9Hpq5DN/DOwWiYXNjpgOAuJYKWCRuxzwS0BoRFvxbN8WY1BfVYHo4+k/o9DqgeClR w2FQp0nUjPlkWNnuXir78CF5AwG2h289wcBXQxcX55GfR3iEozi+tH8iBy96ywBBbdoo /JKz73N7ZjEhZZDVAqgH9VtBWuud4UjtIdOiwfKdCeNaS/o9l68q1wdPrJacA2NXBZPH q8v8UaR6qrAna8OckPwSvJY1TrQPqA3mY++jwPz9wI91Cm64fk/C1C6h8gPhH7arAmGg owcHddVsQUpRZa9p8SZ45x+FGQjAiEPWjwkRHdEq1WHVw0MmBEUxT86ZDbfPWnj54+wl JseQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wICd/6PuTpid08ZKJYuwFfQs4b4ZSUfrEfLUDuMq7r4=; b=xQpwjQeUmkFWoFgrA/J0GakwnugL1su4muUNXPFT9wgABksnwXdDMPRomhVsSazs9e e8HP8jjHHgJBIiCvZTlkjq1h56ZG/aRvgtlQ1IMlsU+T80RoVuHvPsl0ka4jWMHnuRPh j29GGOM6+Usyi3L2adGpSgT2jH8iXUYVBgftMhBondLXXpL5yKMlhxa4cgenjFLdV6A+ EcL2AJfQyZQH4PsQRVwIN6g5X9aKCouSw1CmPot+oN8dS0q5jsdJRAL7LMfDYAy/BA44 9gcPMz+Mj/JFZbuKEpR8eaIWi4Lqs+J36PBSxUoEpH++tNqtbkLRgU5MIZWnJQd3Frt/ Xr5g== X-Gm-Message-State: ACrzQf2P/hvvFvR4UMVsuNE3IrHZGHORssKuRMKQlyIxxpADQXIY5X5M YF04Nil0jP4kPtzU+wsczBU= X-Google-Smtp-Source: AMsMyM5gPDYck9Ry/GutIvil2hNm2f+io98EZmS1cwr63V0+8lZwyfzhDhpwv77EfspXVWz+R5CSqg== X-Received: by 2002:a17:907:b16:b0:7ad:855b:c08c with SMTP id h22-20020a1709070b1600b007ad855bc08cmr6979494ejl.667.1666898435003; Thu, 27 Oct 2022 12:20:35 -0700 (PDT) Received: from hp-power-15.localdomain (mm-238-32-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.32.238]) by smtp.gmail.com with ESMTPSA id w18-20020a1709067c9200b007acc5a42e77sm1187006ejo.88.2022.10.27.12.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 12:20:34 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v6 2/3] dt-bindings: clock: Add Ingenic JZ4755 CGU header Date: Thu, 27 Oct 2022 22:20:22 +0300 Message-Id: <20221027192024.484320-3-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221027192024.484320-1-lis8215@gmail.com> References: <20221027192024.484320-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This will be used from the devicetree bindings to specify the clocks that should be obtained from the jz4755-cgu driver. Acked-by: Krzysztof Kozlowski Signed-off-by: Siarhei Volkau --- .../dt-bindings/clock/ingenic,jz4755-cgu.h | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 include/dt-bindings/clock/ingenic,jz4755-cgu.h diff --git a/include/dt-bindings/clock/ingenic,jz4755-cgu.h b/include/dt-bindings/clock/ingenic,jz4755-cgu.h new file mode 100644 index 000000000..10098494e --- /dev/null +++ b/include/dt-bindings/clock/ingenic,jz4755-cgu.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides clock numbers for the ingenic,jz4755-cgu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ + +#define JZ4755_CLK_EXT 0 +#define JZ4755_CLK_OSC32K 1 +#define JZ4755_CLK_PLL 2 +#define JZ4755_CLK_PLL_HALF 3 +#define JZ4755_CLK_EXT_HALF 4 +#define JZ4755_CLK_CCLK 5 +#define JZ4755_CLK_H0CLK 6 +#define JZ4755_CLK_PCLK 7 +#define JZ4755_CLK_MCLK 8 +#define JZ4755_CLK_H1CLK 9 +#define JZ4755_CLK_UDC 10 +#define JZ4755_CLK_LCD 11 +#define JZ4755_CLK_UART0 12 +#define JZ4755_CLK_UART1 13 +#define JZ4755_CLK_UART2 14 +#define JZ4755_CLK_DMA 15 +#define JZ4755_CLK_MMC 16 +#define JZ4755_CLK_MMC0 17 +#define JZ4755_CLK_MMC1 18 +#define JZ4755_CLK_EXT512 19 +#define JZ4755_CLK_RTC 20 +#define JZ4755_CLK_UDC_PHY 21 +#define JZ4755_CLK_I2S 22 +#define JZ4755_CLK_SPI 23 +#define JZ4755_CLK_AIC 24 +#define JZ4755_CLK_ADC 25 +#define JZ4755_CLK_TCU 26 +#define JZ4755_CLK_BCH 27 +#define JZ4755_CLK_I2C 28 +#define JZ4755_CLK_TVE 29 +#define JZ4755_CLK_CIM 30 +#define JZ4755_CLK_AUX_CPU 31 +#define JZ4755_CLK_AHB1 32 +#define JZ4755_CLK_IDCT 33 +#define JZ4755_CLK_DB 34 +#define JZ4755_CLK_ME 35 +#define JZ4755_CLK_MC 36 +#define JZ4755_CLK_TSSI 37 +#define JZ4755_CLK_IPU 38 + +#endif /* __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ */ From patchwork Thu Oct 27 19:20:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 13022612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90219FA3742 for ; Thu, 27 Oct 2022 19:20:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236536AbiJ0TUw (ORCPT ); Thu, 27 Oct 2022 15:20:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236557AbiJ0TUj (ORCPT ); Thu, 27 Oct 2022 15:20:39 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6526B635C8; Thu, 27 Oct 2022 12:20:38 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id y14so7475730ejd.9; Thu, 27 Oct 2022 12:20:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NZZkI/kASXBUAcQgkP50+OVmHva+6OSmVw+aQO/dR9s=; b=HOsxt6jOJsDey1dTjg10dLsA4heOgwyRDHEdIR2S9E/tVVEcBuPoMnT/IjR6cQNsZy Vn92CirdwAMfOECP1qdkh4fCffs9mQ+OLeJMROJyZfMpMqDVoznfGPX2lbqsiVCMomQc du+g9XBl5f4G3XW51WAArbTQfaRk6KRjA1ubggcY3mspCXhBY1QXndEPRc5DJjgAueiF W+bIz+vs8l1T/Mtg6EK0jsxpTuKAgq4RkbRuV3+ymY18TDPgW0ETFsXNStDBEUY/vf8r 8WqMU0H2YMc5usLffLABZOwdiFGnspF92hlItS42a05YLRr42b6aLn+ZgsmiLLKyOR2j W7pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NZZkI/kASXBUAcQgkP50+OVmHva+6OSmVw+aQO/dR9s=; b=2V9fPzuRVfS2ixgwy/Po6HGmC7/Cf3XNnlEI9WyJ5spt1HQYPmc7PTt1UPmCcss4c1 IGQgfPgEoy8LqAhScuuzKUpfWEjdMkl4d2qoyYHxrsGAsur/nxA09q7Ui8pmKFgQ6jzA rZhSHrccDiXxiACrnniSrD6L3t1wXdRf+rUe+G+cxJqYMA9Pf/u2cR3v3EBQw/pHvdJ5 ba+IVmbeDAmjqSBcvq9dzTTGWoxEftLKWdGDPoS/PnB/dfiehjDnd7mbAxH6ZHMNpqhU 7v0z5exfGL+hC93c+KW82qvs+0C3QaFpxKaS3dVM5pssmg/U09XUSUAqyzWI51sgDGMU AsxQ== X-Gm-Message-State: ACrzQf0Bt70cXGnBevmMDiQxGtWDrkRxYvozTptJL3jaxtpR2lionCAk A+v95i1yNe78uJbwqeGrFD4= X-Google-Smtp-Source: AMsMyM64haKEp31j6KuN6/a4culwFjPkB2WLyybbvo+Y+8mQDLmNWTs9+T+Ar6iIE4DtE0j3C/PCNw== X-Received: by 2002:a17:906:7621:b0:750:c4a3:8fcd with SMTP id c1-20020a170906762100b00750c4a38fcdmr45429722ejn.180.1666898436937; Thu, 27 Oct 2022 12:20:36 -0700 (PDT) Received: from hp-power-15.localdomain (mm-238-32-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.32.238]) by smtp.gmail.com with ESMTPSA id w18-20020a1709067c9200b007acc5a42e77sm1187006ejo.88.2022.10.27.12.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 12:20:36 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Paul Cercueil , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v6 3/3] clk: Add Ingenic JZ4755 CGU driver Date: Thu, 27 Oct 2022 22:20:23 +0300 Message-Id: <20221027192024.484320-4-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221027192024.484320-1-lis8215@gmail.com> References: <20221027192024.484320-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add support for the clocks provided by the CGU in the Ingenic JZ4755 SoC. Signed-off-by: Siarhei Volkau Reviewed-by: Paul Cercueil --- drivers/clk/ingenic/Kconfig | 10 + drivers/clk/ingenic/Makefile | 1 + drivers/clk/ingenic/jz4755-cgu.c | 346 +++++++++++++++++++++++++++++++ 3 files changed, 357 insertions(+) create mode 100644 drivers/clk/ingenic/jz4755-cgu.c diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig index 898f1bc47..f80ac4f29 100644 --- a/drivers/clk/ingenic/Kconfig +++ b/drivers/clk/ingenic/Kconfig @@ -15,6 +15,16 @@ config INGENIC_CGU_JZ4740 If building for a JZ4740 SoC, you want to say Y here. +config INGENIC_CGU_JZ4755 + bool "Ingenic JZ4755 CGU driver" + default MACH_JZ4755 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic JZ4755 + and compatible SoCs. + + If building for a JZ4755 SoC, you want to say Y here. + config INGENIC_CGU_JZ4725B bool "Ingenic JZ4725B CGU driver" default MACH_JZ4725B diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index 9edfaf461..81d8e23c2 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o +obj-$(CONFIG_INGENIC_CGU_JZ4755) += jz4755-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o diff --git a/drivers/clk/ingenic/jz4755-cgu.c b/drivers/clk/ingenic/jz4755-cgu.c new file mode 100644 index 000000000..d2eb3ae0c --- /dev/null +++ b/drivers/clk/ingenic/jz4755-cgu.c @@ -0,0 +1,346 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Ingenic JZ4755 SoC CGU driver + * Heavily based on JZ4725b CGU driver + * + * Copyright (C) 2022 Siarhei Volkau + * Author: Siarhei Volkau + */ + +#include +#include +#include + +#include + +#include "cgu.h" +#include "pm.h" + +/* CGU register offsets */ +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_LCR 0x04 +#define CGU_REG_CPPCR 0x10 +#define CGU_REG_CLKGR 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSCCDR 0x68 +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x7C + +/* bits within the LCR register */ +#define LCR_SLEEP BIT(0) + +static struct ingenic_cgu *cgu; + +static const s8 pll_od_encoding[4] = { + 0x0, 0x1, -1, 0x3, +}; + +static const u8 jz4755_cgu_cpccr_div_table[] = { + 1, 2, 3, 4, 6, 8, +}; + +static const u8 jz4755_cgu_pll_half_div_table[] = { + 2, 1, +}; + +static const struct ingenic_cgu_clk_info jz4755_cgu_clocks[] = { + + /* External clocks */ + + [JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT }, + [JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, + + [JZ4755_CLK_PLL] = { + "pll", CGU_CLK_PLL, + .parents = { JZ4755_CLK_EXT, }, + .pll = { + .reg = CGU_REG_CPPCR, + .rate_multiplier = 1, + .m_shift = 23, + .m_bits = 9, + .m_offset = 2, + .n_shift = 18, + .n_bits = 5, + .n_offset = 2, + .od_shift = 16, + .od_bits = 2, + .od_max = 4, + .od_encoding = pll_od_encoding, + .stable_bit = 10, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 9, + .enable_bit = 8, + }, + }, + + /* Muxes & dividers */ + + [JZ4755_CLK_PLL_HALF] = { + "pll half", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, + jz4755_cgu_pll_half_div_table, + }, + }, + + [JZ4755_CLK_EXT_HALF] = { + "ext half", CGU_CLK_DIV, + .parents = { JZ4755_CLK_EXT, }, + .div = { + CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0, + NULL, + }, + }, + + [JZ4755_CLK_CCLK] = { + "cclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_H0CLK] = { + "hclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_PCLK] = { + "pclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_MCLK] = { + "mclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_H1CLK] = { + "h1clk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, }, + .div = { + CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_UDC] = { + "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, }, + .mux = { CGU_REG_CPCCR, 29, 1 }, + .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 10 }, + }, + + [JZ4755_CLK_LCD] = { + "lcd", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, }, + .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 9 }, + }, + + [JZ4755_CLK_MMC] = { + "mmc", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL_HALF, }, + .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, + }, + + [JZ4755_CLK_I2S] = { + "i2s", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, }, + .mux = { CGU_REG_CPCCR, 31, 1 }, + .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, + }, + + [JZ4755_CLK_SPI] = { + "spi", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, }, + .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 4 }, + }, + + [JZ4755_CLK_TVE] = { + "tve", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { JZ4755_CLK_LCD, JZ4755_CLK_EXT, }, + .mux = { CGU_REG_LPCDR, 31, 1 }, + .gate = { CGU_REG_CLKGR, 18 }, + }, + + [JZ4755_CLK_RTC] = { + "rtc", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT512, JZ4755_CLK_OSC32K, }, + .mux = { CGU_REG_OPCR, 2, 1}, + .gate = { CGU_REG_CLKGR, 2 }, + }, + + [JZ4755_CLK_CIM] = { + "cim", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, }, + .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 8 }, + }, + + /* Gate-only clocks */ + + [JZ4755_CLK_UART0] = { + "uart0", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 0 }, + }, + + [JZ4755_CLK_UART1] = { + "uart1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 14 }, + }, + + [JZ4755_CLK_UART2] = { + "uart2", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 15 }, + }, + + [JZ4755_CLK_ADC] = { + "adc", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 7 }, + }, + + [JZ4755_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 5 }, + }, + + [JZ4755_CLK_I2C] = { + "i2c", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_CLKGR, 3 }, + }, + + [JZ4755_CLK_BCH] = { + "bch", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + + [JZ4755_CLK_TCU] = { + "tcu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT, }, + .gate = { CGU_REG_CLKGR, 1 }, + }, + + [JZ4755_CLK_DMA] = { + "dma", CGU_CLK_GATE, + .parents = { JZ4755_CLK_PCLK, }, + .gate = { CGU_REG_CLKGR, 12 }, + }, + + [JZ4755_CLK_MMC0] = { + "mmc0", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MMC, }, + .gate = { CGU_REG_CLKGR, 6 }, + }, + + [JZ4755_CLK_MMC1] = { + "mmc1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MMC, }, + .gate = { CGU_REG_CLKGR, 16 }, + }, + + [JZ4755_CLK_AUX_CPU] = { + "aux_cpu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 24 }, + }, + + [JZ4755_CLK_AHB1] = { + "ahb1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 23 }, + }, + + [JZ4755_CLK_IDCT] = { + "idct", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 22 }, + }, + + [JZ4755_CLK_DB] = { + "db", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 21 }, + }, + + [JZ4755_CLK_ME] = { + "me", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 20 }, + }, + + [JZ4755_CLK_MC] = { + "mc", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, }, + .gate = { CGU_REG_CLKGR, 19 }, + }, + + [JZ4755_CLK_TSSI] = { + "tssi", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF/* not sure */, }, + .gate = { CGU_REG_CLKGR, 17 }, + }, + + [JZ4755_CLK_IPU] = { + "ipu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF/* not sure */, }, + .gate = { CGU_REG_CLKGR, 13 }, + }, + + [JZ4755_CLK_EXT512] = { + "ext/512", CGU_CLK_FIXDIV, + .parents = { JZ4755_CLK_EXT, }, + + .fixdiv = { 512 }, + }, + + [JZ4755_CLK_UDC_PHY] = { + "udc_phy", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, }, + .gate = { CGU_REG_OPCR, 6, true }, + }, +}; + +static void __init jz4755_cgu_init(struct device_node *np) +{ + int retval; + + cgu = ingenic_cgu_new(jz4755_cgu_clocks, + ARRAY_SIZE(jz4755_cgu_clocks), np); + if (!cgu) { + pr_err("%s: failed to initialise CGU\n", __func__); + return; + } + + retval = ingenic_cgu_register_clocks(cgu); + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + + ingenic_cgu_register_syscore_ops(cgu); +} +CLK_OF_DECLARE_DRIVER(jz4755_cgu, "ingenic,jz4755-cgu", jz4755_cgu_init);