From patchwork Mon Oct 31 12:33:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5EE2AFA3740 for ; Mon, 31 Oct 2022 12:35:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opTzu-0003kb-8e; Mon, 31 Oct 2022 08:34:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTz0-000313-Jp for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:33:46 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTyx-00049O-Br for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:33:37 -0400 Received: by mail-pl1-x632.google.com with SMTP id d24so10613799pls.4 for ; Mon, 31 Oct 2022 05:33:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nr0YW9yWzkpPk77jiuUxzZwbjjkwdTQ1TcUuJ89L3jM=; b=5sW7IDud1o1MLCdzFhhAEoviI4jujWiGEtqNBKU1SY2A0ZCuyx8kOfZDmVNZYsPHA6 ip4OBQnYUhYtNPV1A1EyE5aRgi9HeXUeGfa+7f4M1ZR7AX85tu8DcD9qNqR+pEJvqkaU 6LJhdurILctxIfkmztQB52ysjEpj0YU0KB/78sPimt0Cewyw/Pey0AI53jO73xzdeJDK noHT6aqSBM2kwHysEIQlIp3A9F5pijjJOY8YepKBnInF7YyOEhogMIEOsdVPPtGyZqdl NUK5PkcQ7aI3FYD+1X2awM3BOj/lb5q8V27I6N9RwXup/WuTt+aYGYpwDJ4KAoK2ntUr Cnrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nr0YW9yWzkpPk77jiuUxzZwbjjkwdTQ1TcUuJ89L3jM=; b=eqJuduySgWxML5GxfitC4/hkGyexlKdo8pRPhTTYgdPn2vZO9whEPVco7yPv6hS0qc z2ZHcLrSCmm+53D9Yoaq7GQ1Cqx52PEvh+IL6yUV+vNOFmrtJgycjwclvCNtXrVEmY1W meUBokD6JRog3uW0/kU0m8TJptLGuqh+bMp4/DeAORleq8ZxbZHXQ9pYJWp8lyHMJR/5 qkKxjPaut7gqZiOXOTxR+0Fl7iSHOZ0s/0POUogekgJew1f4brA6DjOEomlKt5m3wsUC ksQcbbhZsgt0VNY+yVWPcuh8tvOB9rc6Ch/DJ0s9CU894YPyRv+CVtr2ljMhxKPSPkRG 7lCQ== X-Gm-Message-State: ACrzQf2I/J3N3ACsuagAc+OV+6q5aF4Iu4aKX5wKP4H1O664ab/fGbV+ 6hZAcSORTl0kBV9lCJ06ukugjHntbWwDvbP6 X-Google-Smtp-Source: AMsMyM42Vkgpe0miKhu7+oszB6wdJr+B9dITmRbEtAkS3LntApdGcWgPUFa/uQu8PxSpF3FWoyYXAg== X-Received: by 2002:a17:902:b10d:b0:187:29fe:bda0 with SMTP id q13-20020a170902b10d00b0018729febda0mr2209432plr.16.1667219613728; Mon, 31 Oct 2022 05:33:33 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:33:33 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 01/17] hw/vfio/pci: Ensure MSI and MSI-X do not overlap Date: Mon, 31 Oct 2022 21:33:03 +0900 Message-Id: <20221031123319.21532-2-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::632; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org pci_add_capability() checks whether capabilities overlap, and notifies its caller so that it can properly handle the case. However, in the most cases, the capabilities actually never overlap, and the interface incurred extra error handling code, which is often incorrect or suboptimal. For such cases, pci_add_capability() can simply abort the execution if the capabilities actually overlap since it should be a programming error. This change handles the other cases: hw/vfio/pci depends on the check to decide MSI and MSI-X capabilities overlap with another. As they are quite an exceptional and hw/vfio/pci knows much about PCI capabilities, adding code specific to the cases to hw/vfio/pci still results in less code than having error handling code everywhere in total. Signed-off-by: Akihiko Odaki --- hw/vfio/pci.c | 61 ++++++++++++++++++++++++++++++++++++++++++--------- hw/vfio/pci.h | 3 +++ 2 files changed, 54 insertions(+), 10 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 939dcc3d4a..c7e3ef95a7 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1278,23 +1278,42 @@ static void vfio_disable_interrupts(VFIOPCIDevice *vdev) } } -static int vfio_msi_setup(VFIOPCIDevice *vdev, int pos, Error **errp) +static void vfio_msi_early_setup(VFIOPCIDevice *vdev, Error **errp) { uint16_t ctrl; - bool msi_64bit, msi_maskbit; - int ret, entries; - Error *err = NULL; + uint8_t pos; + + pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSI); + if (!pos) { + return; + } if (pread(vdev->vbasedev.fd, &ctrl, sizeof(ctrl), vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) { error_setg_errno(errp, errno, "failed reading MSI PCI_CAP_FLAGS"); - return -errno; + return; } - ctrl = le16_to_cpu(ctrl); + vdev->msi_pos = pos; + vdev->msi_ctrl = le16_to_cpu(ctrl); - msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT); - msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT); - entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1); + vdev->msi_cap_size = 0xa; + if ((vdev->msi_ctrl & PCI_MSI_FLAGS_MASKBIT)) { + vdev->msi_cap_size += 0xa; + } + if ((vdev->msi_ctrl & PCI_MSI_FLAGS_64BIT)) { + vdev->msi_cap_size += 0x4; + } +} + +static int vfio_msi_setup(VFIOPCIDevice *vdev, int pos, Error **errp) +{ + bool msi_64bit, msi_maskbit; + int ret, entries; + Error *err = NULL; + + msi_64bit = !!(vdev->msi_ctrl & PCI_MSI_FLAGS_64BIT); + msi_maskbit = !!(vdev->msi_ctrl & PCI_MSI_FLAGS_MASKBIT); + entries = 1 << ((vdev->msi_ctrl & PCI_MSI_FLAGS_QMASK) >> 1); trace_vfio_msi_setup(vdev->vbasedev.name, pos); @@ -1306,7 +1325,6 @@ static int vfio_msi_setup(VFIOPCIDevice *vdev, int pos, Error **errp) error_propagate_prepend(errp, err, "msi_init failed: "); return ret; } - vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0); return 0; } @@ -1524,6 +1542,7 @@ static void vfio_msix_early_setup(VFIOPCIDevice *vdev, Error **errp) pba = le32_to_cpu(pba); msix = g_malloc0(sizeof(*msix)); + msix->pos = pos; msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK; msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK; msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK; @@ -2025,6 +2044,22 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp) } } + if (cap_id != PCI_CAP_ID_MSI && + range_covers_byte(vdev->msi_pos, vdev->msi_cap_size, pos)) { + error_setg(errp, + "A capability overlaps with MSI (%" PRIu8 " in [%" PRIu8 ", %" PRIu8 "))", + pos, vdev->msi_pos, vdev->msi_pos + vdev->msi_cap_size); + return -EINVAL; + } + + if (cap_id != PCI_CAP_ID_MSIX && vdev->msix && + range_covers_byte(vdev->msix->pos, MSIX_CAP_LENGTH, pos)) { + error_setg(errp, + "A capability overlaps with MSI-X (%" PRIu8 " in [%" PRIu8 ", %" PRIu8 "))", + pos, vdev->msix->pos, vdev->msix->pos + MSIX_CAP_LENGTH); + return -EINVAL; + } + /* Scale down size, esp in case virt caps were added above */ size = MIN(size, vfio_std_cap_max_size(pdev, pos)); @@ -3037,6 +3072,12 @@ static void vfio_realize(PCIDevice *pdev, Error **errp) vfio_bars_prepare(vdev); + vfio_msi_early_setup(vdev, &err); + if (err) { + error_propagate(errp, err); + goto error; + } + vfio_msix_early_setup(vdev, &err); if (err) { error_propagate(errp, err); diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index 7c236a52f4..9ae0278058 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -107,6 +107,7 @@ enum { /* Cache of MSI-X setup */ typedef struct VFIOMSIXInfo { + uint8_t pos; uint8_t table_bar; uint8_t pba_bar; uint16_t entries; @@ -128,6 +129,8 @@ struct VFIOPCIDevice { unsigned int rom_size; off_t rom_offset; /* Offset of ROM region within device fd */ void *rom; + uint8_t msi_pos; + uint16_t msi_ctrl; int msi_cap_size; VFIOMSIVector *msi_vectors; VFIOMSIXInfo *msix; From patchwork Mon Oct 31 12:33:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8C7BFA3740 for ; Mon, 31 Oct 2022 12:34:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU07-0003t5-Pl; Mon, 31 Oct 2022 08:34:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzA-00033s-6B for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:33:50 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTz2-0004JJ-R3 for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:33:45 -0400 Received: by mail-pg1-x533.google.com with SMTP id q1so10548228pgl.11 for ; Mon, 31 Oct 2022 05:33:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RVbq2yaYdJoiH8651nfM6y1MMdPJwfTDDNgpcpWTQtU=; b=TqvCcYQdwxQnOH+f5Jnf35dTOjiAWR9ZHIWaZ2K8yO9K5FLM870HN1y7NZuo20+6TU VJpLZoIbES71DtaOsEVKUYLCml8kYODj9zNFN3OjPV8uXercAcFppZcw6z33xcIJxTyU 7De0A/fA09Oz+kXmVyzju2tZMIIUtvu62CBBi51i1uHgJmEa0bugvEe409dt47yqCPwx OrKJKwp6fNPSEMSDK30AVEVxDBr2CwHRJxAswAfrjioUCVjdMqV3p4k4P1s9p+kcPZ/Z us1r82ckfgAmV2uJxX/IyJni1cp4SCqjyzZ3/VHEEARXpEXsibLo6m56TGkhbnKXISIz lyWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RVbq2yaYdJoiH8651nfM6y1MMdPJwfTDDNgpcpWTQtU=; b=ARXeWILgRm2VzywWCGZLFiZpOFMLWtvLz/wJd65RdCawA4I/ldvOi18sL4wG2buVm3 Y5zkygEAwx/s3NYzeYiLwwVYIzzR1rAp9SGzWffBK1QPUqmZDoBuznjp5D8tsoJnkwgM /YsP2i+QIik2l9hoGqw4TP8ODCUExZs5LZdswNA1iOWDOr4QPvCHFlhMm8PYBCl52Z/Q XUFlaba44hrSLHj0K+MS2wau4Gve5csGOC33O3m1x9MvK6gs29IRyNWPyomqIfilJ1o4 SYGmDwESr2V+IzWibuXLL+y82qnPCw7HHaU3Lmcx9hQkaUsymaqMuthGqMNoaawcq6BT yXnA== X-Gm-Message-State: ACrzQf1FM1cW4Yy1rqrM4jcZLfQaea75FNGdoiHKd71+gqjDJFwKtJcc cgfaR+secGKT6UCkGxjGCRic3GBXH0hLfOkC X-Google-Smtp-Source: AMsMyM6rl6PxU6g1thJbovWYQzihw6qwr5+kDlaP/CSrje/rSUl9P6QFkvywMlhHkL9lnzG5beYOHA== X-Received: by 2002:a62:582:0:b0:56c:8c13:247e with SMTP id 124-20020a620582000000b0056c8c13247emr14028286pff.43.1667219618812; Mon, 31 Oct 2022 05:33:38 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:33:38 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 02/17] pci: Allow to omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:04 +0900 Message-Id: <20221031123319.21532-3-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::533; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org pci_add_capability appears most PCI devices. Its error handling required lots of code, and led to inconsistent behaviors such as: - passing error_abort - passing error_fatal - asserting the returned value - propagating the error to the caller - skipping the rest of the function - just ignoring The code generating errors in pci_add_capability had a comment which says: > Verify that capabilities don't overlap. Note: device assignment > depends on this check to verify that the device is not broken. > Should never trigger for emulated devices, but it's helpful for > debugging these. Indeed vfio has some code that passes capability offsets and sizes from a physical device, but it explicitly pays attention so that the capabilities never overlap. Therefore, we can always assert that capabilities never overlap when pci_add_capability is called, resolving these inconsistencies. Such an implementation of pci_add_capability will not have errp parameter. However, there are so many callers of pci_add_capability that it does not make sense to amend all of them at once to match with the new signature. Instead, this change will allow callers of pci_add_capability to omit errp as the first step. Signed-off-by: Akihiko Odaki --- hw/pci/pci.c | 8 ++++---- include/hw/pci/pci.h | 13 ++++++++++--- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 2f450f6a72..8ee2171011 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2513,14 +2513,14 @@ static void pci_del_option_rom(PCIDevice *pdev) } /* - * On success, pci_add_capability() returns a positive value + * On success, pci_add_capability_legacy() returns a positive value * that the offset of the pci capability. * On failure, it sets an error and returns a negative error * code. */ -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp) +int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, + Error **errp) { uint8_t *config; int i, overlapping_cap; diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index b54b6ef88f..51fd106f16 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -2,6 +2,7 @@ #define QEMU_PCI_H #include "exec/memory.h" +#include "qapi/error.h" #include "sysemu/dma.h" /* PCI includes legacy ISA access. */ @@ -390,9 +391,15 @@ void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, void pci_unregister_vga(PCIDevice *pci_dev); pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp); +int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, + Error **errp); + +#define PCI_ADD_CAPABILITY_VA(pdev, cap_id, offset, size, errp, ...) \ + pci_add_capability_legacy(pdev, cap_id, offset, size, errp) + +#define pci_add_capability(...) \ + PCI_ADD_CAPABILITY_VA(__VA_ARGS__, &error_abort) void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size); From patchwork Mon Oct 31 12:33:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7226BFA3740 for ; Mon, 31 Oct 2022 12:35:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0F-0004P1-DR; Mon, 31 Oct 2022 08:34:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzE-000379-RK for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:33:54 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTz9-0004Ki-5i for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:33:49 -0400 Received: by mail-pj1-x1029.google.com with SMTP id h14so10256811pjv.4 for ; Mon, 31 Oct 2022 05:33:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OuJGfEqiahgje0+ZI8xfhUI2kNLbWBqS9djVvTbLrXo=; b=Wj/rTDGMtFHwGKUmYzJNoKJnEUingJqmDmzGb53X63j/lgqmAFJ7krquVT1b3UFU3s BvDQ1rjZf1PO0ycR2PVKUTdEGR8XNkX0v5NacmG8GaHv6+tGMA9NRwx2QxyGP+mPvUlW aCVpinyohMEw2mYTT6qE7W6PyKnVGzP3mOVKYOkMWO3vJV9Za2Q8Ob0uNs3Mp6FT1+zG xcoanWWV4JbbouZZG5+4zHobygDWFkkw+BYUpB8EaAUKL8ZU7kUZwLsVU77+Tpo/VpDV 2Emn+h3hgN5y4ZsCzAsETp9UPzVVYguFbHxR9moXP130jQf71pjOcsDZrCcwZLN6kb1A GXGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OuJGfEqiahgje0+ZI8xfhUI2kNLbWBqS9djVvTbLrXo=; b=WMrzcffxi7PYg8iezIcTQwMdRJJ0SL6watNJPm2yyWpwYtqJ/D9zykJ+B/o9o3X2RA oxNOPxXw3wvhUaHMMlAeULyiSl/oHEpzE4f7G3Cf7LRrYoX7oIV/UoULS5dGuhG0JdAp Q5x5/UjuJO1KDVmRq4FknNn9A124r9JWDTr0Ys1QosECyGS/plyR8x0VeAyjuAlbsDGG gj+SlYI4JNfBSFBPCbWzHKDWf2s2jA6WNB3JsaRrXU5hn1ht1lDygtO1aCFBbkFzLeqM 9yFJsFmyJKWWsZ168d+U+98C9tqsb+ZTsUsROxq95unu2Jg5iCtJgxHQdWpUYkmDjR92 1gFw== X-Gm-Message-State: ACrzQf3roZ2JoByC5ofMx/jRplh6s0p2C8Cg2/TGEqD6RvbDm8HDG1qB eWrYP7h3xHkEIiIEx8pDXmD7edssG5GD96Zh X-Google-Smtp-Source: AMsMyM5A4JvBH0l6eYCNn9vQZc36/oa5rbjBTVl0U1sG8wdhp7dNLtbwAOtEruL+5imVUXGtrJfl9w== X-Received: by 2002:a17:902:b218:b0:184:710c:8c52 with SMTP id t24-20020a170902b21800b00184710c8c52mr14149679plr.95.1667219623954; Mon, 31 Oct 2022 05:33:43 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:33:43 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 03/17] hw/i386/amd_iommu: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:05 +0900 Message-Id: <20221031123319.21532-4-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::1029; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/i386/amd_iommu.c | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 725f69095b..8a88cbea0a 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1539,7 +1539,6 @@ static void amdvi_sysbus_reset(DeviceState *dev) static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) { - int ret = 0; AMDVIState *s = AMD_IOMMU_DEVICE(dev); MachineState *ms = MACHINE(qdev_get_machine()); PCMachineState *pcms = PC_MACHINE(ms); @@ -1553,23 +1552,11 @@ static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) if (!qdev_realize(DEVICE(&s->pci), &bus->qbus, errp)) { return; } - ret = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, - AMDVI_CAPAB_SIZE, errp); - if (ret < 0) { - return; - } - s->capab_offset = ret; + s->capab_offset = pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, + AMDVI_CAPAB_SIZE); - ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, - AMDVI_CAPAB_REG_SIZE, errp); - if (ret < 0) { - return; - } - ret = pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, - AMDVI_CAPAB_REG_SIZE, errp); - if (ret < 0) { - return; - } + pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE); + pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, AMDVI_CAPAB_REG_SIZE); /* Pseudo address space under root PCI bus. */ x86ms->ioapic_as = amdvi_host_dma_iommu(bus, s, AMDVI_IOAPIC_SB_DEVID); From patchwork Mon Oct 31 12:33:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3402FA3742 for ; Mon, 31 Oct 2022 12:38:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0I-0004ik-35; Mon, 31 Oct 2022 08:34:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzL-0003F4-Dp for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:33:59 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTzG-0004LN-ED for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:33:56 -0400 Received: by mail-pl1-x62e.google.com with SMTP id c24so10595523pls.9 for ; Mon, 31 Oct 2022 05:33:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jJjPRo2jnYNBTT+kAOkS5uMVCK0dMEO9iW4TvwZKw3A=; b=gD0CUWN4xTz0cfQginNv+aIFbilCQNOJiya9FtDe+LgFS7c6pVTroUY1/N13zKTBVi 7g9ICIMoq/5taXJuiCfh0ocY+zZo60PfCJMkd2ByoUELtlhYtTDuqN/O1rzW9N/L6Abi L0JiLYhaD437X5BaoaVOyIg2QmujrTTXzt8NEryS1tvUlK55l6ASCXJ1qBzSC/U4YtML 71SqqNZJfJmMExOFWqxXWGVDeDqM325MBiAkgK/XWs7tQ7V/FK3/+hfdFSUNfOI+xZ/b mMxVq8+fBBltrc7d+cvaw3clmrTDOQBDX/Dq475r931M2Fnzle8mtMokGowzOQ7Ld2BC mW2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jJjPRo2jnYNBTT+kAOkS5uMVCK0dMEO9iW4TvwZKw3A=; b=kJJ4UtpAm/BjVDVt/UhmT9kV6G2/opQ8T6X51VNEK8rKO4jyc/1CLu5aW6TvWCZNDt gWXdz8ITB+au2rSBLblwwohJFqF+FY0t59tF97EKlKQ+mVTdR9bTwtjaRLYX0e+emHmp jLvy0pfb0ZP2+YW3ceYarnOBqTNvbBbzc6lFQmxy0AA678VPZB9f5+jp/RNwa9D6NPun ESxew2ztD+Saf1wqGerQYXmeRJIhqT7tc6mkkEEvjqvbfuH1qKkLPm6VuDLfw8elg4Pg RwHUa9jXLDcyzBFQyOUJMl7aXO/FoOyeLsa7r0y3pKtrx8oIwOkiczLHOW6Ou4PWkpSL PFTg== X-Gm-Message-State: ACrzQf19Vv1kU8e5qae2q/9414GCC5tE1xW8j3jg3+ELGRK4TIJz1FUd n+WXvkwXpb5bnqkHVkSLhUJBFVZaVOSeNcfQ X-Google-Smtp-Source: AMsMyM5vuSDEAqmV8vSAIj/G2odetIkezUD70tzrERdr+HndxapHP9/hFvs+TRdKQGyZpsEK3SjC7w== X-Received: by 2002:a17:902:da92:b0:187:25ae:16ad with SMTP id j18-20020a170902da9200b0018725ae16admr3504030plx.20.1667219629011; Mon, 31 Oct 2022 05:33:49 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:33:48 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 04/17] ahci: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:06 +0900 Message-Id: <20221031123319.21532-5-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::62e; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/ide/ich.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/ide/ich.c b/hw/ide/ich.c index 1007a51fcb..3b478b01f8 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -106,7 +106,7 @@ static void pci_ich9_ahci_init(Object *obj) static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) { struct AHCIPCIState *d; - int sata_cap_offset; + uint8_t sata_cap_offset; uint8_t *sata_cap; d = ICH9_AHCI(dev); int ret; @@ -130,11 +130,7 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp) &d->ahci.mem); sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA, - ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE, - errp); - if (sata_cap_offset < 0) { - return; - } + ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE); sata_cap = dev->config + sata_cap_offset; pci_set_word(sata_cap + SATA_CAP_REV, 0x10); From patchwork Mon Oct 31 12:33:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C942EFA3740 for ; Mon, 31 Oct 2022 12:38:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0P-0005AT-FF; Mon, 31 Oct 2022 08:35:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzb-0003NO-0H for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:23 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTzK-0004M2-3g for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:13 -0400 Received: by mail-pf1-x435.google.com with SMTP id f140so10579288pfa.1 for ; Mon, 31 Oct 2022 05:33:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LeDajy+wDOnHrF4VJbDnI9K6oGioqFYjvnSTZ44MAKY=; b=FDVNKTR5lEYj2TRDTQ3HBtwNnFuuGLb3nIMoYkMq5iTqFf8QTDMXvV230fgnXe6XkJ jYWYl+AYU4yD8w1JsLTuR9/x57kv8Gs1toi4p6QVy13ln63wyl2uEA1RDohNwJOrd6Ez kBQccJyFcae5GiU7IC+IDxFeoKbUYJD90E+3o59nteRnHVgmxMJOyB5QJf+gWAz0vrrj XdE8WFse+Izktx6U7gwyBkLx7CDdNeyHkqgmZy5aYRBjQLVrOWapXlRXzZCRSQ+zmoiq deFMwCeDnDNuTCuJ3XQiHwpAVqr0frNxTqS6GQoJ0KAtdo5WIHbnhmdp7nmXZUzxPVAp 1skw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LeDajy+wDOnHrF4VJbDnI9K6oGioqFYjvnSTZ44MAKY=; b=p6EkYvAnLNxcxOyXWiNiWCPK9zriZDogHM9QeKmg/M5naA4ajPPHIPY8rm+NU8zZXY fy9D2z1aUXVY/yqqD5HNu+zmO0N6xMgc/uimeOlCWcdrG5RD2vtL2ECO7a4xTisnpiml O9u3plU6weB1kRDIM0raIPxU9j9K20mG0L14+wH+yyqjLNDpHS2cRFEBrqaiTxP4TAHa enJDVAAVtmRbJffMrM6YmgpPF0gJUBmkCUAc0ocDOYIffVO9tVMLIbv7dBGQ9OYqd1W+ sgNeSP4U5D523h/5z/UhZDXJxxX5jSIhtgh1JMHpDkhfPjgs+ILVcOqNHIR+t8+CuVtO Pr7g== X-Gm-Message-State: ACrzQf2s3KXpD/LnX+suvT/rnf+b9TMfMwpJnPF7LE2EwWHyhp+VvOTf zL9nrLNcil8L6f18QEOMHfB71WSMDvL4CMWW X-Google-Smtp-Source: AMsMyM5yePmvJhhUmW0yDGous49gLcjEykD3Wu1X28OsYcLRmadPYuimW3jmq2JBehE2v0GK/MoWkA== X-Received: by 2002:a63:f214:0:b0:461:8862:331e with SMTP id v20-20020a63f214000000b004618862331emr12430709pgh.386.1667219634116; Mon, 31 Oct 2022 05:33:54 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:33:53 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 05/17] e1000e: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:07 +0900 Message-Id: <20221031123319.21532-6-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::435; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/net/e1000e.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index ac96f7665a..e433b8f9a5 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -377,17 +377,10 @@ e1000e_gen_dsn(uint8_t *mac) (uint64_t)(mac[0]) << 56; } -static int +static void e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) { - Error *local_err = NULL; - int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset, - PCI_PM_SIZEOF, &local_err); - - if (local_err) { - error_report_err(local_err); - return ret; - } + pci_add_capability(pdev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF); pci_set_word(pdev->config + offset + PCI_PM_PMC, PCI_PM_CAP_VER_1_1 | @@ -400,8 +393,6 @@ e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc) pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL, PCI_PM_CTRL_PME_STATUS); - - return ret; } static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address, @@ -480,10 +471,7 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp) trace_e1000e_msi_init_fail(ret); } - if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset, - PCI_PM_CAP_DSI) < 0) { - hw_error("Failed to initialize PM capability"); - } + e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset, PCI_PM_CAP_DSI); if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset, PCI_ERR_SIZEOF, NULL) < 0) { From patchwork Mon Oct 31 12:33:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6472DC38A02 for ; Mon, 31 Oct 2022 12:37:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0K-0004sd-3f; Mon, 31 Oct 2022 08:35:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzQ-0003Mz-AS for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:21 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTzO-0004NE-Nk for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:04 -0400 Received: by mail-pf1-x42b.google.com with SMTP id 17so6302204pfv.4 for ; Mon, 31 Oct 2022 05:34:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vn8QAsjO7gtbZVeE7QQx9COaGQRw61V/sT24VvnuPKo=; b=BikZutB21mbzsJSwEx8B/Ylzp5DWUwdu1CtS3tZ0Kp3H3CwDuZcl9eSt2peEzCSfKM oMYMKP5yePV53nrS7rvz6gTrue1KNHnXguv+O1sRMdEh+j1ZGELqs8CtDjP94+MFs9iu H1h4XeutaFj93oxmrCyCg5zrjOP2Z9nEumpc2AGEL3pj890zHw0nX1p/KZ/X9VfGE50K EGF5e4TgAiYbwCRBAGuNXVGkl1xVLWnhLAUb5FsGnfKNnlzat8CRKpHuUO5u0DyGgiBx ig5o7VhWz3ajCZJ6Hx13pdSzJySKip+KJjNBDhhriGiAQwKYeiKLbL3HIPL5jud3ZeWq GDWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vn8QAsjO7gtbZVeE7QQx9COaGQRw61V/sT24VvnuPKo=; b=xs3ZcRU/KdGzZVgkeq1s+lJTMPFpcgbr+XeoFlGzJFpkKrZauKs0nkHiu97NUQRIk9 RU1Cp4suwMrhuaD+jd+yX6Ren6C1Cv50WOC5sRH+FpfgbhyDvP7iJnJWYMvot6QUTEf9 3+xqNz7pknHwzZVGxXCG9cAcwrmK0DXrgy7l80vwMsB2843PFmplvR67UnZdTxMf2qlW mijatWpo+Sg4GcfYkWzGVWBetRErKDZSo4alpd0GoFIFDl+pU0HrwZudw8te44fWVuSL BTXbRqrdYIW1c8qnFAS3fkr76tZgPNps0RQxDROX6RjBtYaJ+H1Y6RJ7OyTnIhzd3+Ha TCWw== X-Gm-Message-State: ACrzQf2PJrMQ2HypLkyUg/TTB8i4kOpyQ8vwNfeWpubquXr2v4EYrQ2G xMPLtVPtLznQnJ/zo7XDkOPXYcQPty8EgQiH X-Google-Smtp-Source: AMsMyM6foI8WggQkdQEoDNvP1B79NcwTFUDFY5tSpVOWwGkjH0JDNt2Ve/d4MiE7pOXSXxuYvL67kg== X-Received: by 2002:aa7:9629:0:b0:56c:8c22:6d70 with SMTP id r9-20020aa79629000000b0056c8c226d70mr14267144pfg.8.1667219639192; Mon, 31 Oct 2022 05:33:59 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.33.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:33:58 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 06/17] eepro100: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:08 +0900 Message-Id: <20221031123319.21532-7-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::42b; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/net/eepro100.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 679f52f80f..bf2ecdded9 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -549,12 +549,7 @@ static void e100_pci_reset(EEPRO100State *s, Error **errp) if (info->power_management) { /* Power Management Capabilities */ int cfg_offset = 0xdc; - int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM, - cfg_offset, PCI_PM_SIZEOF, - errp); - if (r < 0) { - return; - } + pci_add_capability(&s->dev, PCI_CAP_ID_PM, cfg_offset, PCI_PM_SIZEOF); pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21); #if 0 /* TODO: replace dummy code for power management emulation. */ From patchwork Mon Oct 31 12:33:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 201A3FA3740 for ; Mon, 31 Oct 2022 12:36:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0l-0005lH-QP; Mon, 31 Oct 2022 08:35:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzn-0003Wh-Cd for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:29 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTzS-0004Oc-Q5 for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:26 -0400 Received: by mail-pf1-x432.google.com with SMTP id y13so10547214pfp.7 for ; Mon, 31 Oct 2022 05:34:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r10TkuBoyEwvau/bgUnLf5IBkvgqqBcYI2/YSx6NHxc=; b=YL4bwsZmnxpyPYCtY9tofpKF1/UMhKk2qNGaZNU0jwP2M/YFZDSB5g9+l9dU9w2RrU 8zenL6waVp7evsxkfyxYAO61bjM2ibikHKEjrp4nVlIJ/Qj7mWtqwbh26IBONMfY/f8G Jk/QywsRe6575yubshrU2qzOgJ7q35ifHQ4qWL4yRjWdkvEZTZDg9I7kjDcEpmzcHPDS E8VmZmqnIlXSRGYlwCtOdCoYIs7SlGnrTHqyZOhDw91vNfBgfnFT0qG6xbJa6uk+NM54 BD45TdUm3St24ChtyPtTPKYTDfIbtR7T1GSxAjq+eoYzzsNkroTk80dsAYetKL6WIIu4 3YBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r10TkuBoyEwvau/bgUnLf5IBkvgqqBcYI2/YSx6NHxc=; b=lJcp0mMK2YTGAxD9yn9QodhlLr+uJR7iTKX4XSlS7YWMx2wKWJ3iv6kALNS/7k/aBU 0ehxROjmmNjfDSJ0l++PI75okFJPJIntyUA/giPUgYpVjTB+tYkzlG2T/nZjsPfRETRO P7PHJZupzZUPmIdyLeCTCtNJOPO//1GICjF5pX5MBHnUY9sgv7jV78ghizIxaFzvX0eD vggjn3TZHrDFaRWXMP9mxuTXJQPkHuoBWQ45bxMHROTHCQpksfFtayEBMgxmgBOffwNA zsItG7rYL7tSSKQQ1xP89sP7m3L6mqr99M4WQ/uJIeh6517NRv5W+Z7kVI/fevbAx/bv E9UA== X-Gm-Message-State: ACrzQf3p4Ou9r4ufvwNf4udcdPkQHHIcBxNUH0QBIqWYAPaUpZxh7few W80lIO6d+q9VDf63lyqSglfsjcCJYZcF20yo X-Google-Smtp-Source: AMsMyM4SeDgSgKz9HH2bNIMdXd0ca00QgTUKBVXOM9H+rncdodiwuJHozJy8ig4tZ4G/40LPsJGFdg== X-Received: by 2002:a05:6a00:1d89:b0:56c:a2b:f1c2 with SMTP id z9-20020a056a001d8900b0056c0a2bf1c2mr14509734pfw.45.1667219644277; Mon, 31 Oct 2022 05:34:04 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:03 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 07/17] hw/nvme: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:09 +0900 Message-Id: <20221031123319.21532-8-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::432; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/nvme/ctrl.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 87aeba0564..ff4e2beea6 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -7325,17 +7325,9 @@ static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset) PCI_BASE_ADDRESS_MEM_TYPE_64, bar_size); } -static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) +static void nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) { - Error *err = NULL; - int ret; - - ret = pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, - PCI_PM_SIZEOF, &err); - if (err) { - error_report_err(err); - return ret; - } + pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF); pci_set_word(pci_dev->config + offset + PCI_PM_PMC, PCI_PM_CAP_VER_1_2); @@ -7343,8 +7335,6 @@ static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) PCI_PM_CTRL_NO_SOFT_RESET); pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL, PCI_PM_CTRL_STATE_MASK); - - return 0; } static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) From patchwork Mon Oct 31 12:33:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44C15C38A02 for ; Mon, 31 Oct 2022 12:36:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0k-0005gD-Nx; Mon, 31 Oct 2022 08:35:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzl-0003WF-5L for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:29 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTzh-0004Ok-Ot for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:24 -0400 Received: by mail-pj1-x1031.google.com with SMTP id k5so2700559pjo.5 for ; Mon, 31 Oct 2022 05:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rOjHWNXn/Wht1Shk+YGDnbsD8G3ScWO/Koc/z3Bsls4=; b=u2birZTKvuAI0Mbv1QJ6/Bz86V7LFLywE5wgKFdVyqk1JoCo0/SNwNIqsDqKzlqKo3 QOx4TdpNAfH2cVpNOx4q82G7zTpcf9aKpZPOodHy4y9cKybPMFN21JWsem9OXMYy/D+O Z+xeks7RP/80UoDmz5sM5qCXoFq3USY17iCeIkUQaR6IBMn04FohspNSY/D89qwK8PaI LNcAaXJqLxbPQ73eZ9OCLudBxl6qFaNlqEw9egJ9tP7CGhVpmVbloeu2dM4jw5NaNSpr dUj1C33WOr4KVWiJMW5RPGrx/WluEigeGDqh0R24vGGrTRDKrtF8jiWUrIFy5HlfXtr+ D/ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rOjHWNXn/Wht1Shk+YGDnbsD8G3ScWO/Koc/z3Bsls4=; b=QnTbdaXMgi/fq4fu8DQFqLKLD3bqTFOdVLp5cFl3o6McK170dMzQj7fgLN4+TKSdHC X7CfzXr1gwP/wGu0HPClNAdzskUQJzj5ClZUBMpYD8CNTEzcW6CYLAMoWv4GnH5L5EOH B1Ts9O9/gOZjD/qfvf4o//9okeH2HGW28o/X3trfmMeUjoLq+sQVmDl1qeKB+5850RC+ zAV5JKLPFxnr0g/Gu8irgVG0IBAsgL2703FOYyygLjXdVZYObBQ+IqF2C79QEv8E/L2w 3gGBBFcXaR7YTCS9AEv7m4ijcrZ6RFZVEHmEnIN24Y8yx9icF0nQYjvxhU6nUaV6qVMk k8Jg== X-Gm-Message-State: ACrzQf3bvUVIJ4cYHBle1Ja7Q6lylDN6WiSSUGER7tO4/d37H5nC92jx MZaubZFmKdvwb2gDNPqdTjVMBfRtwtN06/cP X-Google-Smtp-Source: AMsMyM6laLIML14feAWb6f51TQkKT23fSKTAFvnm4U8aTlfs02uM3r2mszeJSuYos1GDQe8Zn6/qVQ== X-Received: by 2002:a17:902:f68f:b0:186:9b98:8d8a with SMTP id l15-20020a170902f68f00b001869b988d8amr13975971plg.59.1667219649515; Mon, 31 Oct 2022 05:34:09 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:08 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 08/17] msi: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:10 +0900 Message-Id: <20221031123319.21532-9-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::1031; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of msi_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci/msi.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/hw/pci/msi.c b/hw/pci/msi.c index 058d1d1ef1..5283a08b5a 100644 --- a/hw/pci/msi.c +++ b/hw/pci/msi.c @@ -194,7 +194,6 @@ int msi_init(struct PCIDevice *dev, uint8_t offset, unsigned int vectors_order; uint16_t flags; uint8_t cap_size; - int config_offset; if (!msi_nonbroken) { error_setg(errp, "MSI is not supported by interrupt controller"); @@ -221,13 +220,7 @@ int msi_init(struct PCIDevice *dev, uint8_t offset, } cap_size = msi_cap_sizeof(flags); - config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, - cap_size, errp); - if (config_offset < 0) { - return config_offset; - } - - dev->msi_cap = config_offset; + dev->msi_cap = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size); dev->cap_present |= QEMU_PCI_CAP_MSI; pci_set_word(dev->config + msi_flags_off(dev), flags); From patchwork Mon Oct 31 12:33:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CC02FA3740 for ; Mon, 31 Oct 2022 12:39:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0O-00055u-At; Mon, 31 Oct 2022 08:35:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzj-0003OG-9B for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:23 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTzf-0004PD-Ni for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:22 -0400 Received: by mail-pj1-x1031.google.com with SMTP id 3-20020a17090a0f8300b00212d5cd4e5eso15766420pjz.4 for ; Mon, 31 Oct 2022 05:34:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ENEn0P7Y2heV6flYqbtW2H+Zea4rTiTJEEmDhl8ljMs=; b=5B94dceR25WnqPrCexnoxFgSt0LG248A954q9C3gB/cKIwsy9ifbC9RqkRK5MNOUsx iFsDr8ovT3nsM8rwMnLRP9tE8Quc4CbJNZkj2SVPxU6tboeT2pt24ShJ4CDuNqoK+L8G /mW1u4XzuHmQu4Fx5LQ6jyz7StJHDM5KUfHUsfQxQDdVSCDwt/BOrh+vfpalySkhtaE6 EZeUwoJAIGr7BfUOC3fumUnJnQoAbXx+Ct6xFso+aaiIeCCR8qTGNhKceLVwXete8wMc RpwhJAyvkItH09Vmir7/lycLWZPTZqnJscS7jIZLw44mWw+3lFZH+WiYKJZyQKKBD1vd 32Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ENEn0P7Y2heV6flYqbtW2H+Zea4rTiTJEEmDhl8ljMs=; b=spqArd4xScNVlxvgdOdfNPwkkA7ootY1MnFuQNyVTPM8QyBTRvkbXug29XIYSRW3UU bHRoVk176ZcvNrp7taq9dQyFdoNjXg6bb7HE4hS41qr5+Tjziy2tgXfgt7HLTpweavgR jEJhF9wIWhecMF2f/fxQlE/e7gp2R1mXmpCKbCRbjfAPmCSI8xgu/XJ81Nm7fY72bjh8 3gbZCnmUJlpZGRvuoNdlAxODqiUPJ3GYYzaXlaasWG/3lV9ka3lIYKGTPbiWM+i5+w0I lpabG7RDhG+ZUl7PRPIyWqEOf0k2mT9MRewphygFYLKE2NuH11iJqMGP/BUiFcHDyhbM 5hpg== X-Gm-Message-State: ACrzQf3tb4hPwjaVnwpB8PpGvc6fubMCZXHHlj82FihxZo2jhozH/6f2 T/naK9graLl+OUNY2y+g8BSH3JPSzXz01emF X-Google-Smtp-Source: AMsMyM60otEgMOs6tphJv3BT0aE13QgtfAux5RbQHvRn4I8LMN0Md22oNqBAOtvjoNcXG9KH7QsyvQ== X-Received: by 2002:a17:90b:4b84:b0:213:beb9:b3c1 with SMTP id lr4-20020a17090b4b8400b00213beb9b3c1mr10641331pjb.162.1667219654579; Mon, 31 Oct 2022 05:34:14 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:14 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 09/17] hw/pci/pci_bridge: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:11 +0900 Message-Id: <20221031123319.21532-10-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::1031; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of pci_bridge_ssvid_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci-bridge/i82801b11.c | 14 ++------------ hw/pci-bridge/pcie_root_port.c | 7 +------ hw/pci-bridge/xio3130_downstream.c | 8 ++------ hw/pci-bridge/xio3130_upstream.c | 8 ++------ hw/pci/pci_bridge.c | 21 ++++++--------------- include/hw/pci/pci_bridge.h | 5 ++--- 6 files changed, 15 insertions(+), 48 deletions(-) diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c index f28181e210..f45dcdbacc 100644 --- a/hw/pci-bridge/i82801b11.c +++ b/hw/pci-bridge/i82801b11.c @@ -61,21 +61,11 @@ typedef struct I82801b11Bridge { static void i82801b11_bridge_realize(PCIDevice *d, Error **errp) { - int rc; - pci_bridge_initfn(d, TYPE_PCI_BUS); - rc = pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET, - I82801ba_SSVID_SVID, I82801ba_SSVID_SSID, - errp); - if (rc < 0) { - goto err_bridge; - } + pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET, + I82801ba_SSVID_SVID, I82801ba_SSVID_SSID); pci_config_set_prog_interface(d->config, PCI_CLASS_BRIDGE_PCI_INF_SUB); - return; - -err_bridge: - pci_bridge_exitfn(d); } static const VMStateDescription i82801b11_bridge_dev_vmstate = { diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 460e48269d..a9d8c2adb4 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -74,12 +74,7 @@ static void rp_realize(PCIDevice *d, Error **errp) } pcie_port_init_reg(d); - rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, - rpc->ssid, errp); - if (rc < 0) { - error_append_hint(errp, "Can't init SSV ID, error %d\n", rc); - goto err_bridge; - } + pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, rpc->ssid); if (rpc->interrupts_init) { rc = rpc->interrupts_init(d, errp); diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 05e2b06c0c..eea3d3a2df 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -81,12 +81,8 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) goto err_bridge; } - rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, - XIO3130_SSVID_SVID, XIO3130_SSVID_SSID, - errp); - if (rc < 0) { - goto err_msi; - } + pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, + XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, p->port, errp); diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c index 5ff46ef050..d954906d79 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -71,12 +71,8 @@ static void xio3130_upstream_realize(PCIDevice *d, Error **errp) goto err_bridge; } - rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, - XIO3130_SSVID_SVID, XIO3130_SSVID_SSID, - errp); - if (rc < 0) { - goto err_msi; - } + pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, + XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, p->port, errp); diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index da34c8ebcd..30032fed64 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -42,21 +42,15 @@ #define PCI_SSVID_SVID 4 #define PCI_SSVID_SSID 6 -int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, - uint16_t svid, uint16_t ssid, - Error **errp) +void pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, + uint16_t svid, uint16_t ssid) { - int pos; + uint8_t pos; - pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, - PCI_SSVID_SIZEOF, errp); - if (pos < 0) { - return pos; - } + pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF); pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid); pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid); - return pos; } /* Accessor function to get parent bridge device from pci bus. */ @@ -455,11 +449,8 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, .mem_pref_64 = cpu_to_le64(res_reserve.mem_pref_64) }; - int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, - cap_offset, cap_len, errp); - if (offset < 0) { - return offset; - } + uint8_t offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len); memcpy(dev->config + offset + PCI_CAP_FLAGS, (char *)&cap + PCI_CAP_FLAGS, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ba4bafac7c..e499482972 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -101,9 +101,8 @@ typedef struct PXBDev PXBDev; DECLARE_INSTANCE_CHECKER(PXBDev, PXB_CXL_DEV, TYPE_PXB_CXL_DEVICE) -int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, - uint16_t svid, uint16_t ssid, - Error **errp); +void pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, + uint16_t svid, uint16_t ssid); PCIDevice *pci_bridge_get_device(PCIBus *bus); PCIBus *pci_bridge_get_sec_bus(PCIBridge *br); From patchwork Mon Oct 31 12:33:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 551EFFA3740 for ; Mon, 31 Oct 2022 12:36:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0m-0005qO-Un; Mon, 31 Oct 2022 08:35:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzl-0003WI-UU for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:29 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTzh-0004Pa-IR for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:25 -0400 Received: by mail-pl1-x62a.google.com with SMTP id 4so10644822pli.0 for ; Mon, 31 Oct 2022 05:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K62uSk0SUJ08aFWVmBuSN5NcuySA/C1fQniUaQ1ZScM=; b=PuPeiBPI4Y9SjCE7wBvva8pjpQetrY/JFiMITrdTtkJfClHKhetPWCwvMcG74eQMvS 1yjtOCppBztGFZbrvWTwPfOZNLP11Ky+aFnx2pKjTyo2/f1C/xhXLrtkdk2KcU9DYOdy 7QBfCxYIQNuatCSMR6ZW7z2ZcizJhfjGEsSnKoTFrUB4Jr7MHN0/lA58qCCvbUs1uWi0 pyhaxL5rdLOZUlDg/K48Z4N9accbBDCFlm5VA/8h7XDT/2zXqpR//6z4JCQGHUm26Xmy 8BSZc/E2rAAoBuaLCVmMfOoFBAivMlpIko/+fUDipWX3oEW7DYvwxd2g+9RfLHtyf5Ed Oeyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K62uSk0SUJ08aFWVmBuSN5NcuySA/C1fQniUaQ1ZScM=; b=C1AhASLAHErX2AK/tf3/nyO16YjIS5+05JvI/enoEJ/uRuy6ivLh2mAEVaVQcZBhnb PaQfok+0CMCvzewClIycvH1VZKDHVjORA7GIMzETZLJJ+OHnmebT5udPJkRAA7sfH7bB HsKi5nCDPCCjTZm2vUjnBokwdi23BW/8/bqXkT/4ZthytjXWYKOn4zWplUjTzwuQi8G9 rVlzKu7p4ELTLxzyrIkYpChHdY86MGeXCfY4dvgPp6t9XPrvIMJvktFxvdhU1eZDzy7L jGj1PRjPYciI23FxULWbflzdc0Wow2mroFdZqNoPiHz0394zOOg22fXZhbIY5gYXA9ve 1RbQ== X-Gm-Message-State: ACrzQf1qaKYEE/0DZf9OXgdsmt6g+6HuivTLyOrXtpbER6nyDrYQvryV cd0qqxtm/6F/kf7uoFfSXVo9qsMvz8w17rqM X-Google-Smtp-Source: AMsMyM7eH2KNKsbBWBoFeoU3YdbSyM7GSRnzNAqqgKg3eVEx8YzGMVdD/dwVDPqG2c4hXiUd63VWTg== X-Received: by 2002:a17:902:a611:b0:178:6b71:2ee5 with SMTP id u17-20020a170902a61100b001786b712ee5mr13918303plq.53.1667219659834; Mon, 31 Oct 2022 05:34:19 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:19 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki , Jonathan Cameron Subject: [PATCH v6 10/17] pcie: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:12 +0900 Message-Id: <20221031123319.21532-11-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::62a; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of a PCIe function which calls pci_add_capability() in turn is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki Acked-by: Jonathan Cameron (for CXL parts) --- docs/pcie_sriov.txt | 4 +-- hw/display/bochs-display.c | 4 +-- hw/net/e1000e.c | 4 +-- hw/pci-bridge/cxl_downstream.c | 9 ++---- hw/pci-bridge/cxl_upstream.c | 8 ++--- hw/pci-bridge/pcie_pci_bridge.c | 6 +--- hw/pci-bridge/pcie_root_port.c | 9 +----- hw/pci-bridge/xio3130_downstream.c | 7 +--- hw/pci-bridge/xio3130_upstream.c | 7 +--- hw/pci-host/designware.c | 3 +- hw/pci-host/xilinx-pcie.c | 4 +-- hw/pci/pcie.c | 52 ++++++++---------------------- hw/usb/hcd-xhci-pci.c | 3 +- hw/virtio/virtio-pci.c | 3 +- include/hw/pci/pcie.h | 11 +++---- 15 files changed, 35 insertions(+), 99 deletions(-) diff --git a/docs/pcie_sriov.txt b/docs/pcie_sriov.txt index 11158dbf88..728a73ba7b 100644 --- a/docs/pcie_sriov.txt +++ b/docs/pcie_sriov.txt @@ -49,7 +49,7 @@ setting up a BAR for a VF. pci_your_pf_dev_realize( ... ) { ... - int ret = pcie_endpoint_cap_init(d, 0x70); + pcie_endpoint_cap_init(d, 0x70); ... pcie_ari_init(d, 0x100, 1); ... @@ -79,7 +79,7 @@ setting up a BAR for a VF. pci_your_vf_dev_realize( ... ) { ... - int ret = pcie_endpoint_cap_init(d, 0x60); + pcie_endpoint_cap_init(d, 0x60); ... pcie_ari_init(d, 0x100, 1); ... diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c index 8ed734b195..111cabcfb3 100644 --- a/hw/display/bochs-display.c +++ b/hw/display/bochs-display.c @@ -265,7 +265,6 @@ static void bochs_display_realize(PCIDevice *dev, Error **errp) { BochsDisplayState *s = BOCHS_DISPLAY(dev); Object *obj = OBJECT(dev); - int ret; if (s->vgamem < 4 * MiB) { error_setg(errp, "bochs-display: video memory too small"); @@ -302,8 +301,7 @@ static void bochs_display_realize(PCIDevice *dev, Error **errp) } if (pci_bus_is_express(pci_get_bus(dev))) { - ret = pcie_endpoint_cap_init(dev, 0x80); - assert(ret > 0); + pcie_endpoint_cap_init(dev, 0x80); } else { dev->cap_present &= ~QEMU_PCI_CAP_EXPRESS; } diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index e433b8f9a5..aea4305c43 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -462,9 +462,7 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp) e1000e_init_msix(s); - if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) { - hw_error("Failed to initialize PCIe capability"); - } + pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset); ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL); if (ret) { diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index a361e519d0..1980dd9c6c 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -155,12 +155,8 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) goto err_bridge; } - rc = pcie_cap_init(d, CXL_DOWNSTREAM_PORT_EXP_OFFSET, - PCI_EXP_TYPE_DOWNSTREAM, p->port, - errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, CXL_DOWNSTREAM_PORT_EXP_OFFSET, + PCI_EXP_TYPE_DOWNSTREAM, p->port); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); @@ -195,7 +191,6 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) pcie_chassis_del_slot(s); err_pcie_cap: pcie_cap_exit(d); - err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index a83a3e81e4..26f27ba681 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -138,11 +138,8 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) goto err_bridge; } - rc = pcie_cap_init(d, CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET, - PCI_EXP_TYPE_UPSTREAM, p->port, errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET, + PCI_EXP_TYPE_UPSTREAM, p->port); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); @@ -165,7 +162,6 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) err_cap: pcie_cap_exit(d); -err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c index 1cd917a459..df5dfdd139 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -47,10 +47,7 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) goto error; } - rc = pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, errp); - if (rc < 0) { - goto cap_error; - } + pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0); pos = pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); if (pos < 0) { @@ -90,7 +87,6 @@ msi_error: aer_error: pm_error: pcie_cap_exit(d); -cap_error: shpc_cleanup(d, &pcie_br->shpc_bar); error: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index a9d8c2adb4..92cebc7cce 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -83,13 +83,7 @@ static void rp_realize(PCIDevice *d, Error **errp) } } - rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, - p->port, errp); - if (rc < 0) { - error_append_hint(errp, "Can't add Root Port capability, " - "error %d\n", rc); - goto err_int; - } + pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, p->port); pcie_cap_arifwd_init(d); pcie_cap_deverr_init(d); @@ -120,7 +114,6 @@ err: pcie_chassis_del_slot(s); err_pcie_cap: pcie_cap_exit(d); -err_int: if (rpc->interrupts_uninit) { rpc->interrupts_uninit(d); } diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index eea3d3a2df..37307c8c23 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -84,11 +84,7 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); - rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, - p->port, errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, p->port); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); pcie_cap_slot_init(d, s); @@ -113,7 +109,6 @@ err: pcie_chassis_del_slot(s); err_pcie_cap: pcie_cap_exit(d); -err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c index d954906d79..546224d97c 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -74,11 +74,7 @@ static void xio3130_upstream_realize(PCIDevice *d, Error **errp) pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); - rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, - p->port, errp); - if (rc < 0) { - goto err_msi; - } + pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, p->port); pcie_cap_flr_init(d); pcie_cap_deverr_init(d); @@ -92,7 +88,6 @@ static void xio3130_upstream_realize(PCIDevice *d, Error **errp) err: pcie_cap_exit(d); -err_msi: msi_uninit(d); err_bridge: pci_bridge_exitfn(d); diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index bde3a343a2..3e4972ad76 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -414,8 +414,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) pcie_port_init_reg(dev); - pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT, - 0, &error_fatal); + pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT, 0); msi_nonbroken = true; msi_init(dev, 0x50, 32, true, true, &error_fatal); diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c index 38d5901a45..49f0ac5e35 100644 --- a/hw/pci-host/xilinx-pcie.c +++ b/hw/pci-host/xilinx-pcie.c @@ -282,9 +282,7 @@ static void xilinx_pcie_root_realize(PCIDevice *pci_dev, Error **errp) pci_bridge_initfn(pci_dev, TYPE_PCI_BUS); - if (pcie_endpoint_cap_v1_init(pci_dev, 0x80) < 0) { - error_setg(errp, "Failed to initialize PCIe capability"); - } + pcie_endpoint_cap_v1_init(pci_dev, 0x80); } static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 68a62da0b5..923ad29c52 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -151,21 +151,15 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) } } -int pcie_cap_init(PCIDevice *dev, uint8_t offset, - uint8_t type, uint8_t port, - Error **errp) +void pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) { /* PCIe cap v2 init */ - int pos; + uint8_t pos; uint8_t *exp_cap; assert(pci_is_express(dev)); - pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, - PCI_EXP_VER2_SIZEOF, errp); - if (pos < 0) { - return pos; - } + pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER2_SIZEOF); dev->exp.exp_cap = pos; exp_cap = dev->config + pos; @@ -185,38 +179,26 @@ int pcie_cap_init(PCIDevice *dev, uint8_t offset, /* read-only to behave like a 'NULL' Extended Capability Header */ pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0); } - - return pos; } -int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, - uint8_t port) +void pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type, + uint8_t port) { /* PCIe cap v1 init */ - int pos; - Error *local_err = NULL; + uint8_t pos; assert(pci_is_express(dev)); - pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, - PCI_EXP_VER1_SIZEOF, &local_err); - if (pos < 0) { - error_report_err(local_err); - return pos; - } + pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, PCI_EXP_VER1_SIZEOF); dev->exp.exp_cap = pos; pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1); - - return pos; } -static int +static void pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) { uint8_t type = PCI_EXP_TYPE_ENDPOINT; - Error *local_err = NULL; - int ret; /* * Windows guests will report Code 10, device cannot start, if @@ -229,26 +211,20 @@ pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) } if (cap_size == PCI_EXP_VER1_SIZEOF) { - return pcie_cap_v1_init(dev, offset, type, 0); + pcie_cap_v1_init(dev, offset, type, 0); } else { - ret = pcie_cap_init(dev, offset, type, 0, &local_err); - - if (ret < 0) { - error_report_err(local_err); - } - - return ret; + pcie_cap_init(dev, offset, type, 0); } } -int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) +void pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) { - return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); + pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF); } -int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) +void pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset) { - return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); + pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF); } void pcie_cap_exit(PCIDevice *dev) diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c index e934b1a5b1..0eba2b36ae 100644 --- a/hw/usb/hcd-xhci-pci.c +++ b/hw/usb/hcd-xhci-pci.c @@ -150,8 +150,7 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp) if (pci_bus_is_express(pci_get_bus(dev)) || xhci_get_flag(&s->xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { - ret = pcie_endpoint_cap_init(dev, 0xa0); - assert(ret > 0); + pcie_endpoint_cap_init(dev, 0xa0); } if (s->msix != ON_OFF_AUTO_OFF) { diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 45327f0b31..c37bdc77ea 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1862,8 +1862,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp) int pos; uint16_t last_pcie_cap_offset = PCI_CONFIG_SPACE_SIZE; - pos = pcie_endpoint_cap_init(pci_dev, 0); - assert(pos > 0); + pcie_endpoint_cap_init(pci_dev, 0); pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 798a262a0a..7a35851ae8 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -92,13 +92,12 @@ struct PCIExpressDevice { #define COMPAT_PROP_PCP "power_controller_present" /* PCI express capability helper functions */ -int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, - uint8_t port, Error **errp); -int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, - uint8_t type, uint8_t port); -int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset); +void pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port); +void pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, + uint8_t type, uint8_t port); +void pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset); void pcie_cap_exit(PCIDevice *dev); -int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset); +void pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset); void pcie_cap_v1_exit(PCIDevice *dev); uint8_t pcie_cap_get_type(const PCIDevice *dev); void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector); From patchwork Mon Oct 31 12:33:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5FECFA3740 for ; Mon, 31 Oct 2022 12:38:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0p-00062G-EI; Mon, 31 Oct 2022 08:35:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzr-0003ea-SS for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:31 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTzn-0004Qo-56 for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:29 -0400 Received: by mail-pg1-x534.google.com with SMTP id h193so1879957pgc.10 for ; Mon, 31 Oct 2022 05:34:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NRuCwoKWiPF/zQ4ogg7uItA8DuEE4aQtCuC8AzGLcFo=; b=ureHZbayRPBZR6d1zQc1t/5iOcN/AGpraBTkqRN47pKZg4fsEv514rLV3rBzPhv4mo aLqvXIiZbrXF+71zgSKW3uFTgLROsHy9HJ9+K4QXdGSGBLYYFJPB8LCg1uumUF8GxRNf eSOQgKu1/STEGjfpQSElV/KarOt1gAWBjC68EJqf+ySc+8//BUad4jpumpvwUxzikB8R W3I5gGJeXl+hoAJew9PaGNl9yTdgBTg4kjVfojJfXgJ/qrl8kNDVatmuMNb9ibXCkGL/ fRcWhzptqyEJ1q+uw3nP0gz/1LnilTkkiIdqpZHAtEv8ZXL/MubsCvkLNgE1ar0+C8dF BBHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NRuCwoKWiPF/zQ4ogg7uItA8DuEE4aQtCuC8AzGLcFo=; b=FNwZNlttVLmU0+sX3e+lTGicR+owfBSs02wERl3p3trl0jP+7sJOFcZHS0frCgv94I u9Elen0g9weDnzz6qPi+/WxHE2XRfwSHPRzhJQ/rcHyTFtKdhLZDhE6JkbQoTPnl/4gh x/yLVPApKkxXe+D3E/KaP7EB0gAPV3GK6dH/n54IuqTenLqPn0BL5gloFJglDpisJj5K hl1Tkn46025MKpmmPxkflZA+4h8gsOjA8V9d4nwdo91q+Y3s9ZS9YKl3NCiy47w3B/gy sDuen3PBSaNuplzpbwXWpsLzV+bMjjsegknbS4OVXfu4cgN5ezgvof2aZtZoJ9l2GJfm BnFw== X-Gm-Message-State: ACrzQf3338MzP9TKBhlbIJtVTsugEIbOGQb46vr4ijpGB77N1XbITuKT AsO/ibfCnxVJvL8GxNqwf0O1+bxtVH80nMfi X-Google-Smtp-Source: AMsMyM7QjYUADvyoq1yKcmRTLYyj7dcizPv3tuHoHX0Ww51C3gU/BLqzz8eMkD8yG5nDbLpN6E9Dsg== X-Received: by 2002:a63:6cc2:0:b0:46f:cec6:c9b2 with SMTP id h185-20020a636cc2000000b0046fcec6c9b2mr3097878pgc.167.1667219664924; Mon, 31 Oct 2022 05:34:24 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:24 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 11/17] pci/shpc: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:13 +0900 Message-Id: <20221031123319.21532-12-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::534; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of shpc_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci-bridge/pci_bridge_dev.c | 2 +- hw/pci-bridge/pcie_pci_bridge.c | 2 +- hw/pci/shpc.c | 23 ++++++----------------- include/hw/pci/shpc.h | 3 +-- 4 files changed, 9 insertions(+), 21 deletions(-) diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index 657a06ddbe..4b6d1876eb 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -66,7 +66,7 @@ static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp) dev->config[PCI_INTERRUPT_PIN] = 0x1; memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar", shpc_bar_size(dev)); - err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0, errp); + err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0); if (err) { goto shpc_error; } diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c index df5dfdd139..99778e3e24 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -42,7 +42,7 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) d->config[PCI_INTERRUPT_PIN] = 0x1; memory_region_init(&pcie_br->shpc_bar, OBJECT(d), "shpc-bar", shpc_bar_size(d)); - rc = shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp); + rc = shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0); if (rc) { goto error; } diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index e71f3a7483..5b3228c793 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -440,16 +440,11 @@ static void shpc_cap_update_dword(PCIDevice *d) } /* Add SHPC capability to the config space for the device. */ -static int shpc_cap_add_config(PCIDevice *d, Error **errp) +static void shpc_cap_add_config(PCIDevice *d) { uint8_t *config; - int config_offset; - config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC, - 0, SHPC_CAP_LENGTH, - errp); - if (config_offset < 0) { - return config_offset; - } + uint8_t config_offset; + config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC, 0, SHPC_CAP_LENGTH); config = d->config + config_offset; pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0); @@ -459,7 +454,6 @@ static int shpc_cap_add_config(PCIDevice *d, Error **errp) /* Make dword select and data writable. */ pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff); pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff); - return 0; } static uint64_t shpc_mmio_read(void *opaque, hwaddr addr, @@ -584,18 +578,13 @@ void shpc_device_unplug_request_cb(HotplugHandler *hotplug_dev, } /* Initialize the SHPC structure in bridge's BAR. */ -int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, - unsigned offset, Error **errp) +int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset) { - int i, ret; + int i; int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */ SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc)); shpc->sec_bus = sec_bus; - ret = shpc_cap_add_config(d, errp); - if (ret) { - g_free(d->shpc); - return ret; - } + shpc_cap_add_config(d); if (nslots < SHPC_MIN_SLOTS) { return 0; } diff --git a/include/hw/pci/shpc.h b/include/hw/pci/shpc.h index d5683b7399..18ab16ec9f 100644 --- a/include/hw/pci/shpc.h +++ b/include/hw/pci/shpc.h @@ -38,8 +38,7 @@ struct SHPCDevice { void shpc_reset(PCIDevice *d); int shpc_bar_size(PCIDevice *dev); -int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, - unsigned off, Error **errp); +int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned off); void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar); void shpc_free(PCIDevice *dev); void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len); From patchwork Mon Oct 31 12:33:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94DCDC38A02 for ; Mon, 31 Oct 2022 12:40:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0s-0006Gg-6x; Mon, 31 Oct 2022 08:35:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzv-0003ni-UQ for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:36 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTzt-0004Sw-Ce for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:35 -0400 Received: by mail-pj1-x1029.google.com with SMTP id m2so10263526pjr.3 for ; Mon, 31 Oct 2022 05:34:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ve64Yknp9Z5jtrd7y/2CScvNeMugfa6S0tD/94xCa3A=; b=ftnYt/0fDgjS0EKUSqUIqx61YJHzGLpuTcVHaUlKt8tKNyDLkzAkU8Atbh8+6p/hMC Ewm/WDLAQMIsn4KaJqjmsQJseBhAqF28CPnhve6jC74tPwzDnDH7iaWbPAZU579ShDAH LGqOg62B4B/Vvp+7AOiwZdNI79ODUPsNdK2oSmsm7HYsamzG/s66yYggXsdHWvt0sbu/ kvMzUF98O1jE21bryhNLpkRBBzmwjFx2ajgpxbVZpLnu+VEpF5LGPe6vEh5oXLBA5wTC Dzn+tr73ttQxOXUvn+Q2aZpeKwJPRPncSsz+KSQJTuwQ0wXPwzO4MOX6x0GGpb9gdhjG 205A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ve64Yknp9Z5jtrd7y/2CScvNeMugfa6S0tD/94xCa3A=; b=GUvSJybQ0VGBPD398lXpdCWlOcsKNSrePaZO7GS981y4GwJAM4dqXatqhAKNqympxT iHEBo75z0FxJK47DEavhKJRRVaZdMPZBBKd5CW/0GtzGDtHZabJyVBg5l54HpY+CtoUv sjL3EIrtDbiotuYIb2a4OqUvKVc1O6P182UPWtnT4Nkp3dyfh7d6/AOUDii2m8tjpnkw AJ+YCFdjFj3kVnSJwpjRCpZXXv8cDaLGX4zcXxmO+R+RUHgMa2joiVu5QzCCBn7MPSFR DFDY9HZ6F2Ru6dBqpKBurNmNbjGBHn23Vmt/X+ZqGxMtclkbSPlbTIDiMl1cEwh5QDMS nQ8Q== X-Gm-Message-State: ACrzQf3zIgS3VOgJy89MxdN2kmfviEO8HMqUUDDMuWDQgemGuS+r23DH csx8XXlKKgICcdO+Gt4z+ZHsfmHZzuDqF2+U X-Google-Smtp-Source: AMsMyM5UhGtSDVCMrW0GUdiXLIMQ8ZyU5G3L8l6R3WcEK6V6gLUEgAz3lto4ES8//kIpfnKAuc+dVw== X-Received: by 2002:a17:90b:1918:b0:213:d97c:c6c9 with SMTP id mp24-20020a17090b191800b00213d97cc6c9mr6522557pjb.198.1667219671930; Mon, 31 Oct 2022 05:34:31 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:29 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 12/17] msix: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:14 +0900 Message-Id: <20221031123319.21532-13-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::1029; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of msix_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci/msix.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/pci/msix.c b/hw/pci/msix.c index 1e381a9813..28af83403b 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -311,7 +311,7 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries, uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos, Error **errp) { - int cap; + uint8_t cap; unsigned table_size, pba_size; uint8_t *config; @@ -340,11 +340,7 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries, return -EINVAL; } - cap = pci_add_capability(dev, PCI_CAP_ID_MSIX, - cap_pos, MSIX_CAP_LENGTH, errp); - if (cap < 0) { - return cap; - } + cap = pci_add_capability(dev, PCI_CAP_ID_MSIX, cap_pos, MSIX_CAP_LENGTH); dev->msix_cap = cap; dev->cap_present |= QEMU_PCI_CAP_MSIX; From patchwork Mon Oct 31 12:33:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42E5FC38A02 for ; Mon, 31 Oct 2022 12:38:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0v-0006S0-Dd; Mon, 31 Oct 2022 08:35:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opU00-0003qw-NL for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:47 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTzz-0004UC-9J for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:40 -0400 Received: by mail-pg1-x52f.google.com with SMTP id 128so10597003pga.1 for ; Mon, 31 Oct 2022 05:34:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ulXMgjC1nhezaSD23eulJZtw/gqtaE7ewFuc5xi9szM=; b=bFNVJdiupLN+zfeGsQDegx2y6j6IbuBt5ao2H3NjbDFMFhOeRmzTW6yqofKHjjupey poVbd0Ha4RzUErZ5wW6E8fTZZbZxCKVvW95ARm4vGK2bhVnKzpNL0C+AsVQ6OKSEnKK2 r/rt5yKIBoQ8qL1DZG9/I8EZTjT4AfZGYNjXC5bGT3L+mhpiFDzMAQ7X1NPR9alXl7B1 xZgZLcwOej4FbbcEAnNaQNocqxgsxP2sB3FLDfkwlkfTdgoXG7mBzmEOw4OJxVUzY5Pr 2lt8eqVg1Fr2h274Qc8k0GWkoxXxXRv0VVH0/0CRvhD86hzjocw/KiHbb9o9VG+HLWhp 1f1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ulXMgjC1nhezaSD23eulJZtw/gqtaE7ewFuc5xi9szM=; b=rVeQrYFicgOMVEN4qj/Eyvi6fZexFzbeY1Hl6mBfpfGhm2M7mDkpuZ/zgPWAWXtMHD r0d9N+UXT71sOusXAgiiuT3UqfwadeY02ZU5Pd07ei1MJxK++1PSEvMcm6ljE7jhgtqP h4c+7SmnxZm7riyWyUoZqcjA3PakulhjswqmyiodPxe10H1xmVGX6dH7yvcQkxO+fzrx WVJ1tP1aarte3LbjtZzg62AezPAZRg0/FYzNsaASGhCRoPmX7EO68wvdkFzjFcGK1RfV e7QpgzToWvejUZmxncJJXxe4Id7kfjk46o4wT6TuYADXeolnY4yULbbM+FX5wbag4ume cZDQ== X-Gm-Message-State: ACrzQf0bZg8TWCN5mace6kIsmIxRVHe1eEqPsgIbPo7zLeHMpE0IzuHn MB7kWP4VieJ+ZM3ZRAuOHp8Egg9rGewE6vRB X-Google-Smtp-Source: AMsMyM7YOC8L6ORtZqD/K7UnlykX6EuAVWyefZcjp4BSB24RVxg2queg1+lkVbBqmIyiGAxCDT6JHA== X-Received: by 2002:a63:6b83:0:b0:460:c07c:553b with SMTP id g125-20020a636b83000000b00460c07c553bmr12393717pgc.209.1667219676982; Mon, 31 Oct 2022 05:34:36 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:36 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 13/17] pci/slotid: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:15 +0900 Message-Id: <20221031123319.21532-14-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::52f; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of slotid_cap_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci/slotid_cap.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/pci/slotid_cap.c b/hw/pci/slotid_cap.c index 36d021b4a6..5da8c82133 100644 --- a/hw/pci/slotid_cap.c +++ b/hw/pci/slotid_cap.c @@ -12,7 +12,7 @@ int slotid_cap_init(PCIDevice *d, int nslots, unsigned offset, Error **errp) { - int cap; + uint8_t cap; if (!chassis) { error_setg(errp, "Bridge chassis not specified. Each bridge is required" @@ -24,11 +24,7 @@ int slotid_cap_init(PCIDevice *d, int nslots, return -EINVAL; } - cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, - SLOTID_CAP_LENGTH, errp); - if (cap < 0) { - return cap; - } + cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, SLOTID_CAP_LENGTH); /* We make each chassis unique, this way each bridge is First in Chassis */ d->config[cap + PCI_SID_ESR] = PCI_SID_ESR_FIC | (nslots << SLOTID_NSLOTS_SHIFT); From patchwork Mon Oct 31 12:33:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5F56C38A02 for ; Mon, 31 Oct 2022 12:38:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU11-0006ep-E2; Mon, 31 Oct 2022 08:35:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opU05-0003rW-Iz for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:47 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opU03-0004Yh-KL for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:45 -0400 Received: by mail-pj1-x102f.google.com with SMTP id m14-20020a17090a3f8e00b00212dab39bcdso15841424pjc.0 for ; Mon, 31 Oct 2022 05:34:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SnM99KyqX7P48Yqolo9mjrgei37okMKuMCflMKIVI0w=; b=AZjM7NlOo7EPDOHogbz96xCiBFDeAuB8YW/vahA4p5CgU+QiX51G8rq95AvKil4abP HgFgQ2odOpmT9eJqJTTdy0VzJ+xI6EU7DL+CRp0YOLD/SGj3kRNs42/Uk/mwtk+QZQxe jiXJoZ4ene1s/HMn0rWQ4oCvHmgRr/vuUN8wxbqme2Tu6r7fGHsZtcHdLNiWfAWAgVKN R+nKJ+n8yupaJwDy3jCox2jy7h2Zq1EjO39VmV1e4ReXjlq6dR6ywnaVKoZvjWxxDAwm fGr4lwDe7sA89GiiwcgneZcXVFibBBaT/Nxch+h2CGCxDAmLUjZLTW60s+r2Zs1DUDxy Le+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SnM99KyqX7P48Yqolo9mjrgei37okMKuMCflMKIVI0w=; b=wGguGOfu4FRs0zPi/XaU70EJSZb/F63or53crWCQFYGjUCP5hprLoF9qjEAAnV3L2y v/k14rugCLxNJhtauEY05o7AgyPEPUbu9YX+tsgwki4wtAsBAm3Kev8th9/aJVHgEpWd +nppCTV0LeKT7WIvSmNcE50fjn6yyiS/kF/rd9JWgZghLfuMpsBa/+K6eSUJMgCRtAXE rG/QZQ9u88976wooC3nFPwUHz6f9HEDrJWKyf7CpFw7T6zLYqZlBKlG5IcWZW0gBI86c Yo0tb5GFAqahh9dpq1XW2wbCF3NUeEW4D5akj6uMXugHlYOjmT3klsCpDG9Fp2TpCZKA olyA== X-Gm-Message-State: ACrzQf3OZabrC3UA13y856h7xZtEoLHYWzbQCVul4rdTN+RunFkLIkQT iiGg/58dhpcCdZCfDf+802yymuez2OQxXnfn X-Google-Smtp-Source: AMsMyM72SlmHGd1FAoF/ZXypo3f4kAs5i/yaBtbutB1WCSPtuh8ymBuRfM0Mpx4Evd/0l7vN5ByZvw== X-Received: by 2002:a17:90b:4c46:b0:213:d3e3:ba44 with SMTP id np6-20020a17090b4c4600b00213d3e3ba44mr7183833pjb.18.1667219682119; Mon, 31 Oct 2022 05:34:42 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:41 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 14/17] hw/pci-bridge/pcie_pci_bridge: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:16 +0900 Message-Id: <20221031123319.21532-15-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::102f; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate heare because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/pci-bridge/pcie_pci_bridge.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c index 99778e3e24..1b839465e7 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -35,7 +35,7 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) { PCIBridge *br = PCI_BRIDGE(d); PCIEPCIBridge *pcie_br = PCIE_PCI_BRIDGE_DEV(d); - int rc, pos; + int rc; pci_bridge_initfn(d, TYPE_PCI_BUS); @@ -49,12 +49,8 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0); - pos = pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); - if (pos < 0) { - goto pm_error; - } - d->exp.pm_cap = pos; - pci_set_word(d->config + pos + PCI_PM_PMC, 0x3); + d->exp.pm_cap = pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF); + pci_set_word(d->config + d->exp.pm_cap + PCI_PM_PMC, 0x3); pcie_cap_arifwd_init(d); pcie_cap_deverr_init(d); @@ -85,7 +81,6 @@ static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) msi_error: pcie_aer_exit(d); aer_error: -pm_error: pcie_cap_exit(d); shpc_cleanup(d, &pcie_br->shpc_bar); error: From patchwork Mon Oct 31 12:33:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3531BFA3740 for ; Mon, 31 Oct 2022 12:38:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU1F-0007KG-JD; Mon, 31 Oct 2022 08:35:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opU0O-00057Q-Ku for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:35:04 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opU08-0004Qf-6i for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:35:04 -0400 Received: by mail-pg1-x535.google.com with SMTP id r18so10547687pgr.12 for ; Mon, 31 Oct 2022 05:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X6IxClWqWb6CZpSBnvYuO1So2GK7x/G/Cu2kKWY3Y/g=; b=m3p4+wzCN51/W4ls7oV3xOsRrjPaftqnO6iji8OLULaXW+zLyffD7DMS3REv8Ah/ga CukiG6bMVfh+gVP16RhaHKr6p99/DktpbbncepksWBB2Xn/54gZVZ6OIwmehe9iS3jDK ekNJ3XpXQ+0tLkJW/nyaDJTEsenYIg+LhOeooBOrAnGt3PRls/wLZOC6h0A7N3P6q8t6 1yVluRhC8cEbCfes43hWKqxAmBWH9+SacvTyRzbHliTazCvUphp8t8v9tf47o8R0c1C/ eQiJlXahUlsxYgi41aXmBefv25kKaDWGVNwXeiDW7Olq0rtOMsj7zHZTVyQ18zP5eeBQ UzZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X6IxClWqWb6CZpSBnvYuO1So2GK7x/G/Cu2kKWY3Y/g=; b=FWwKevce8Rm573z2HcU3jtMHaknQzn30rpP8UMTSAD8Vzzo9r/p4B2zzSzuMVSQzXs D8ML9MNjANDNV1nGT7nxHIqDaQeOUKUZQhde9xUhtRTUfMJYbgUaI/ES1GWffVEgPehK jCT3gyfiLcRHbcJzFXKJVRgBDLTccMlIV0COkFpkv6qgYrlFnTCzsh2iTOzuPGkrR/xV 795PWG0rzRb3YBMsLsy9a66/6vmXhVnBIdRVlfaOnubMwPExn5VzKNohCw2fFtIw9sxZ BVhwIsA4JLkF2MjzzU0F1c26Hl51ycAoRBdPRgwMCQDA7lRt7Rq8y+ipvcE858X02xdd hq2A== X-Gm-Message-State: ACrzQf0CwXQCdk5OEqLtK/uI9tC9BKNOZ0C68biLBGsR8Fnz7KET0pzm AxidH/Dnf3zaJ+gYwKC0VAZYX7p8Vjr7yTl5 X-Google-Smtp-Source: AMsMyM79Ko1XFMVf8SHXhKIVZBNR+HSEfPzS07HSzOgjvtkcBCetarQQQqOIs92u8jGElpLHMGxWWA== X-Received: by 2002:a63:5f54:0:b0:462:1149:f3b3 with SMTP id t81-20020a635f54000000b004621149f3b3mr12364519pgb.445.1667219687133; Mon, 31 Oct 2022 05:34:47 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:46 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 15/17] hw/vfio/pci: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:17 +0900 Message-Id: <20221031123319.21532-16-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::535; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org The code generating errors in pci_add_capability has a comment which says: > Verify that capabilities don't overlap. Note: device assignment > depends on this check to verify that the device is not broken. > Should never trigger for emulated devices, but it's helpful for > debugging these. Indeed vfio has some code that passes capability offsets and sizes from a physical device, but it explicitly pays attention so that the capabilities never overlap. Therefore, in pci_add_capability(), we can always assert that capabilities never overlap, and that is what happens when omitting errp. Signed-off-by: Akihiko Odaki --- hw/vfio/pci-quirks.c | 15 +++------------ hw/vfio/pci.c | 14 +++++--------- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index f0147a050a..e94fd273ea 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1530,7 +1530,7 @@ const PropertyInfo qdev_prop_nv_gpudirect_clique = { static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp) { PCIDevice *pdev = &vdev->pdev; - int ret, pos = 0xC8; + int pos = 0xC8; if (vdev->nv_gpudirect_clique == 0xFF) { return 0; @@ -1547,11 +1547,7 @@ static int vfio_add_nv_gpudirect_cap(VFIOPCIDevice *vdev, Error **errp) return -EINVAL; } - ret = pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add NVIDIA GPUDirect cap: "); - return ret; - } + pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, 8); memset(vdev->emulated_config_bits + pos, 0xFF, 8); pos += PCI_CAP_FLAGS; @@ -1718,12 +1714,7 @@ static int vfio_add_vmd_shadow_cap(VFIOPCIDevice *vdev, Error **errp) return -EFAULT; } - ret = pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, - VMD_SHADOW_CAP_LEN, errp); - if (ret < 0) { - error_prepend(errp, "Failed to add VMD MEMBAR Shadow cap: "); - return ret; - } + pci_add_capability(&vdev->pdev, PCI_CAP_ID_VNDR, pos, VMD_SHADOW_CAP_LEN); memset(vdev->emulated_config_bits + pos, 0xFF, VMD_SHADOW_CAP_LEN); pos += PCI_CAP_FLAGS; diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index c7e3ef95a7..cad5850f5e 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1845,7 +1845,7 @@ static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos, vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); } -static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, +static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, uint8_t pos, uint8_t size, Error **errp) { uint16_t flags; @@ -1962,11 +1962,7 @@ static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, 1, PCI_EXP_FLAGS_VERS); } - pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, - errp); - if (pos < 0) { - return pos; - } + pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); vdev->pdev.exp.exp_cap = pos; @@ -2080,14 +2076,14 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp) case PCI_CAP_ID_PM: vfio_check_pm_reset(vdev, pos); vdev->pm_cap = pos; - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; case PCI_CAP_ID_AF: vfio_check_af_flr(vdev, pos); - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; default: - ret = pci_add_capability(pdev, cap_id, pos, size, errp); + pci_add_capability(pdev, cap_id, pos, size); break; } From patchwork Mon Oct 31 12:33:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5DBBC38A02 for ; Mon, 31 Oct 2022 12:38:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU19-0006vJ-Qx; Mon, 31 Oct 2022 08:35:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opU0G-0004Wj-1q for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:56 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opU0D-0004Ok-AO for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:55 -0400 Received: by mail-pj1-x1031.google.com with SMTP id k5so2702124pjo.5 for ; Mon, 31 Oct 2022 05:34:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GSC2v4ngPUcx+TLSPrzIkvnSf/m2yHNZ/Q2yIIKBef8=; b=noYmXoS6xvS9xEdOiu9N+6kfbHdXezMRVuA5OMJPuGnRdilLo2mVJT7AcBcL32ty3R fh1HQKLgmkvFHlaUsol1wjeK4nvm0IYKi9O92nnxoseU1iC5eG9829cxdImF5rQaC2Hz p71yGNz+CgTBHqPtS/cj/fljCL3pJKz1PvBN0p9Eh/b//iyiGE/F/t3AHWW2W4jBK3wH wI90Ztuxm6t/XTghYGJBWuss8KgShLt1kWr3fTh0kO/fa+dQYsZaIjtddwELkPfn6bg0 p2Wfj+Qf+fwGI3LoYqoFxn6TI9HDQArcSUJ97JVmmDuUKBB/TzptFg/XY1Np9tAPMQBw 8kMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GSC2v4ngPUcx+TLSPrzIkvnSf/m2yHNZ/Q2yIIKBef8=; b=ic2SFrjeFZyaFYO39CHnJHdSl4gk3X4aqqlqZthhSSNuP/6puPPCEnwT794D+5caHW hVuyRsaUPrvqBX3peSIMtXo48Z2EDgF1LX+q5C1oHALRgO2ogrq9AYfi14K7pUJfQ74w d4YGbVpQ6tI39uloEABLfRU3S3JtiKx1X7i9B3qaahy2qeynrxaOM26iYgEWEMBPb8y/ KVKK3H30GeEs13MY2UhphzGhViN/Wd9LH7dBduNEOnITj49hNIOg8nYe/MqWFrRcnAtJ 5+GMrQwM3GIk10TxD1Cvj1ikCrbvu07ZnrGMsGs/Ekm7xHUSk3pdTLTYQLgfdwOvdxjC akIA== X-Gm-Message-State: ACrzQf0wmrx3KcEk+mXN/VdrYYG03htYiz3X2PITATpwBe7ExckNYnpM 0pKEjG7VNSWdc0tbtLUvqgUDrAbVcKXeHq6e X-Google-Smtp-Source: AMsMyM625CzzWVI8HLxwP0f5Q1RNdVF/OzF0AEIFjiLiOqdoFQczbFTcaXoyRSJBdUlM48Wl3PS6/Q== X-Received: by 2002:a17:90b:3013:b0:213:ab5f:d388 with SMTP id hg19-20020a17090b301300b00213ab5fd388mr12996481pjb.66.1667219692233; Mon, 31 Oct 2022 05:34:52 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:51 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 16/17] virtio-pci: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:18 +0900 Message-Id: <20221031123319.21532-17-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::1031; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. This behavior is appropriate here because all of the capabilities set in this device are defined in the program and their overlap should not happen unless there is a programming error. Signed-off-by: Akihiko Odaki --- hw/virtio/virtio-pci.c | 9 ++------- include/hw/virtio/virtio-pci.h | 2 +- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index c37bdc77ea..b393ff01be 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1154,8 +1154,7 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy, PCIDevice *dev = &proxy->pci_dev; int offset; - offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, - cap->cap_len, &error_abort); + offset = pci_add_capability(dev, PCI_CAP_ID_VNDR, 0, cap->cap_len); assert(cap->cap_len >= sizeof *cap); memcpy(dev->config + offset + PCI_CAP_FLAGS, &cap->cap_len, @@ -1864,11 +1863,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp) pcie_endpoint_cap_init(pci_dev, 0); - pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, - PCI_PM_SIZEOF, errp); - if (pos < 0) { - return; - } + pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF); pci_dev->exp.pm_cap = pos; diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index 2446dcd9ae..9f3736723c 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -141,7 +141,7 @@ struct VirtIOPCIProxy { uint32_t msix_bar_idx; uint32_t modern_io_bar_idx; uint32_t modern_mem_bar_idx; - int config_cap; + uint8_t config_cap; uint32_t flags; bool disable_modern; bool ignore_backend_features; From patchwork Mon Oct 31 12:33:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 13025745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98A3DFA3742 for ; Mon, 31 Oct 2022 12:39:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU1D-0007B8-W1; Mon, 31 Oct 2022 08:35:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opU0K-0004wd-N6 for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:35:00 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opU0J-0004bC-2U for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:35:00 -0400 Received: by mail-pg1-x535.google.com with SMTP id f9so10590328pgj.2 for ; Mon, 31 Oct 2022 05:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P72V6+Ir6tNrNqLeGOgeVfZ54cbK622H9TATsjqGOCc=; b=iQ/jMguTumKuX2/iqA6YN/fuHvpRY9zI10BZnwgEKTNWJQi7zUsuCxclFHMTekPioq qwK6nVNOrqnpAtHqngJOLHNjIWV+IkkRIAIKDaD/zAWr4hDU2SOg6G0moEoB7mK9W2cY u83qkpmgO5V1fjBUOydwJivin2F/O4c5HlAifuMAmQ+zHZq+hqoAaROtlVuQv6T3UO4v NiFuajjo/6YCQQ4F9tvM3KIBYcDqQcdYpeUUKptUBW3d/2hcB/bg5IZPMDU3hV+/B16N gn1QkBWugT+boeWche7PMkL96xfDKBBGxHxBLJDrI9dtcaxgZo6Ya1+rAeWxe4zrtyUY E3Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P72V6+Ir6tNrNqLeGOgeVfZ54cbK622H9TATsjqGOCc=; b=WUZpZ37t/4cBacJxUV+zurmM623oPNT3VXLktROx4x2wjHXsldlKHEvs15LPkEutH9 E8MXGafADp8uDFLogAl2kjtY+UK21W7RfxaY0nKh4HgmIqqcYRvRAcUhlihRxPr+0KjQ Dhy7IeS2B9Hs2iXyLABHFQUH9DxED1Ma4LsNgIznS2nEvcb+jrTf8qFVcuh+MfAkM/na nQ//uvE/HVMgak2tyUnOPbYDHMuD6dKrp+6Rau1WVc2jylH9aLCStRsR5508YTuwdWZl /YNFsCEam84I21Jbnhoifo5hoLTUcyWr1U7ZHes2lSqsN4wj5yZuh7OwjaJYUknGAQ9A 3cFQ== X-Gm-Message-State: ACrzQf18Vfu2UuSKwWUwGw74r5bOhnWW6vHgcr9heWsoG2fmd+T2P2Pq Z6Uiff3R+gzKZlf9N0oVV5iqdroRULEl8OD+ X-Google-Smtp-Source: AMsMyM4npOjRuRKHXLbNABQJ8LJCxDOZNOZ9qSXxWR5cO0NKzPlUJcJIvE46shahbl7O99MGlmvHeg== X-Received: by 2002:a05:6a00:174a:b0:562:781f:eca3 with SMTP id j10-20020a056a00174a00b00562781feca3mr13890168pfc.41.1667219697331; Mon, 31 Oct 2022 05:34:57 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:56 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 17/17] pci: Remove legacy errp from pci_add_capability Date: Mon, 31 Oct 2022 21:33:19 +0900 Message-Id: <20221031123319.21532-18-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::535; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Akihiko Odaki --- hw/pci/pci.c | 29 +++++++---------------------- include/hw/pci/pci.h | 12 ++---------- 2 files changed, 9 insertions(+), 32 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 8ee2171011..8ff71e4553 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2513,38 +2513,23 @@ static void pci_del_option_rom(PCIDevice *pdev) } /* - * On success, pci_add_capability_legacy() returns a positive value - * that the offset of the pci capability. - * On failure, it sets an error and returns a negative error - * code. + * pci_add_capability() returns a positive value that the offset of the pci + * capability. */ -int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp) +uint8_t pci_add_capability(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size) { uint8_t *config; - int i, overlapping_cap; + int i; if (!offset) { offset = pci_find_space(pdev, size); /* out of PCI config space is programming error */ assert(offset); } else { - /* Verify that capabilities don't overlap. Note: device assignment - * depends on this check to verify that the device is not broken. - * Should never trigger for emulated devices, but it's helpful - * for debugging these. */ + /* Verify that capabilities don't overlap. */ for (i = offset; i < offset + size; i++) { - overlapping_cap = pci_find_capability_at_offset(pdev, i); - if (overlapping_cap) { - error_setg(errp, "%s:%02x:%02x.%x " - "Attempt to add PCI capability %x at offset " - "%x overlaps existing capability %x at offset %x", - pci_root_bus_path(pdev), pci_dev_bus_num(pdev), - PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), - cap_id, offset, overlapping_cap, i); - return -EINVAL; - } + assert(!pci_find_capability_at_offset(pdev, i)); } } diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 51fd106f16..2a5d4b329f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -2,7 +2,6 @@ #define QEMU_PCI_H #include "exec/memory.h" -#include "qapi/error.h" #include "sysemu/dma.h" /* PCI includes legacy ISA access. */ @@ -391,15 +390,8 @@ void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, void pci_unregister_vga(PCIDevice *pci_dev); pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); -int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp); - -#define PCI_ADD_CAPABILITY_VA(pdev, cap_id, offset, size, errp, ...) \ - pci_add_capability_legacy(pdev, cap_id, offset, size, errp) - -#define pci_add_capability(...) \ - PCI_ADD_CAPABILITY_VA(__VA_ARGS__, &error_abort) +uint8_t pci_add_capability(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size); void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);