From patchwork Wed Nov 2 16:13:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Usama Arif X-Patchwork-Id: 13028544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E2CEC433FE for ; Wed, 2 Nov 2022 16:20:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231616AbiKBQUo (ORCPT ); Wed, 2 Nov 2022 12:20:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231301AbiKBQU0 (ORCPT ); Wed, 2 Nov 2022 12:20:26 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65F5530F41 for ; Wed, 2 Nov 2022 09:14:49 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id i5-20020a1c3b05000000b003cf47dcd316so1595215wma.4 for ; Wed, 02 Nov 2022 09:14:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZXj/+tvutn9072ZUAQ/Fj8mIysO5PQhhp6FCeEN8Zrw=; b=A1TppZwD1Iw4IiArSoEXOboBO1payKvnhkZBo3OOtZHRLZ4/rXNVt6HQfaMag0SB3I o7IG79mBlebjo+m4QnYUOSccej3xGTMo2gfsJxfeykR32qFtNfnKcKC/xBPaneuroKb1 FZmHjMcT+hD//AuJYINwjZTuxoioQ+LfktSZbFrIy8ZZbm0bZt1wYOF6wRd7RphI1kmt 2xqKYWexAvzjDguIaLOmSDiOSrsYLM4XEGpfZzTZO4lq9uDHcZIq0T6w+mgWVR4gjLOD JVRPHC8kAAdfUu+ij3PWrhXEBc5OiM6ZdIrP/JUKHIaVIJoX2aguWijsZNu16WKRGULF HxRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZXj/+tvutn9072ZUAQ/Fj8mIysO5PQhhp6FCeEN8Zrw=; b=7PUGFLRQwtO16pCQlgjzEu4746uG/CsEy1CsUi1g/XLiPI/fycmobiSPyVMR/on0ns QaLcWfIcXjLvyROjUGkbaIHvRx8pJ7ZNNggDbaWxSx5ZRY3xwXmMOUFfogscj4mSrSz0 sj1fmLxpo1YUPhqDHnfL2/HyfBOMRnj/tGRe2oLMvm9UTheTmoLyUtyNoGzCteHkaOhq FoA/wB4QF6y1BZ6UAvOMWEUz+kFO/WF1r5HYunTYr1zlfHCfpvp0DcR/JgrNaLPpklFi U7v1sV5/ANy2b3HbeTFhX8Y9SZeqJwMxWXt0Td0q1jO1Ahx8RWA/nroY5fHzR/gBmaeE oqYQ== X-Gm-Message-State: ACrzQf3CIhc+fDEY8eyuz4yLihVqzOOEg9soMso5rKEpgsFt0mlZkazg 99+iCzjWNxmHAbjgMCNu3QfkPg== X-Google-Smtp-Source: AMsMyM7qHohe8t2aLsIgDI8jervh0lNgxUy3saJvw7Yjrle9KJulmdFLIMMRUOI9RkGHuYDYlrh0IQ== X-Received: by 2002:a05:600c:4313:b0:3cf:894d:1d05 with SMTP id p19-20020a05600c431300b003cf894d1d05mr896047wme.32.1667405659085; Wed, 02 Nov 2022 09:14:19 -0700 (PDT) Received: from usaari01.cust.communityfibre.co.uk ([2a02:6b6a:b4d7:0:6a08:9b26:ab04:7065]) by smtp.gmail.com with ESMTPSA id m17-20020a5d56d1000000b0022cc6b8df5esm13230923wrw.7.2022.11.02.09.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 09:14:18 -0700 (PDT) From: Usama Arif To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-doc@vger.kernel.org, virtualization@lists.linux-foundation.org, linux@armlinux.org.uk, yezengruan@huawei.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, steven.price@arm.com, mark.rutland@arm.com Cc: fam.zheng@bytedance.com, liangma@liangbit.com, punit.agrawal@bytedance.com, Usama Arif Subject: [RFC 1/6] KVM: arm64: Document PV-lock interface Date: Wed, 2 Nov 2022 16:13:35 +0000 Message-Id: <20221102161340.2982090-2-usama.arif@bytedance.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102161340.2982090-1-usama.arif@bytedance.com> References: <20221102161340.2982090-1-usama.arif@bytedance.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce a paravirtualization interface for KVM/arm64 to obtain whether the VCPU is currently running or not. The PV lock structure of the guest is allocated by user space. A hypercall interface is provided for the guest to interrogate the hypervisor's support for this interface and the location of the shared memory structures. Signed-off-by: Zengruan Ye Signed-off-by: Usama Arif --- Documentation/virt/kvm/arm/pvlock.rst | 64 +++++++++++++++++++++++++ Documentation/virt/kvm/devices/vcpu.rst | 23 +++++++++ 2 files changed, 87 insertions(+) create mode 100644 Documentation/virt/kvm/arm/pvlock.rst diff --git a/Documentation/virt/kvm/arm/pvlock.rst b/Documentation/virt/kvm/arm/pvlock.rst new file mode 100644 index 000000000000..766aeef50b2d --- /dev/null +++ b/Documentation/virt/kvm/arm/pvlock.rst @@ -0,0 +1,64 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Paravirtualized lock support for arm64 +====================================== + +KVM/arm64 provides hypervisor service calls for paravirtualized guests to check +whether a VCPU is currently running or not. + +Two new SMCCC compatible hypercalls are defined: + +* PV_LOCK_FEATURES: 0xC6000020 +* PV_LOCK_PREEMPTED: 0xC6000021 + +The existence of the PV_LOCK hypercall should be probed using the SMCCC 1.1 +ARCH_FEATURES mechanism before calling it. + +PV_LOCK_FEATURES + ============= ======== ========== + Function ID: (uint32) 0xC6000020 + PV_call_id: (uint32) The function to query for support. + Currently only PV_LOCK_PREEMPTED is supported. + Return value: (int64) NOT_SUPPORTED (-1) or SUCCESS (0) if the relevant + PV-lock feature is supported by the hypervisor. + ============= ======== ========== + +PV_LOCK_PREEMPTED + ============= ======== ========== + Function ID: (uint32) 0xC6000021 + Return value: (int64) IPA of the pv lock data structure for this + VCPU. On failure: + NOT_SUPPORTED (-1) + ============= ======== ========== + +The IPA returned by PV_LOCK_PREEMPTED should be mapped by the guest as normal +memory with inner and outer write back caching attributes, in the inner +shareable domain. + +PV_LOCK_PREEMPTED returns the structure for the calling VCPU. + +PV lock state +------------- + +The structure pointed to by the PV_LOCK_PREEMPTED hypercall is as follows: + ++-----------+-------------+-------------+---------------------------------+ +| Field | Byte Length | Byte Offset | Description | ++===========+=============+=============+=================================+ +| preempted | 8 | 0 | Indicate if the VCPU that owns | +| | | | this struct is running or not. | +| | | | Non-zero values mean the VCPU | +| | | | has been preempted. Zero means | +| | | | the VCPU is not preempted. | ++-----------+-------------+-------------+---------------------------------+ + +The preempted field will be updated to 1 by the hypervisor prior to scheduling +a VCPU. When the VCPU is scheduled out, the preempted field will be updated +to 0 by the hypervisor. + +The structure will be present within a reserved region of the normal memory +given to the guest. The guest should not attempt to write into this memory. +There is a structure per VCPU of the guest. + +For the user space interface see Documentation/virt/kvm/devices/vcpu.rst +section "4. GROUP: KVM_ARM_VCPU_PVLOCK_CTRL". diff --git a/Documentation/virt/kvm/devices/vcpu.rst b/Documentation/virt/kvm/devices/vcpu.rst index 716aa3edae14..223ac2fe62f0 100644 --- a/Documentation/virt/kvm/devices/vcpu.rst +++ b/Documentation/virt/kvm/devices/vcpu.rst @@ -263,3 +263,26 @@ From the destination VMM process: 7. Write the KVM_VCPU_TSC_OFFSET attribute for every vCPU with the respective value derived in the previous step. + +5. GROUP: KVM_ARM_VCPU_PVLOCK_CTRL +================================== + +:Architectures: ARM64 + +5.1 ATTRIBUTE: KVM_ARM_VCPU_PVLOCK_IPA +-------------------------------------- + +:Parameters: 64-bit base address + +Returns: + + ======= ====================================== + -ENXIO PV lock not implemented + -EEXIST Base address already set for this VCPU + -EINVAL Base address not 64 byte aligned + ======= ====================================== + +Specifies the base address of the pv lock structure for this VCPU. The +base address must be 64 byte aligned and exist within a valid guest memory +region. See Documentation/virt/kvm/arm/pvlock.rst for more information +including the layout of the pv lock structure. From patchwork Wed Nov 2 16:13:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Usama Arif X-Patchwork-Id: 13028543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AE79C43217 for ; Wed, 2 Nov 2022 16:20:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231611AbiKBQUn (ORCPT ); Wed, 2 Nov 2022 12:20:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231290AbiKBQUZ (ORCPT ); Wed, 2 Nov 2022 12:20:25 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D34B2D768 for ; Wed, 2 Nov 2022 09:14:50 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id bk15so25227683wrb.13 for ; Wed, 02 Nov 2022 09:14:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r6tj+7sNHNnTbkzs8ZeKL5miL5fHgtHHC3d2WQTSFbE=; b=KuAbtL9XTBizhGI/s9UKTASCs9n5mCuzpUBAjDKPpPPbTBikgNbBtzoyDhdJz3rdNU mmnuIzpAEBxAKkL+DSU3LgSNMu7c5yAJmdwZrv3aqDlQYsO7Ila4V+71ZfNrywCdFHeQ qz+K94xhrzF57uJqLYDnlI27OVmAWXosKtVna3HQNbDzOffVPx8/KVkDFCHIYs+85RoB 2pIindGfcIhgS8XCYFTKhsqqN5wJwSPlJEbGfiTQOJ2fr0OI9nBwpHz9KNF4c4QZfMYH 1imRxckHe24zPJoQfARJnpU3RhMO+dr1NG35zgb/SwU0IahY+x1Gdzd60NEOPYSKZ5Il VTRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r6tj+7sNHNnTbkzs8ZeKL5miL5fHgtHHC3d2WQTSFbE=; b=2w0nsj80sEjKhBnnxEhEtWrozqHjUcZ1T3yISr1OgxMAz4c9zL3w1a0D4ag7loTGpp /tHj3MdM1K24CnT5/0EDRgn7cpkmeNGd8Akmmrr/WtCGqAko19SujV1BSl0h48fyXBiS aYWU3hQHxWd9iZIXy9l/rvmkGyhwHPLEfmZbtSSDa5PdO506VDKUqjNWV7lLxTdcv46/ FV3GXNxN7vuJncjc7tIH/UsHSofUIliyICs/cegdug0o2quJQLZC8Ou5LU/WCAjP09ME M+bHWgyoDXqBQJukA42bGsLyrSC/KsjgcQ150CtPqsrhbyMMCBt5ysC/3rbbHT92CTtd QcAA== X-Gm-Message-State: ACrzQf28NN89YeOO/xhAHihHQdo9cE71DU4pgEfjsAvtcGmwKVTgzUtz 3vjao5MexZxOwcq+7qvZkO01bA== X-Google-Smtp-Source: AMsMyM7D3GBwOzz5QAuoLmf+oB2TmG0p9ILQukZoZQKCpczeNQrlwRKtrJtUrLcSObIcUbD2rOZ3WQ== X-Received: by 2002:a5d:5410:0:b0:236:fe1:bb74 with SMTP id g16-20020a5d5410000000b002360fe1bb74mr15694845wrv.512.1667405660181; Wed, 02 Nov 2022 09:14:20 -0700 (PDT) Received: from usaari01.cust.communityfibre.co.uk ([2a02:6b6a:b4d7:0:6a08:9b26:ab04:7065]) by smtp.gmail.com with ESMTPSA id m17-20020a5d56d1000000b0022cc6b8df5esm13230923wrw.7.2022.11.02.09.14.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 09:14:19 -0700 (PDT) From: Usama Arif To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-doc@vger.kernel.org, virtualization@lists.linux-foundation.org, linux@armlinux.org.uk, yezengruan@huawei.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, steven.price@arm.com, mark.rutland@arm.com Cc: fam.zheng@bytedance.com, liangma@liangbit.com, punit.agrawal@bytedance.com, Usama Arif Subject: [RFC 2/6] KVM: arm64: Add SMCCC paravirtualised lock calls Date: Wed, 2 Nov 2022 16:13:36 +0000 Message-Id: <20221102161340.2982090-3-usama.arif@bytedance.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102161340.2982090-1-usama.arif@bytedance.com> References: <20221102161340.2982090-1-usama.arif@bytedance.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add two new SMCCC compatible hypercalls for PV lock features: PV_LOCK_FEATURES: 0xC6000020 PV_LOCK_PREEMPTED: 0xC6000021 Also add the header file which defines the ABI for the paravirtualized lock features we're about to add. Signed-off-by: Zengruan Ye Signed-off-by: Usama Arif --- arch/arm64/include/asm/pvlock-abi.h | 17 +++++++++++++++++ include/linux/arm-smccc.h | 13 +++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 arch/arm64/include/asm/pvlock-abi.h diff --git a/arch/arm64/include/asm/pvlock-abi.h b/arch/arm64/include/asm/pvlock-abi.h new file mode 100644 index 000000000000..3f4574071679 --- /dev/null +++ b/arch/arm64/include/asm/pvlock-abi.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright(c) 2019 Huawei Technologies Co., Ltd + * Author: Zengruan Ye + * Usama Arif + */ + +#ifndef __ASM_PVLOCK_ABI_H +#define __ASM_PVLOCK_ABI_H + +struct pvlock_vcpu_state { + __le64 preempted; + /* Structure must be 64 byte aligned, pad to that size */ + u8 padding[56]; +} __packed; + +#endif diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 220c8c60e021..6360333e0f64 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -151,6 +151,19 @@ ARM_SMCCC_OWNER_STANDARD_HYP, \ 0x21) +/* Paravirtualised lock calls */ +#define ARM_SMCCC_HV_PV_LOCK_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_VENDOR_HYP, \ + 0x20) + +#define ARM_SMCCC_HV_PV_LOCK_PREEMPTED \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_VENDOR_HYP, \ + 0x21) + /* TRNG entropy source calls (defined by ARM DEN0098) */ #define ARM_SMCCC_TRNG_VERSION \ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ From patchwork Wed Nov 2 16:13:37 2022 Content-Type: text/plain; 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Wed, 02 Nov 2022 09:14:20 -0700 (PDT) Received: from usaari01.cust.communityfibre.co.uk ([2a02:6b6a:b4d7:0:6a08:9b26:ab04:7065]) by smtp.gmail.com with ESMTPSA id m17-20020a5d56d1000000b0022cc6b8df5esm13230923wrw.7.2022.11.02.09.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 09:14:20 -0700 (PDT) From: Usama Arif To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-doc@vger.kernel.org, virtualization@lists.linux-foundation.org, linux@armlinux.org.uk, yezengruan@huawei.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, steven.price@arm.com, mark.rutland@arm.com Cc: fam.zheng@bytedance.com, liangma@liangbit.com, punit.agrawal@bytedance.com, Usama Arif Subject: [RFC 3/6] KVM: arm64: Support pvlock preempted via shared structure Date: Wed, 2 Nov 2022 16:13:37 +0000 Message-Id: <20221102161340.2982090-4-usama.arif@bytedance.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102161340.2982090-1-usama.arif@bytedance.com> References: <20221102161340.2982090-1-usama.arif@bytedance.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Implement the service call for configuring a shared structure between a VCPU and the hypervisor in which the hypervisor can tell whether the VCPU is running or not. The preempted field is zero if the VCPU is not preempted. Any other value means the VCPU has been preempted. Signed-off-by: Zengruan Ye Signed-off-by: Usama Arif --- Documentation/virt/kvm/arm/hypercalls.rst | 3 ++ arch/arm64/include/asm/kvm_host.h | 18 ++++++++++ arch/arm64/include/uapi/asm/kvm.h | 1 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/arm.c | 8 +++++ arch/arm64/kvm/hypercalls.c | 36 +++++++++++++++++++ arch/arm64/kvm/pvlock.c | 43 +++++++++++++++++++++++ arch/arm64/kvm/pvtime.c | 16 --------- tools/arch/arm64/include/uapi/asm/kvm.h | 1 + tools/include/linux/arm-smccc.h | 13 +++++++ 10 files changed, 124 insertions(+), 17 deletions(-) create mode 100644 arch/arm64/kvm/pvlock.c diff --git a/Documentation/virt/kvm/arm/hypercalls.rst b/Documentation/virt/kvm/arm/hypercalls.rst index 3e23084644ba..872a16226ace 100644 --- a/Documentation/virt/kvm/arm/hypercalls.rst +++ b/Documentation/virt/kvm/arm/hypercalls.rst @@ -127,6 +127,9 @@ The pseudo-firmware bitmap register are as follows: Bit-1: KVM_REG_ARM_VENDOR_HYP_BIT_PTP: The bit represents the Precision Time Protocol KVM service. + Bit-2: KVM_REG_ARM_VENDOR_HYP_BIT_PV_LOCK: + The bit represents the Paravirtualized lock service. + Errors: ======= ============================================================= diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 45e2136322ba..18303b30b7e9 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -417,6 +417,11 @@ struct kvm_vcpu_arch { u64 last_steal; gpa_t base; } steal; + + /* Guest PV lock state */ + struct { + gpa_t base; + } pv; }; /* @@ -840,6 +845,19 @@ static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) return (vcpu_arch->steal.base != GPA_INVALID); } +static inline void kvm_arm_pvlock_preempted_init(struct kvm_vcpu_arch *vcpu_arch) +{ + vcpu_arch->pv.base = GPA_INVALID; +} + +static inline bool kvm_arm_is_pvlock_preempted_ready(struct kvm_vcpu_arch *vcpu_arch) +{ + return (vcpu_arch->pv.base != GPA_INVALID); +} + +gpa_t kvm_init_pvlock(struct kvm_vcpu *vcpu); +void kvm_update_pvlock_preempted(struct kvm_vcpu *vcpu, u64 preempted); + void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index 316917b98707..bd05ece5c590 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -365,6 +365,7 @@ enum { enum { KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0, KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1, + KVM_REG_ARM_VENDOR_HYP_BIT_PV_LOCK = 2, #ifdef __KERNEL__ KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT, #endif diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 5e33c2d4645a..e1f711885916 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -10,7 +10,7 @@ include $(srctree)/virt/kvm/Makefile.kvm obj-$(CONFIG_KVM) += kvm.o obj-$(CONFIG_KVM) += hyp/ -kvm-y += arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \ +kvm-y += arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o pvlock.o \ inject_fault.o va_layout.o handle_exit.o \ guest.o debug.o reset.o sys_regs.o stacktrace.o \ vgic-sys-reg-v3.o fpsimd.o pkvm.o \ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 94d33e296e10..73da4ac859fd 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -345,6 +345,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) kvm_arm_pvtime_vcpu_init(&vcpu->arch); + kvm_arm_pvlock_preempted_init(&vcpu->arch); + vcpu->arch.hw_mmu = &vcpu->kvm->arch.mmu; err = kvm_vgic_vcpu_init(vcpu); @@ -420,6 +422,10 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) if (vcpu_has_ptrauth(vcpu)) vcpu_ptrauth_disable(vcpu); + + if (kvm_arm_is_pvlock_preempted_ready(&vcpu->arch)) + kvm_update_pvlock_preempted(vcpu, 0); + kvm_arch_vcpu_load_debug_state_flags(vcpu); if (!cpumask_test_cpu(smp_processor_id(), vcpu->kvm->arch.supported_cpus)) @@ -433,6 +439,8 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) if (has_vhe()) kvm_vcpu_put_sysregs_vhe(vcpu); kvm_timer_vcpu_put(vcpu); + if (kvm_arm_is_pvlock_preempted_ready(&vcpu->arch)) + kvm_update_pvlock_preempted(vcpu, 1); kvm_vgic_put(vcpu); kvm_vcpu_pmu_restore_host(vcpu); kvm_arm_vmid_clear_active(); diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index c9f401fa01a9..263500c4f20e 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -93,6 +93,27 @@ static bool kvm_hvc_call_default_allowed(u32 func_id) } } +long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu) +{ + u32 feature = smccc_get_arg1(vcpu); + long val = SMCCC_RET_NOT_SUPPORTED; + + switch (feature) { + case ARM_SMCCC_HV_PV_TIME_FEATURES: + case ARM_SMCCC_HV_PV_TIME_ST: + if (vcpu->arch.steal.base != GPA_INVALID) + val = SMCCC_RET_SUCCESS; + break; + case ARM_SMCCC_HV_PV_LOCK_FEATURES: + case ARM_SMCCC_HV_PV_LOCK_PREEMPTED: + if (vcpu->arch.pv.base != GPA_INVALID) + val = SMCCC_RET_SUCCESS; + break; + } + + return val; +} + static bool kvm_hvc_call_allowed(struct kvm_vcpu *vcpu, u32 func_id) { struct kvm_smccc_features *smccc_feat = &vcpu->kvm->arch.smccc_feat; @@ -109,6 +130,10 @@ static bool kvm_hvc_call_allowed(struct kvm_vcpu *vcpu, u32 func_id) case ARM_SMCCC_HV_PV_TIME_ST: return test_bit(KVM_REG_ARM_STD_HYP_BIT_PV_TIME, &smccc_feat->std_hyp_bmap); + case ARM_SMCCC_HV_PV_LOCK_FEATURES: + case ARM_SMCCC_HV_PV_LOCK_PREEMPTED: + return test_bit(KVM_REG_ARM_VENDOR_HYP_BIT_PV_LOCK, + &smccc_feat->vendor_hyp_bmap); case ARM_SMCCC_VENDOR_HYP_KVM_FEATURES_FUNC_ID: case ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID: return test_bit(KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT, @@ -191,9 +216,15 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) &smccc_feat->std_hyp_bmap)) val[0] = SMCCC_RET_SUCCESS; break; + case ARM_SMCCC_HV_PV_LOCK_FEATURES: + if (test_bit(KVM_REG_ARM_VENDOR_HYP_BIT_PV_LOCK, + &smccc_feat->vendor_hyp_bmap)) + val[0] = SMCCC_RET_SUCCESS; + break; } break; case ARM_SMCCC_HV_PV_TIME_FEATURES: + case ARM_SMCCC_HV_PV_LOCK_FEATURES: val[0] = kvm_hypercall_pv_features(vcpu); break; case ARM_SMCCC_HV_PV_TIME_ST: @@ -201,6 +232,11 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu) if (gpa != GPA_INVALID) val[0] = gpa; break; + case ARM_SMCCC_HV_PV_LOCK_PREEMPTED: + gpa = kvm_init_pvlock(vcpu); + if (gpa != GPA_INVALID) + val[0] = gpa; + break; case ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID: val[0] = ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_0; val[1] = ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_1; diff --git a/arch/arm64/kvm/pvlock.c b/arch/arm64/kvm/pvlock.c new file mode 100644 index 000000000000..3eb35ab31481 --- /dev/null +++ b/arch/arm64/kvm/pvlock.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright(c) 2019 Huawei Technologies Co., Ltd + * Author: Zengruan Ye + * Usama Arif + */ + +#include +#include + +#include + +#include + +gpa_t kvm_init_pvlock(struct kvm_vcpu *vcpu) +{ + struct pvlock_vcpu_state init_values = {}; + struct kvm *kvm = vcpu->kvm; + u64 base = vcpu->arch.pv.base; + int idx; + + if (base == GPA_INVALID) + return base; + + idx = srcu_read_lock(&kvm->srcu); + kvm_write_guest(kvm, base, &init_values, sizeof(init_values)); + srcu_read_unlock(&kvm->srcu, idx); + + return base; +} + +void kvm_update_pvlock_preempted(struct kvm_vcpu *vcpu, u64 preempted) +{ + int idx; + u64 offset; + struct kvm *kvm = vcpu->kvm; + u64 base = vcpu->arch.pv.base; + + idx = srcu_read_lock(&kvm->srcu); + offset = offsetof(struct pvlock_vcpu_state, preempted); + kvm_put_guest(kvm, base + offset, cpu_to_le64(preempted)); + srcu_read_unlock(&kvm->srcu, idx); +} diff --git a/arch/arm64/kvm/pvtime.c b/arch/arm64/kvm/pvtime.c index 78a09f7a6637..ab130f02cdc6 100644 --- a/arch/arm64/kvm/pvtime.c +++ b/arch/arm64/kvm/pvtime.c @@ -32,22 +32,6 @@ void kvm_update_stolen_time(struct kvm_vcpu *vcpu) srcu_read_unlock(&kvm->srcu, idx); } -long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu) -{ - u32 feature = smccc_get_arg1(vcpu); - long val = SMCCC_RET_NOT_SUPPORTED; - - switch (feature) { - case ARM_SMCCC_HV_PV_TIME_FEATURES: - case ARM_SMCCC_HV_PV_TIME_ST: - if (vcpu->arch.steal.base != GPA_INVALID) - val = SMCCC_RET_SUCCESS; - break; - } - - return val; -} - gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu) { struct pvclock_vcpu_stolen_time init_values = {}; diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h b/tools/arch/arm64/include/uapi/asm/kvm.h index 316917b98707..bd05ece5c590 100644 --- a/tools/arch/arm64/include/uapi/asm/kvm.h +++ b/tools/arch/arm64/include/uapi/asm/kvm.h @@ -365,6 +365,7 @@ enum { enum { KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0, KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1, + KVM_REG_ARM_VENDOR_HYP_BIT_PV_LOCK = 2, #ifdef __KERNEL__ KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT, #endif diff --git a/tools/include/linux/arm-smccc.h b/tools/include/linux/arm-smccc.h index 63ce9bebccd3..82b4fd050dd7 100644 --- a/tools/include/linux/arm-smccc.h +++ b/tools/include/linux/arm-smccc.h @@ -150,6 +150,19 @@ ARM_SMCCC_OWNER_STANDARD_HYP, \ 0x21) +/* Paravirtualised lock calls */ +#define ARM_SMCCC_HV_PV_LOCK_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_VENDOR_HYP, \ + 0x20) + +#define ARM_SMCCC_HV_PV_LOCK_PREEMPTED \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64, \ + ARM_SMCCC_OWNER_VENDOR_HYP, \ + 0x21) + /* TRNG entropy source calls (defined by ARM DEN0098) */ #define ARM_SMCCC_TRNG_VERSION \ ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ From patchwork Wed Nov 2 16:13:38 2022 Content-Type: text/plain; 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Wed, 02 Nov 2022 09:14:21 -0700 (PDT) Received: from usaari01.cust.communityfibre.co.uk ([2a02:6b6a:b4d7:0:6a08:9b26:ab04:7065]) by smtp.gmail.com with ESMTPSA id m17-20020a5d56d1000000b0022cc6b8df5esm13230923wrw.7.2022.11.02.09.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 09:14:21 -0700 (PDT) From: Usama Arif To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-doc@vger.kernel.org, virtualization@lists.linux-foundation.org, linux@armlinux.org.uk, yezengruan@huawei.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, steven.price@arm.com, mark.rutland@arm.com Cc: fam.zheng@bytedance.com, liangma@liangbit.com, punit.agrawal@bytedance.com, Usama Arif Subject: [RFC 4/6] KVM: arm64: Provide VCPU attributes for PV lock Date: Wed, 2 Nov 2022 16:13:38 +0000 Message-Id: <20221102161340.2982090-5-usama.arif@bytedance.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102161340.2982090-1-usama.arif@bytedance.com> References: <20221102161340.2982090-1-usama.arif@bytedance.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Allow user space to inform the KVM host where in the physical memory map the paravirtualized lock structures should be located. User space can set an attribute on the VCPU providing the IPA base address of the PV lock structure for that VCPU. This must be repeated for every VCPU in the VM. The address is given in terms of the physical address visible to the guest and must be 64 byte aligned. The guest will discover the address via a hypercall. Signed-off-by: Zengruan Ye Signed-off-by: Usama Arif --- arch/arm64/include/asm/kvm_host.h | 7 ++++ arch/arm64/include/uapi/asm/kvm.h | 2 ++ arch/arm64/kvm/guest.c | 9 +++++ arch/arm64/kvm/pvlock.c | 57 +++++++++++++++++++++++++++++++ include/uapi/linux/kvm.h | 2 ++ 5 files changed, 77 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 18303b30b7e9..86aeca8a4393 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -829,6 +829,13 @@ int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *attr); +int kvm_arm_pvlock_set_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); +int kvm_arm_pvlock_get_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); +int kvm_arm_pvlock_has_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr); + extern unsigned int kvm_arm_vmid_bits; int kvm_arm_vmid_alloc_init(void); void kvm_arm_vmid_alloc_free(void); diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index bd05ece5c590..71010bacaaab 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -412,6 +412,8 @@ enum { #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 #define KVM_ARM_VCPU_PVTIME_CTRL 2 #define KVM_ARM_VCPU_PVTIME_IPA 0 +#define KVM_ARM_VCPU_PVLOCK_CTRL 3 +#define KVM_ARM_VCPU_PVLOCK_IPA 0 /* KVM_IRQ_LINE irq field index values */ #define KVM_ARM_IRQ_VCPU2_SHIFT 28 diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 2ff13a3f8479..7e765e3256ef 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -959,6 +959,9 @@ int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_set_attr(vcpu, attr); break; + case KVM_ARM_VCPU_PVLOCK_CTRL: + ret = kvm_arm_pvlock_set_attr(vcpu, attr); + break; default: ret = -ENXIO; break; @@ -982,6 +985,9 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_get_attr(vcpu, attr); break; + case KVM_ARM_VCPU_PVLOCK_CTRL: + ret = kvm_arm_pvlock_get_attr(vcpu, attr); + break; default: ret = -ENXIO; break; @@ -1005,6 +1011,9 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, case KVM_ARM_VCPU_PVTIME_CTRL: ret = kvm_arm_pvtime_has_attr(vcpu, attr); break; + case KVM_ARM_VCPU_PVLOCK_CTRL: + ret = kvm_arm_pvlock_has_attr(vcpu, attr); + break; default: ret = -ENXIO; break; diff --git a/arch/arm64/kvm/pvlock.c b/arch/arm64/kvm/pvlock.c index 3eb35ab31481..b08a287a4811 100644 --- a/arch/arm64/kvm/pvlock.c +++ b/arch/arm64/kvm/pvlock.c @@ -41,3 +41,60 @@ void kvm_update_pvlock_preempted(struct kvm_vcpu *vcpu, u64 preempted) kvm_put_guest(kvm, base + offset, cpu_to_le64(preempted)); srcu_read_unlock(&kvm->srcu, idx); } + +int kvm_arm_pvlock_set_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + u64 __user *user = (u64 __user *)attr->addr; + struct kvm *kvm = vcpu->kvm; + u64 ipa; + int ret = 0; + int idx; + + if (attr->attr != KVM_ARM_VCPU_PVLOCK_IPA) + return -ENXIO; + + if (get_user(ipa, user)) + return -EFAULT; + if (!IS_ALIGNED(ipa, 64)) + return -EINVAL; + if (vcpu->arch.pv.base != GPA_INVALID) + return -EEXIST; + + /* Check the address is in a valid memslot */ + idx = srcu_read_lock(&kvm->srcu); + if (kvm_is_error_hva(gfn_to_hva(kvm, ipa >> PAGE_SHIFT))) + ret = -EINVAL; + srcu_read_unlock(&kvm->srcu, idx); + + if (!ret) + vcpu->arch.pv.base = ipa; + + return ret; +} + +int kvm_arm_pvlock_get_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + u64 __user *user = (u64 __user *)attr->addr; + u64 ipa; + + if (attr->attr != KVM_ARM_VCPU_PVLOCK_IPA) + return -ENXIO; + + ipa = vcpu->arch.pv.base; + + if (put_user(ipa, user)) + return -EFAULT; + return 0; +} + +int kvm_arm_pvlock_has_attr(struct kvm_vcpu *vcpu, + struct kvm_device_attr *attr) +{ + switch (attr->attr) { + case KVM_ARM_VCPU_PVLOCK_IPA: + return 0; + } + return -ENXIO; +} \ No newline at end of file diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 0d5d4419139a..1fe3cce5c84a 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1429,6 +1429,8 @@ enum kvm_device_type { #define KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_ARM_PV_TIME, #define KVM_DEV_TYPE_ARM_PV_TIME KVM_DEV_TYPE_ARM_PV_TIME + KVM_DEV_TYPE_ARM_PV_LOCK, +#define KVM_DEV_TYPE_ARM_PV_LOCK KVM_DEV_TYPE_ARM_PV_LOCK KVM_DEV_TYPE_MAX, }; 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Wed, 02 Nov 2022 09:14:23 -0700 (PDT) Received: from usaari01.cust.communityfibre.co.uk ([2a02:6b6a:b4d7:0:6a08:9b26:ab04:7065]) by smtp.gmail.com with ESMTPSA id m17-20020a5d56d1000000b0022cc6b8df5esm13230923wrw.7.2022.11.02.09.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Nov 2022 09:14:22 -0700 (PDT) From: Usama Arif To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-doc@vger.kernel.org, virtualization@lists.linux-foundation.org, linux@armlinux.org.uk, yezengruan@huawei.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, steven.price@arm.com, mark.rutland@arm.com Cc: fam.zheng@bytedance.com, liangma@liangbit.com, punit.agrawal@bytedance.com, Usama Arif Subject: [RFC 5/6] KVM: arm64: Support the VCPU preemption check Date: Wed, 2 Nov 2022 16:13:39 +0000 Message-Id: <20221102161340.2982090-6-usama.arif@bytedance.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102161340.2982090-1-usama.arif@bytedance.com> References: <20221102161340.2982090-1-usama.arif@bytedance.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Support the vcpu_is_preempted() functionality under KVM/arm64. This will enhance lock performance on overcommitted hosts (more runnable VCPUs than physical CPUs in the system) as doing busy waits for preempted VCPUs will hurt system performance far worse than early yielding. Signed-off-by: Zengruan Ye Signed-off-by: Usama Arif --- arch/arm64/include/asm/paravirt.h | 2 + arch/arm64/include/asm/spinlock.h | 16 +++- arch/arm64/kernel/paravirt.c | 126 ++++++++++++++++++++++++++++++ arch/arm64/kernel/setup.c | 3 + include/linux/cpuhotplug.h | 1 + 5 files changed, 147 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/paravirt.h b/arch/arm64/include/asm/paravirt.h index 9aa193e0e8f2..4ccb4356c56b 100644 --- a/arch/arm64/include/asm/paravirt.h +++ b/arch/arm64/include/asm/paravirt.h @@ -19,10 +19,12 @@ static inline u64 paravirt_steal_clock(int cpu) } int __init pv_time_init(void); +int __init pv_lock_init(void); #else #define pv_time_init() do {} while (0) +#define pv_lock_init() do {} while (0) #endif // CONFIG_PARAVIRT diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h index 0525c0b089ed..7023efa4de96 100644 --- a/arch/arm64/include/asm/spinlock.h +++ b/arch/arm64/include/asm/spinlock.h @@ -10,7 +10,20 @@ /* See include/linux/spinlock.h */ #define smp_mb__after_spinlock() smp_mb() +#define vcpu_is_preempted vcpu_is_preempted + +#ifdef CONFIG_PARAVIRT +#include + +bool dummy_vcpu_is_preempted(int cpu); +DECLARE_STATIC_CALL(pv_vcpu_is_preempted, dummy_vcpu_is_preempted); +static inline bool vcpu_is_preempted(int cpu) +{ + return static_call(pv_vcpu_is_preempted)(cpu); +} + +#else /* * Changing this will break osq_lock() thanks to the call inside * smp_cond_load_relaxed(). @@ -18,10 +31,11 @@ * See: * https://lore.kernel.org/lkml/20200110100612.GC2827@hirez.programming.kicks-ass.net */ -#define vcpu_is_preempted vcpu_is_preempted static inline bool vcpu_is_preempted(int cpu) { return false; } +#endif /* CONFIG_PARAVIRT */ + #endif /* __ASM_SPINLOCK_H */ diff --git a/arch/arm64/kernel/paravirt.c b/arch/arm64/kernel/paravirt.c index 57c7c211f8c7..45bcca87bed7 100644 --- a/arch/arm64/kernel/paravirt.c +++ b/arch/arm64/kernel/paravirt.c @@ -22,6 +22,7 @@ #include #include +#include #include struct static_key paravirt_steal_enabled; @@ -38,7 +39,12 @@ struct pv_time_stolen_time_region { struct pvclock_vcpu_stolen_time __rcu *kaddr; }; +struct pv_lock_state_region { + struct pvlock_vcpu_state __rcu *kaddr; +}; + static DEFINE_PER_CPU(struct pv_time_stolen_time_region, stolen_time_region); +static DEFINE_PER_CPU(struct pv_lock_state_region, lock_state_region); static bool steal_acc = true; static int __init parse_no_stealacc(char *arg) @@ -178,3 +184,123 @@ int __init pv_time_init(void) return 0; } + +static bool native_vcpu_is_preempted(int cpu) +{ + return false; +} + +DEFINE_STATIC_CALL(pv_vcpu_is_preempted, native_vcpu_is_preempted); + +static bool para_vcpu_is_preempted(int cpu) +{ + struct pv_lock_state_region *reg; + __le64 preempted_le; + + reg = per_cpu_ptr(&lock_state_region, cpu); + if (!reg->kaddr) { + pr_warn_once("PV lock enabled but not configured for cpu %d\n", + cpu); + return false; + } + + preempted_le = le64_to_cpu(READ_ONCE(reg->kaddr->preempted)); + + return !!(preempted_le); +} + +static int pvlock_vcpu_state_dying_cpu(unsigned int cpu) +{ + struct pv_lock_state_region *reg; + + reg = this_cpu_ptr(&lock_state_region); + if (!reg->kaddr) + return 0; + + memunmap(reg->kaddr); + memset(reg, 0, sizeof(*reg)); + + return 0; +} + +static int init_pvlock_vcpu_state(unsigned int cpu) +{ + struct pv_lock_state_region *reg; + struct arm_smccc_res res; + + reg = this_cpu_ptr(&lock_state_region); + + arm_smccc_1_1_invoke(ARM_SMCCC_HV_PV_LOCK_PREEMPTED, &res); + + if (res.a0 == SMCCC_RET_NOT_SUPPORTED) { + pr_warn("Failed to init PV lock data structure\n"); + return -EINVAL; + } + + reg->kaddr = memremap(res.a0, + sizeof(struct pvlock_vcpu_state), + MEMREMAP_WB); + + if (!reg->kaddr) { + pr_warn("Failed to map PV lock data structure\n"); + return -ENOMEM; + } + + return 0; +} + +static int kvm_arm_init_pvlock(void) +{ + int ret; + + ret = cpuhp_setup_state(CPUHP_AP_ARM_KVM_PVLOCK_STARTING, + "hypervisor/arm/pvlock:starting", + init_pvlock_vcpu_state, + pvlock_vcpu_state_dying_cpu); + if (ret < 0) { + pr_warn("PV-lock init failed\n"); + return ret; + } + + return 0; +} + +static bool has_kvm_pvlock(void) +{ + struct arm_smccc_res res; + + /* To detect the presence of PV lock support we require SMCCC 1.1+ */ + if (arm_smccc_1_1_get_conduit() == SMCCC_CONDUIT_NONE) + return false; + + arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_HV_PV_LOCK_FEATURES, &res); + + if (res.a0 != SMCCC_RET_SUCCESS) + return false; + + arm_smccc_1_1_invoke(ARM_SMCCC_HV_PV_LOCK_FEATURES, + ARM_SMCCC_HV_PV_LOCK_PREEMPTED, &res); + + return (res.a0 == SMCCC_RET_SUCCESS); +} + +int __init pv_lock_init(void) +{ + int ret; + + if (is_hyp_mode_available()) + return 0; + + if (!has_kvm_pvlock()) + return 0; + + ret = kvm_arm_init_pvlock(); + if (ret) + return ret; + + static_call_update(pv_vcpu_is_preempted, para_vcpu_is_preempted); + pr_info("using PV-lock preempted\n"); + + return 0; +} \ No newline at end of file diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index fea3223704b6..05ca07ac5800 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include #include @@ -360,6 +361,8 @@ void __init __no_sanitize_address setup_arch(char **cmdline_p) smp_init_cpus(); smp_build_mpidr_hash(); + pv_lock_init(); + /* Init percpu seeds for random tags after cpus are set up. */ kasan_init_sw_tags(); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index f61447913db9..c0ee11855c73 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -192,6 +192,7 @@ enum cpuhp_state { /* Must be the last timer callback */ CPUHP_AP_DUMMY_TIMER_STARTING, CPUHP_AP_ARM_XEN_STARTING, + CPUHP_AP_ARM_KVM_PVLOCK_STARTING, CPUHP_AP_ARM_CORESIGHT_STARTING, CPUHP_AP_ARM_CORESIGHT_CTI_STARTING, CPUHP_AP_ARM64_ISNDEP_STARTING, From patchwork Wed Nov 2 16:13:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Usama Arif X-Patchwork-Id: 13028548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30F26C4332F for ; Wed, 2 Nov 2022 16:21:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231696AbiKBQVP (ORCPT ); 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Wed, 02 Nov 2022 09:14:24 -0700 (PDT) From: Usama Arif To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-doc@vger.kernel.org, virtualization@lists.linux-foundation.org, linux@armlinux.org.uk, yezengruan@huawei.com, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, steven.price@arm.com, mark.rutland@arm.com Cc: fam.zheng@bytedance.com, liangma@liangbit.com, punit.agrawal@bytedance.com, Usama Arif Subject: [RFC 6/6] KVM: selftests: add tests for PV time specific hypercalls Date: Wed, 2 Nov 2022 16:13:40 +0000 Message-Id: <20221102161340.2982090-7-usama.arif@bytedance.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102161340.2982090-1-usama.arif@bytedance.com> References: <20221102161340.2982090-1-usama.arif@bytedance.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org These are vendor specific hypercalls. Signed-off-by: Usama Arif --- tools/testing/selftests/kvm/aarch64/hypercalls.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/testing/selftests/kvm/aarch64/hypercalls.c b/tools/testing/selftests/kvm/aarch64/hypercalls.c index a39da3fe4952..743ee6cb97d8 100644 --- a/tools/testing/selftests/kvm/aarch64/hypercalls.c +++ b/tools/testing/selftests/kvm/aarch64/hypercalls.c @@ -79,6 +79,8 @@ static const struct test_hvc_info hvc_info[] = { ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID), TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID, 0), TEST_HVC_INFO(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID, KVM_PTP_VIRT_COUNTER), + TEST_HVC_INFO(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, ARM_SMCCC_HV_PV_LOCK_FEATURES), + TEST_HVC_INFO(ARM_SMCCC_HV_PV_LOCK_FEATURES, ARM_SMCCC_HV_PV_LOCK_PREEMPTED), }; /* Feed false hypercall info to test the KVM behavior */