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Mon, 21 Jan 2019 02:06:21 -0800 (PST) Received: from dogfood.home ([2a01:cb1d:112:6f00:789e:cc70:7004:686b]) by smtp.gmail.com with ESMTPSA id f22sm4541857wmj.26.2019.01.21.02.06.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Jan 2019 02:06:20 -0800 (PST) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86 Date: Mon, 21 Jan 2019 11:06:17 +0100 Message-Id: <20190121100617.2311-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190121_020623_827240_C0342346 X-CRM114-Status: GOOD ( 16.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Will Deacon , David Zhou , Maxime Ripard , Benjamin Herrenschmidt , Ard Biesheuvel , David Airlie , Maarten Lankhorst , Michel Daenzer , linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, Junwei Zhang , Huang Rui , dri-devel@lists.freedesktop.org, Daniel Vetter , Michael Ellerman , Alex Deucher , Sean Paul , Christian Koenig MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Currently, the DRM code assumes that PCI devices are always cache coherent for DMA, and that this can be selectively overridden for some buffers using non-cached mappings on the CPU side and PCIe NoSnoop transactions on the bus side. Whether the NoSnoop part is implemented correctly is highly platform specific. Whether it /matters/ if NoSnoop is implemented correctly or not is architecture specific: on x86, such transactions are coherent with the CPU whether the NoSnoop attribute is honored or not. On other architectures, it depends on whether such transactions may allocate in caches that are non-coherent with the CPU's uncached mappings. Bottom line is that we should not rely on this optimization to work correctly for cache coherent devices in the general case. On the other hand, disabling this optimization for non-coherent devices is likely to cause breakage as well, since the driver will assume cache coherent PCIe if this optimization is turned off. So rename drm_arch_can_wc_memory() to drm_device_can_wc_memory(), and pass the drm_device pointer into it so we can base the return value on whether the device is cache coherent or not if not running on X86. Cc: Christian Koenig Cc: Alex Deucher Cc: David Zhou Cc: Huang Rui Cc: Junwei Zhang Cc: Michel Daenzer Cc: David Airlie Cc: Daniel Vetter Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Sean Paul Cc: Michael Ellerman Cc: Benjamin Herrenschmidt Cc: Will Deacon Reported-by: Carsten Haitzler Signed-off-by: Ard Biesheuvel --- This is a followup to '[RFC PATCH] drm/ttm: force cached mappings for system RAM on ARM' https://lore.kernel.org/linux-arm-kernel/20190110072841.3283-1-ard.biesheuvel@linaro.org/ Without t drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/radeon/radeon_object.c | 2 +- include/drm/drm_cache.h | 19 +++++++++++-------- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 728e15e5d68a..777fa251838f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -480,7 +480,7 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, /* For architectures that don't support WC memory, * mask out the WC flag from the BO */ - if (!drm_arch_can_wc_memory()) + if (!drm_device_can_wc_memory(adev->ddev)) bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; #endif diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index 833e909706a9..610889bf6ab5 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -249,7 +249,7 @@ int radeon_bo_create(struct radeon_device *rdev, /* For architectures that don't support WC memory, * mask out the WC flag from the BO */ - if (!drm_arch_can_wc_memory()) + if (!drm_device_can_wc_memory(rdev->ddev)) bo->flags &= ~RADEON_GEM_GTT_WC; #endif diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h index bfe1639df02d..ced63b1207a3 100644 --- a/include/drm/drm_cache.h +++ b/include/drm/drm_cache.h @@ -33,6 +33,8 @@ #ifndef _DRM_CACHE_H_ #define _DRM_CACHE_H_ +#include +#include #include void drm_clflush_pages(struct page *pages[], unsigned long num_pages); @@ -41,15 +43,16 @@ void drm_clflush_virt_range(void *addr, unsigned long length); u64 drm_get_max_iomem(void); -static inline bool drm_arch_can_wc_memory(void) +static inline bool drm_device_can_wc_memory(struct drm_device *ddev) { -#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) - return false; -#elif defined(CONFIG_MIPS) && defined(CONFIG_CPU_LOONGSON3) - return false; -#else - return true; -#endif + if (IS_ENABLED(CONFIG_PPC)) + return IS_ENABLED(CONFIG_NOT_COHERENT_CACHE); + else if (IS_ENABLED(CONFIG_MIPS)) + return !IS_ENABLED(CONFIG_CPU_LOONGSON3); + else if (IS_ENABLED(CONFIG_X86)) + return true; + + return !dev_is_dma_coherent(ddev->dev); } #endif