From patchwork Thu Nov 3 18:20:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13030819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A992AC43217 for ; Thu, 3 Nov 2022 18:21:19 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 88C02E0F; Thu, 3 Nov 2022 19:20:27 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 88C02E0F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1667499677; bh=7kexx5aSRDT78KBP5AfTUKfmCOUdDakZgxwkDab2+gs=; h=From:To:Subject:Date:Cc:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From; b=KZdasVq6aMkanUreo4Z4gZLjynGJWtK9UlymX5jGLQ0KRb6ZI7berwuTGHOCALHZ2 FFzRNZFakXdJVjyMh100LbFQw3hqax2SEQ7SZ+qJt6VcS/1UFrpioNNd6e5p6VRU5G aNA2KhdS/7PA6mAsexWQg56oucvwDSJF9PkF/f1g= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 29B5BF8051C; Thu, 3 Nov 2022 19:20:27 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id E8646F8051E; Thu, 3 Nov 2022 19:20:25 +0100 (CET) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 20485F801D5 for ; Thu, 3 Nov 2022 19:20:22 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 20485F801D5 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="ab735NtM" Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 2849683F4E; Thu, 3 Nov 2022 19:20:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1667499622; bh=n51u6LhFoceBViiV5/DmLIF5y/lACNEMtpDmoM1ErXc=; h=From:To:Cc:Subject:Date:From; b=ab735NtMzRYBxdhstvZORIGr01mtOwOhEMCz8Fbz1ff9sJNKPBqQapxV2fcrsxNcD wynSaiiR5UCr+ZM5qJys8B/3J45OoKAJwNgGO0YDgasAY4w7IpyCSr9IxLugN83WJ2 0snxXbTsquw91C7WccW3Wxs3ZiFGBqblgP0337LlLL2eXsde4bsqXU4MGvpY2H8uyZ jokf3H8NLVisfOIPYY/lCpxjvnTi8GuK7dZBJospVxIcASonniORmYtaKCN2TUx3Wh BeuVICOP7ABTqPrDiy6DbJW5giqa1h0YYibKE+x6tvsaZCHNzc3vkW86kixk20hkGf ikvGff5Udw8cA== From: Marek Vasut To: devicetree@vger.kernel.org Subject: [PATCH] ASoC: dt-bindings: fsl-sai: Convert to YAML DT schema Date: Thu, 3 Nov 2022 19:20:16 +0100 Message-Id: <20221103182016.95808-1-marex@denx.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Cc: Marek Vasut , alsa-devel@alsa-project.org, Xiubo Li , Shengjiu Wang , Takashi Iwai , Liam Girdwood , Rob Herring , Nicolin Chen , Mark Brown , Krzysztof Kozlowski , Fabio Estevam X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Convert the SAI bindings to YAML DT schema to permit validation. Add Shengjiu as maintainer, derived from sound/soc/fsl/fsl_sai.c get_maintainer result. Describe existing used combinations of compatible strings, add the missing imx7d-sai compatible string which is used on i.MX7 . Properties lsb-first, fsl,sai-synchronous-rx, fsl,sai-asynchronous, fsl,dataline are no longer listed as required, since those are clearly optional, even the description says so, so does their usage. Fix the undefined edma channel macro per arch/arm/boot/dts/vfxxx.dtsi , use the value itself just like in the vfxxx.dtsi . Document interrupts property, which was previously undocumented, but it is required property of this IP. Document #sound-sai-cells, which should be zero for this IP. Document fsl,imx6ul-iomuxc-gpr and its dependency on MX6UL and fsl,sai-mclk-direction-output . Signed-off-by: Marek Vasut --- Cc: Fabio Estevam Cc: Jaroslav Kysela Cc: Krzysztof Kozlowski Cc: Liam Girdwood Cc: Mark Brown Cc: Nicolin Chen Cc: Rob Herring Cc: Shengjiu Wang Cc: Takashi Iwai Cc: Xiubo Li Cc: alsa-devel@alsa-project.org To: devicetree@vger.kernel.org --- .../devicetree/bindings/sound/fsl-sai.yaml | 188 ++++++++++++++++++ 1 file changed, 188 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/fsl-sai.yaml diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.yaml b/Documentation/devicetree/bindings/sound/fsl-sai.yaml new file mode 100644 index 0000000000000..e6620a127f419 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl-sai.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/fsl-sai.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Synchronous Audio Interface (SAI). + +maintainers: + - Shengjiu Wang + +description: + The SAI is based on I2S module that used communicating with audio + codecs, which provides a synchronous audio interface that supports + fullduplex serial interfaces with frame synchronization such as I2S, + AC97, TDM, and codec/DSP interfaces. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx6ul-sai + - fsl,imx7d-sai + - const: fsl,imx6sx-sai + + - items: + - enum: + - fsl,imx8mm-sai + - fsl,imx8mn-sai + - fsl,imx8mp-sai + - const: fsl,imx8mq-sai + + - items: + - enum: + - fsl,imx6sx-sai + - fsl,imx7ulp-sai + - fsl,imx8mq-sai + - fsl,imx8qm-sai + - fsl,imx8ulp-sai + - fsl,vf610-sai + + reg: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 6 + + clock-names: + minItems: 4 + items: + - const: bus + - const: mclk1 + - const: mclk2 + - const: mclk3 + - const: pll8k + - const: pll11k + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + lsb-first: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Configures whether the LSB or the MSB is transmitted first for the + fifo data. If this property is absent, the MSB is transmitted first + as default, or the LSB is transmitted first. + + fsl,sai-synchronous-rx: + $ref: /schemas/types.yaml#/definitions/flag + description: | + This is a boolean property. If present, indicating that SAI will + work in the synchronous mode (sync Tx with Rx) which means both + the transmitter and the receiver will send and receive data by + following receiver's bit clocks and frame sync clocks. + If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are + absent, the default synchronous mode (sync Rx with Tx) will + be used, which means both transmitter and receiver will send + and receive data by following clocks of transmitter. + fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive. + + fsl,sai-asynchronous: + $ref: /schemas/types.yaml#/definitions/flag + description: | + If present, indicating that SAI will work in the asynchronous + mode, which means both transmitter and receiver will send and + receive data by following their own bit clocks and frame sync + clocks separately. + If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are + absent, the default synchronous mode (sync Rx with Tx) will + be used, which means both transmitter and receiver will send + and receive data by following clocks of transmitter. + fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive. + + fsl,dataline: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: | + Configure the dataline. It has 3 values for each configuration: + first one means the type: I2S(1) or PDM(2) + second one is dataline mask for 'rx' + third one is dataline mask for 'tx'. + for example: fsl,dataline = <1 0xff 0xff 2 0xff 0x11>; + means I2S type rx mask is 0xff, tx mask is 0xff, PDM type + rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). + + fsl,sai-mclk-direction-output: + $ref: /schemas/types.yaml#/definitions/flag + description: | + If present, indicates that SAI will output the SAI MCLK clock. + + fsl,imx6ul-iomuxc-gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to MX6UL IOMUXC GPR shared register file. + + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Required if all the SAI registers are big-endian rather + than little-endian. + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - dmas + - dma-names + - interrupts + +unevaluatedProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6ul-sai + then: + dependencies: + fsl,imx6ul-iomuxc-gpr: [ "fsl,sai-mclk-direction-output" ] + + - if: + not: + properties: + compatible: + contains: + enum: + - fsl,imx6ul-sai + - fsl,imx8mm-sai + - fsl,imx8mn-sai + - fsl,imx8mp-sai + - fsl,imx8mq-sai + then: + properties: + fsl,sai-mclk-direction-output: false + +examples: + - | + #include + #include + + sai@40031000 { + compatible = "fsl,vf610-sai"; + reg = <0x40031000 0x1000>; + interrupts = <86 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_1>; + clocks = <&clks VF610_CLK_PLATFORM_BUS>, <&clks VF610_CLK_SAI2>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 0 21>, <&edma0 0 20>; + big-endian; + lsb-first; + };