From patchwork Thu Nov 3 21:21:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13031037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57EE7C433FE for ; Thu, 3 Nov 2022 21:21:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231536AbiKCVVv (ORCPT ); Thu, 3 Nov 2022 17:21:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231545AbiKCVVr (ORCPT ); Thu, 3 Nov 2022 17:21:47 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F381321E34; Thu, 3 Nov 2022 14:21:42 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id bk15so4532239wrb.13; Thu, 03 Nov 2022 14:21:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=VIcm/SirnZMuA7oz66y5Oz4Q+8fuoc4tcWENPsKxvJU=; b=km90eVlRFFREd/Ht0TdeBdyFn7QERBsyBxvACAsXnW5BgsIndfPfk3IugX6Q2o8J9C ZS9QtORTcfsH6lV9aelKa9N8/6FaXuSrk+8AcGaysY2QGp8NC05x1nO6g+uNy1yLFAtL SzuzNw4wAaoCAZKFt7hpeY9tyH2H4BMnrYjLOZArOMJvGUu6sYt/ZgPIbY9c37UyCcPW ZlXllmPdx/FnnavTKRHzK19ib2uupuzalotJyCuybb9lO4w0AyNmbB7Elw3VmUsy0Yfy y1PNHGzZchJ5WM2d23hNDbk2mcv5TiFzbdYaHI0zXueNJJMprlVCJHKsDeyaQnBsnUNG IgmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=VIcm/SirnZMuA7oz66y5Oz4Q+8fuoc4tcWENPsKxvJU=; b=eyjLnMXZO2MU5SdsP4cHqBDKgYigDV+PvDNi6gooPbf2+zjnZDKQFBroC9HMbSMOcW C9z+KTkz70CZGPNfRVUHapUJTaqrx2ztkKlL/o9iZPVhsbsx/eGUjevktVgmbZZ4BEXu XQhC0a0iseE/5y5v+VLIeU6kYqldVL/anLrOuXsytWPQJR9dzsGiTH1OqF+xNFu3Z0Ej l8y/L/XrJ2mCe5/DWeHi5S1snZ/WcZGknxYl8p3T+k0hppq/szYuY4PYqVIH6Y7E3cQe V280RduzLPGo8NnE2wQgn0UKg60HCHR1A4U8QqNRZxmUDf7JNwUBfKPN8FtvP4Wwbl/6 5Upg== X-Gm-Message-State: ACrzQf2Wz55ZJGGr3HPMCxZw+cz6KzbcQx6SpDYIpVA8MqChafbHVTqE 031AYe3BygoJ8RrOJbU1qcY= X-Google-Smtp-Source: AMsMyM4Tc7NHZWTmPrJLUG4XIhrT0h6TeynUXjG6j3uBaakeeybFCdXAj7cn1BoDQg0XLzlwqOVi+w== X-Received: by 2002:a5d:4887:0:b0:226:ed34:7bbd with SMTP id g7-20020a5d4887000000b00226ed347bbdmr19529597wrq.561.1667510501178; Thu, 03 Nov 2022 14:21:41 -0700 (PDT) Received: from localhost.localdomain (93-42-71-18.ip85.fastwebnet.it. [93.42.71.18]) by smtp.googlemail.com with ESMTPSA id m29-20020a05600c3b1d00b003b47b913901sm6968320wms.1.2022.11.03.14.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 14:21:40 -0700 (PDT) From: Christian Marangi To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Kishon Vijay Abraham I , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: Christian Marangi , Robert Marko Subject: [PATCH 1/2] phy: qcom-qmp-pcie: split pcs_misc init cfg for ipq8074 pcs table Date: Thu, 3 Nov 2022 22:21:24 +0100 Message-Id: <20221103212125.17156-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Commit af6643242d3a ("phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3") reworked the pcs regs values and removed the 0x400 offset for each pcs_misc regs. This change caused the malfunction of ipq8074 downstream since it still has the legacy pcs table where pcs_misc are not placed on a different table and instead put together assuming the offset of 0x400 for the related pcs_misc regs. Split pcs_misc init cfg from the ipq8074 pcs init table to be handled correctly to prepare for actual support for gen3 pcie for ipq8074. Fixes: af6643242d3a ("phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3") Reported-by: Robert Marko Tested-by: Robert Marko Signed-off-by: Christian Marangi --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 7c81667dd968..d699fb4f7436 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -485,6 +485,13 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), +}; + +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), @@ -497,11 +504,7 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), }; static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { @@ -1506,6 +1509,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), .pcs = ipq8074_pcie_gen3_pcs_tbl, .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), + .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), }, .clk_list = ipq8074_pciephy_clk_l, .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), From patchwork Thu Nov 3 21:21:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13031038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC63CC4332F for ; Thu, 3 Nov 2022 21:22:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231539AbiKCVVw (ORCPT ); Thu, 3 Nov 2022 17:21:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231589AbiKCVVr (ORCPT ); Thu, 3 Nov 2022 17:21:47 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20DB921818; Thu, 3 Nov 2022 14:21:44 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id o30so1941775wms.2; Thu, 03 Nov 2022 14:21:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EBi1xTEb0SF667Jza54gm5V6cR58OHc1YhW84qRd8ZY=; b=pEpBEi9mvFUmu+V8wv+E4uWSllh8HKI11O/WhiLwohawSDkKp3f4WiHG8k6eFuQupN 1Fo8hWGbqymC4ZYnuLbxp1OwsD92umaBOaVFejXTmpHluITjQjDFKqsW/ODtfSY+jbUi fSYENdAOuVrOVUr5wX+IvPtt+B3ny1puRwGTi3dTukpwSm71z9rJZWiOMKpV9RZCMBZK tXi7iDW1ggE+JLPczofCGcUJ5IIB7EcmU+Yo7njOlXjg6kPRHxjurd7NIYTpsQDvSJNi aZn1cpJKIKi2sOoDYny5eCU6lu49qXlEOLMEw9dczZB17MHKx+M2NAZFyP0ejK4tGqiy J6wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EBi1xTEb0SF667Jza54gm5V6cR58OHc1YhW84qRd8ZY=; b=4b/tgToTjvL1mv3k8S83NI+jtDWDPFHm6myMTYSvqxi9cG2U6ow4wkaEhA2K5pFOOW W9da95S2nt1hbMCi14RcK4b/YZ/v/6ZLtgv4Zr0MxgSkuQ4xKm1PEdKRhCbazioa77Ap 1nHynZQ8fWKeAEz9yLQ330Go8mpAybNQuJ+6eX2SX738556/k+SMcvOd5TevJ5ZOLQOM e3bwP5r4ZJLGafsnwNc8sVxnNkDGrV2cWUpcbnU6N76dKDBhunlaHoxRyQwmXabaIhMF nrcGKnVeaeYDi+z0e16LYrG3aQONV3RbgSZdUaiNLUm5b+FsibtSwA+eFLShKpAj9THX 7IvA== X-Gm-Message-State: ACrzQf2gOMYy4wX/7JDJWK2FKwxFz+HSKWDvN8k3MlHMwmfqWhMIJnLv wFjxHjlwtyqhLUbv4/4bYI3CIKr/MXM= X-Google-Smtp-Source: AMsMyM5z2kO3XboxYINuKbpi6PqUYVuHI6ShBZBQbgTxcJLiIelbbB1yygyhNZLsHD0YytDk2cIUww== X-Received: by 2002:a05:600c:4486:b0:3cf:6e1d:f4a5 with SMTP id e6-20020a05600c448600b003cf6e1df4a5mr18119129wmo.85.1667510502516; Thu, 03 Nov 2022 14:21:42 -0700 (PDT) Received: from localhost.localdomain (93-42-71-18.ip85.fastwebnet.it. [93.42.71.18]) by smtp.googlemail.com with ESMTPSA id m29-20020a05600c3b1d00b003b47b913901sm6968320wms.1.2022.11.03.14.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Nov 2022 14:21:42 -0700 (PDT) From: Christian Marangi To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Kishon Vijay Abraham I , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Cc: Christian Marangi Subject: [PATCH 2/2] arm64: dts: qcom: ipq6018: improve pcie phy pcs reg table Date: Thu, 3 Nov 2022 22:21:25 +0100 Message-Id: <20221103212125.17156-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221103212125.17156-1-ansuelsmth@gmail.com> References: <20221103212125.17156-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This is not a fix on its own but more a cleanup. Phy qmp pcie driver currently have a workaround to handle pcs_misc not declared and add 0x400 offset to the pcs reg if pcs_misc is not declared. Correctly declare pcs_misc reg and reduce PCS size to the common value of 0x1f0 as done for every other qmp based pcie phy device. Signed-off-by: Christian Marangi Reviewed-by: Vinod Koul --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9ebb9e2371b1..95d7f49bc61a 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -406,7 +406,8 @@ pcie_phy: phy@84000 { pcie_phy0: phy@84200 { reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ - <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */ + <0x0 0x84800 0x0 0x1f0>; /* PCS: Lane0, COM, PCIE */ + <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */ #phy-cells = <0>; clocks = <&gcc GCC_PCIE0_PIPE_CLK>;