From patchwork Fri Nov 4 22:51:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13032680 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E4EAC43217 for ; Fri, 4 Nov 2022 22:52:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HkiJhfnyLA8AaVZg1/i4bXcFuoU2QyRaPdJ0j1ARo7w=; b=Q2y065/yqOfGvs r9Pbsq0LS+tmA1aDPl4wDLITo36XMJZzGjvob6G3YvsTPWIYwz9bcYU732GXedvhWJI2YgwQt6KJt 0Lc7SdUSBe4GR0aOA9z4c/Ji8ZWv+kgUZhVBLtu5dX+LuNFCp+nqmpOlkCKDHIZAfBlfECdoQoKd1 kMI7UNOJMsT136Kkoym+bR+qIUo6GG2/fJywuE8xmzuInSVfJLdxZmDjXUANkyBwGhvO9VBmS94gD prq4Zkizu+BBBgElhMVFGzK3Ypbsh2Ey6JfFTBFg+HRdnkd6QEgA2PIYBc5usxMLjk5xWSALPuqcK nfVtaEgC6UZAcfvztp6A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Xo-005QCy-2U; Fri, 04 Nov 2022 22:52:12 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Xl-005QAn-0d for linux-riscv@lists.infradead.org; Fri, 04 Nov 2022 22:52:10 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1or5Xg-0001sc-2O; Fri, 04 Nov 2022 23:52:04 +0100 From: Heiko Stuebner To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com, conor@kernel.org, philipp.tomsich@vrull.eu, Heiko Stuebner Subject: [PATCH RFC 1/9] string: allow override for strstarts() Date: Fri, 4 Nov 2022 23:51:45 +0100 Message-Id: <20221104225153.2710873-2-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104225153.2710873-1-heiko@sntech.de> References: <20221104225153.2710873-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_155209_069670_C02907BB X-CRM114-Status: UNSURE ( 9.84 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org In some special cases it may be necessary to also override the inline strstarts() function, so move the relevant #ifdef in place. Signed-off-by: Heiko Stuebner --- include/linux/string.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/string.h b/include/linux/string.h index cf7607b32102..2e5483238532 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -206,6 +206,7 @@ extern ssize_t memory_read_from_buffer(void *to, size_t count, loff_t *ppos, int ptr_to_hashval(const void *ptr, unsigned long *hashval_out); +#ifndef __HAVE_ARCH_STRSTARTS /** * strstarts - does @str start with @prefix? * @str: string to examine @@ -215,6 +216,7 @@ static inline bool strstarts(const char *str, const char *prefix) { return strncmp(str, prefix, strlen(prefix)) == 0; } +#endif size_t memweight(const void *ptr, size_t bytes); From patchwork Fri Nov 4 22:51:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13032683 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34D0EC43219 for ; Fri, 4 Nov 2022 22:52:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0+hOXZH64nZAPWe7vDjYwSzTlppkBWxcFDKo5mjg5+Y=; b=JpA8DOE7oiEcDm uQsfsndTGjakfr7jiOkJY2hooh7C4eVolgtjyzuWniZyVOIwoAX/uwxhblL46+Pqd3bJTU6BOOAuJ AmrUapx5bPAaLme1rTjvlm+cedbgDdbIxM7pNdI+73JcSNIuGxx8UDzng3ejHNILo9SNWb1M86RAI eVM/W+AyR/eDhhBicqAIC7/526RLf0FMFZf59p1iB1zJwp64sji69AYvJl3bwXvAc2j7ExqS0Xe4N h/AJNAKSQ2Zg6iDD1Cveo4bRXgLEuFArtPCijPgO7tEZZ2Q56udQZHsPeUfTCWdKixDu2toPdReyl 7TnTb3ABWFpNF8R75Wxg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Xs-005QEp-1o; Fri, 04 Nov 2022 22:52:16 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Xl-005QAq-Mw for linux-riscv@lists.infradead.org; Fri, 04 Nov 2022 22:52:11 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1or5Xg-0001sc-CK; Fri, 04 Nov 2022 23:52:04 +0100 From: Heiko Stuebner To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com, conor@kernel.org, philipp.tomsich@vrull.eu, Heiko Stuebner Subject: [PATCH RFC 2/9] efi/riscv: libstub: mark when compiling libstub Date: Fri, 4 Nov 2022 23:51:46 +0100 Message-Id: <20221104225153.2710873-3-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104225153.2710873-1-heiko@sntech.de> References: <20221104225153.2710873-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_155209_761226_FE1C059C X-CRM114-Status: GOOD ( 11.93 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We want to runtime-optimize some core functions (str*, mem*) but not have this leak into libstub. Instead libstub for the short while it's running should just use the generic implementation. To be able to determine whether functions are getting compiled as part of libstub or not, add a compile-flag we can check via #ifdef. Signed-off-by: Heiko Stuebner --- drivers/firmware/efi/libstub/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile index b1601aad7e1a..39c8e3da1937 100644 --- a/drivers/firmware/efi/libstub/Makefile +++ b/drivers/firmware/efi/libstub/Makefile @@ -25,7 +25,7 @@ cflags-$(CONFIG_ARM) := $(subst $(CC_FLAGS_FTRACE),,$(KBUILD_CFLAGS)) \ -fno-builtin -fpic \ $(call cc-option,-mno-single-pic-base) cflags-$(CONFIG_RISCV) := $(subst $(CC_FLAGS_FTRACE),,$(KBUILD_CFLAGS)) \ - -fpic + -fpic -DRISCV_EFISTUB cflags-$(CONFIG_LOONGARCH) := $(subst $(CC_FLAGS_FTRACE),,$(KBUILD_CFLAGS)) \ -fpie From patchwork Fri Nov 4 22:51:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13032679 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A06FCC433FE for ; Fri, 4 Nov 2022 22:52:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Ucxf9stpp+ZKf8VcY4AxmMngMybkZlMc6FxLnGu4KVc=; b=5CahAuG8bshYf9 HOd6QL8XN4bFN7fJcvFDxU3RRO2Q+Wlg/m5GJKy/k2eek1ktyeercrc4THdl/PVK0TNdkOqCRPPip ZJOVKPXJyIT16IUBotvS6tPONe3vx3XDzprjVG/l6QeORBXLXNiZZdQoQ5oxFuOsy127Gq71X7k9D 8+26Qj/faz9jDtY7x3uzb2ke2luW4bg0Wy/Gf5Mjt9dJ2OJs1XVRuahjth6QE1+mVKSCRDumGnWXQ hPN0BsUB2yVejQW46HoVJAX29x1ZxtZVlDjdvyDbdPBeimgvShwMocQWQKTjtFUm4KzreZhYwx4s0 CkQVPWkXFkNs0x1tI/Uw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Xp-005QDb-HG; Fri, 04 Nov 2022 22:52:13 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Xl-005QAr-6S for linux-riscv@lists.infradead.org; Fri, 04 Nov 2022 22:52:10 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1or5Xg-0001sc-Lz; Fri, 04 Nov 2022 23:52:04 +0100 From: Heiko Stuebner To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com, conor@kernel.org, philipp.tomsich@vrull.eu, Heiko Stuebner Subject: [PATCH RFC 3/9] RISC-V: add auipc elements to parse_asm header Date: Fri, 4 Nov 2022 23:51:47 +0100 Message-Id: <20221104225153.2710873-4-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104225153.2710873-1-heiko@sntech.de> References: <20221104225153.2710873-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_155209_247297_B675795A X-CRM114-Status: UNSURE ( 9.37 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We will want to use the opcode parsing outside kdb as well and need at least the auipc element there. Signed-off-by: Heiko Stuebner --- arch/riscv/include/asm/parse_asm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/parse_asm.h b/arch/riscv/include/asm/parse_asm.h index f36368de839f..c287c1426aa7 100644 --- a/arch/riscv/include/asm/parse_asm.h +++ b/arch/riscv/include/asm/parse_asm.h @@ -100,6 +100,7 @@ #define RVC_C2_RD_OPOFF 7 /* parts of opcode for RVG*/ +#define OPCODE_AUIPC 0x17 #define OPCODE_BRANCH 0x63 #define OPCODE_JALR 0x67 #define OPCODE_JAL 0x6f @@ -129,6 +130,7 @@ #define FUNCT12_SRET 0x10200000 +#define MATCH_AUIPC (OPCODE_AUIPC) #define MATCH_JALR (FUNCT3_JALR | OPCODE_JALR) #define MATCH_JAL (OPCODE_JAL) #define MATCH_BEQ (FUNCT3_BEQ | OPCODE_BRANCH) @@ -145,6 +147,7 @@ #define MATCH_C_JR (FUNCT4_C_JR | OPCODE_C_2) #define MATCH_C_JALR (FUNCT4_C_JALR | OPCODE_C_2) +#define MASK_AUIPC 0x7f #define MASK_JALR 0x707f #define MASK_JAL 0x7f #define MASK_C_JALR 0xf07f From patchwork Fri Nov 4 22:51:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13032687 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56048C4332F for ; Fri, 4 Nov 2022 22:52:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jG3zLHe0kgnJWSJIQnnI0LceWJyfX0aMT7/YgmY57LI=; b=Va+T+dTjjPAlOL ZgeyOGpQQfwDkozYgDHc3OLOybQO61plGNN1T69S8mKIVKidOxXoHcpHIfvrquPn7dBmSZluD59lR j2yNqV19jsIFYshRIUq5Jz/OaeLc3stepWYMNFOyUZluEGf1D63g8w4hcMZSBote71zzphl3LNXPu DEEHMHDwgOLDUkLupP5hsASa7sSFcpa+2HmrXhavCX3/A9rtoS1scIXN/G4xhgB8vP7j7iXvelvcv GSuuWV37AaBbxl6ZqYz9lM113UxSWfdnSqxwPG6V6SHzb5uftrhm6Oe/8hfzBVGyLgKDBF0862g4R nEHvZmkB+qOAckVOzcGA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Y0-005QJR-By; Fri, 04 Nov 2022 22:52:24 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Xr-005QAu-4j for linux-riscv@lists.infradead.org; Fri, 04 Nov 2022 22:52:16 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1or5Xg-0001sc-WC; Fri, 04 Nov 2022 23:52:05 +0100 From: Heiko Stuebner To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com, conor@kernel.org, philipp.tomsich@vrull.eu, Heiko Stuebner Subject: [PATCH RFC 4/9] RISC-V: add U-type imm parsing to parse_asm header Date: Fri, 4 Nov 2022 23:51:48 +0100 Message-Id: <20221104225153.2710873-5-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104225153.2710873-1-heiko@sntech.de> References: <20221104225153.2710873-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_155215_207628_4AB14F16 X-CRM114-Status: GOOD ( 12.25 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Similar to other existing types, allow extracting the immediate for a U-type instruction. U-type immediates are special in that regard, that the value in the instruction in bits [31:12] already represents the same bits of the immediate, so no shifting is required. Signed-off-by: Heiko Stuebner --- arch/riscv/include/asm/parse_asm.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/include/asm/parse_asm.h b/arch/riscv/include/asm/parse_asm.h index c287c1426aa7..939ede0ee527 100644 --- a/arch/riscv/include/asm/parse_asm.h +++ b/arch/riscv/include/asm/parse_asm.h @@ -25,6 +25,15 @@ #define J_IMM_11_MASK GENMASK(0, 0) #define J_IMM_19_12_MASK GENMASK(7, 0) +/* + * U-type IMMs contain the upper 20bits [31:20] of an immediate with + * the rest filled in by zeros, so no shifting required. Similarly, + * bit31 contains the signed state, so no sign extension necessary. + */ +#define U_IMM_SIGN_OPOFF 31 +#define U_IMM_31_12_OPOFF 0 +#define U_IMM_31_12_MASK GENMASK(31, 12) + /* The bit field of immediate value in B-type instruction */ #define B_IMM_SIGN_OPOFF 31 #define B_IMM_10_5_OPOFF 25 @@ -183,6 +192,10 @@ static inline bool is_ ## INSN_NAME ## _insn(long insn) \ #define RV_X(X, s, mask) (((X) >> (s)) & (mask)) #define RVC_X(X, s, mask) RV_X(X, s, mask) +#define EXTRACT_UTYPE_IMM(x) \ + ({typeof(x) x_ = (x); \ + (RV_X(x_, U_IMM_31_12_OPOFF, U_IMM_31_12_MASK)); }) + #define EXTRACT_JTYPE_IMM(x) \ ({typeof(x) x_ = (x); \ (RV_X(x_, J_IMM_10_1_OPOFF, J_IMM_10_1_MASK) << J_IMM_10_1_OFF) | \ From patchwork Fri Nov 4 22:51:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13032681 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DBFAC433FE for ; Fri, 4 Nov 2022 22:52:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=E5hVO6e7fIUEwYW1YEGkGyNsxgZof35KmCaZoMCY900=; b=gYkd+XG+Mhbb0i 8BX99u9uxn5vmjF85+ZkvdkFCMgcge/fAsVC+hclrhYr6fll0QVnps8fgJWSvyoVhfBHWP0qVMKzN uuWmas9DnGtxBK/816jKi6iCwlXOofqOSqsjvAWJ9oM83XmoxCmbZpjSOs/4T4xlapQste5Oz659n lxxv7Vc1/Z4/USILlqmXZT29vFt8e9mVF4m9Aoj5V7MHtcvBuBVAR3kagtGoQbroEK1FZ509BhMr6 zUe///liXG6wBQCyIInNkzInL1lLyPYd8babfA/wp5qZA0mEaNhrjvx/fRcB9tHQHhcg7e0yvFLq1 KH3+VilxYLzViV3MU1Xw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Xq-005QE7-MC; Fri, 04 Nov 2022 22:52:14 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Xl-005QAv-FL for linux-riscv@lists.infradead.org; Fri, 04 Nov 2022 22:52:11 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1or5Xh-0001sc-9r; Fri, 04 Nov 2022 23:52:05 +0100 From: Heiko Stuebner To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com, conor@kernel.org, philipp.tomsich@vrull.eu, Heiko Stuebner Subject: [PATCH RFC 5/9] RISC-V: add rd reg parsing to parse_asm header Date: Fri, 4 Nov 2022 23:51:49 +0100 Message-Id: <20221104225153.2710873-6-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104225153.2710873-1-heiko@sntech.de> References: <20221104225153.2710873-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_155209_526331_4C6F794B X-CRM114-Status: UNSURE ( 9.90 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add a macro to allow parsing of the rd register from an instruction. Signed-off-by: Heiko Stuebner --- arch/riscv/include/asm/parse_asm.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/parse_asm.h b/arch/riscv/include/asm/parse_asm.h index 939ede0ee527..305b15f7d41c 100644 --- a/arch/riscv/include/asm/parse_asm.h +++ b/arch/riscv/include/asm/parse_asm.h @@ -51,6 +51,7 @@ #define RVG_RS1_OPOFF 15 #define RVG_RS2_OPOFF 20 #define RVG_RD_OPOFF 7 +#define RVG_RD_MASK GENMASK(4, 0) /* The bit field of immediate value in RVC J instruction */ #define RVC_J_IMM_SIGN_OPOFF 12 @@ -192,6 +193,10 @@ static inline bool is_ ## INSN_NAME ## _insn(long insn) \ #define RV_X(X, s, mask) (((X) >> (s)) & (mask)) #define RVC_X(X, s, mask) RV_X(X, s, mask) +#define EXTRACT_RD_REG(x) \ + ({typeof(x) x_ = (x); \ + (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); }) + #define EXTRACT_UTYPE_IMM(x) \ ({typeof(x) x_ = (x); \ (RV_X(x_, U_IMM_31_12_OPOFF, U_IMM_31_12_MASK)); }) From patchwork Fri Nov 4 22:51:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13032682 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9E8DC4332F for ; Fri, 4 Nov 2022 22:52:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=UR9+bY1bxOFXbPDM8AFwB4UV2JaT23qz4m5FM6usFZc=; b=3zlKhipTFHkZ6Z AAwDv4sX26aowuW5JhBKOoO4y9PK90E4yt8FPMcQ12lKIwBz7nBBy0qu/VXfxyNN1ucZn2yhp1stj ETWkVT411xUD34OgbS8mY29Gs75JunwI0fyQvHVcZ2G6UDwuCEjEqyCiPSHvrWj6gIJ2260rijImv NitnUfo76DI3FEFzgrf0DqYAcho72agmzCOopqvBBvykPGZnAwFRhjYbdWAnByQ2FZYXLX9vsFkGl Hm1pyN7gA+1hJLEz68QqwJTsJ//3tgfELSMUL2uMXxddIuJREKFciB82kbhDFZf8gamX7dADat6eq 02tNRIvMYqfifm4mKJIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Xt-005QFG-7a; Fri, 04 Nov 2022 22:52:17 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1or5Xn-005QB4-1E for linux-riscv@lists.infradead.org; Fri, 04 Nov 2022 22:52:12 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1or5Xh-0001sc-Jv; Fri, 04 Nov 2022 23:52:05 +0100 From: Heiko Stuebner To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com, conor@kernel.org, philipp.tomsich@vrull.eu, Heiko Stuebner Subject: [PATCH RFC 6/9] RISC-V: fix auipc-jalr addresses in patched alternatives Date: Fri, 4 Nov 2022 23:51:50 +0100 Message-Id: <20221104225153.2710873-7-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104225153.2710873-1-heiko@sntech.de> References: <20221104225153.2710873-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_155211_087472_B30D8F52 X-CRM114-Status: GOOD ( 17.20 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Alternatives live in a different section, so addresses used by call functions will point to wrong locations after the patch got applied. Similar to arm64, adjust the location to consider that offset. Signed-off-by: Heiko Stuebner --- arch/riscv/kernel/cpufeature.c | 78 +++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 694267d1fe81..22f3453d6db8 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -298,6 +298,73 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage) return cpu_req_feature; } +#include + +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) + +static inline bool is_auipc_jalr_pair(long insn1, long insn2) +{ + return is_auipc_insn(insn1) && is_jalr_insn(insn2); +} + +#define JALR_SIGN_MASK BIT(I_IMM_SIGN_OPOFF - I_IMM_11_0_OPOFF) +#define JALR_OFFSET_MASK I_IMM_11_0_MASK +#define AUIPC_OFFSET_MASK U_IMM_31_12_MASK +#define AUIPC_PAD (0x00001000) +#define JALR_SHIFT I_IMM_11_0_OPOFF + +#define to_jalr_imm(offset) \ + ((offset & I_IMM_11_0_MASK) << I_IMM_11_0_OPOFF) + +#define to_auipc_imm(offset) \ + ((offset & JALR_SIGN_MASK) ? \ + ((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) : \ + (offset & AUIPC_OFFSET_MASK)) + +static void riscv_alternative_fix_auipc_jalr(unsigned int *alt_ptr, unsigned int len, int patch_offset) +{ + int num_instr = len / sizeof(u32); + unsigned int call[2]; + int i; + int imm1; + u32 rd1; + + for (i = 0; i < num_instr; i++) { + /* is there a further instruction? */ + if (i + 1 >= num_instr) + continue; + + if (!is_auipc_jalr_pair(*(alt_ptr + i), *(alt_ptr + i + 1))) + continue; + + /* call will use ra register */ + rd1 = EXTRACT_RD_REG(*(alt_ptr + i)); + if (rd1 != 1) + continue; + + /* get and adjust new target address */ + imm1 = EXTRACT_UTYPE_IMM(*(alt_ptr + i)); + imm1 += EXTRACT_ITYPE_IMM(*(alt_ptr + i + 1)); + imm1 -= patch_offset; + + /* pick the original auipc + jalr */ + call[0] = *(alt_ptr + i); + call[1] = *(alt_ptr + i + 1); + + /* drop the old IMMs */ + call[0] &= ~(U_IMM_31_12_MASK); + call[1] &= ~(I_IMM_11_0_MASK << I_IMM_11_0_OPOFF); + + /* add the adapted IMMs */ + call[0] |= to_auipc_imm(imm1); + call[1] |= to_jalr_imm(imm1); + + /* patch the call place again */ + patch_text_nosync(alt_ptr + i * sizeof(u32), call, 8); + } +} + void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned int stage) @@ -316,8 +383,15 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, } tmp = (1U << alt->errata_id); - if (cpu_req_feature & tmp) - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + if (cpu_req_feature & tmp) { + /* do the basic patching */ + patch_text_nosync(alt->old_ptr, alt->alt_ptr, + alt->alt_len); + + riscv_alternative_fix_auipc_jalr(alt->old_ptr, + alt->alt_len, + alt->old_ptr - alt->alt_ptr); + } } } #endif From patchwork Fri Nov 4 22:51:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13032688 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A79BC433FE for ; Fri, 4 Nov 2022 22:52:32 +0000 (UTC) DKIM-Signature: v=1; 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Fri, 04 Nov 2022 23:52:05 +0100 From: Heiko Stuebner To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com, conor@kernel.org, philipp.tomsich@vrull.eu, Heiko Stuebner Subject: [PATCH RFC 7/9] RISC-V: add infrastructure to allow different str* implementations Date: Fri, 4 Nov 2022 23:51:51 +0100 Message-Id: <20221104225153.2710873-8-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104225153.2710873-1-heiko@sntech.de> References: <20221104225153.2710873-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_225212_262449_FA221590 X-CRM114-Status: GOOD ( 19.65 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Depending on supported extensions on specific RISC-V cores, optimized str* functions might make sense. This adds basic infrastructure to allow patching the function calls via alternatives later on. The main idea is to have the core str* functions be inline functions which then call the most optimized variant and this call then be replaced via alternatives. The big advantage is that we don't need additional calls. Though we need to duplicate the generic functions as the main code expects either itself or the architecture to provide the str* functions. The added *_generic functions are done in assembler (taken from disassembling the main-kernel functions for now) to allow us to control the used registers. Signed-off-by: Heiko Stuebner --- arch/riscv/include/asm/string.h | 77 +++++++++++++++++++++++++++++++++ arch/riscv/kernel/image-vars.h | 6 +-- arch/riscv/lib/Makefile | 4 ++ arch/riscv/lib/strcmp.S | 25 +++++++++++ arch/riscv/lib/string.c | 20 +++++++++ arch/riscv/lib/strlen.S | 17 ++++++++ arch/riscv/lib/strncmp.S | 27 ++++++++++++ 7 files changed, 173 insertions(+), 3 deletions(-) create mode 100644 arch/riscv/lib/strcmp.S create mode 100644 arch/riscv/lib/string.c create mode 100644 arch/riscv/lib/strlen.S create mode 100644 arch/riscv/lib/strncmp.S diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h index 909049366555..41eef000d18f 100644 --- a/arch/riscv/include/asm/string.h +++ b/arch/riscv/include/asm/string.h @@ -18,6 +18,83 @@ extern asmlinkage void *__memcpy(void *, const void *, size_t); #define __HAVE_ARCH_MEMMOVE extern asmlinkage void *memmove(void *, const void *, size_t); extern asmlinkage void *__memmove(void *, const void *, size_t); + +#define __HAVE_ARCH_STRCMP +extern asmlinkage int __strcmp_generic(const char *cs, const char *ct); + +static __always_inline int strcmp(const char *cs, const char *ct) +{ +#ifdef RISCV_EFISTUB + return __strcmp_generic(cs, ct); +#else + register const char* a0 asm("a0") = cs; + register const char* a1 asm("a1") = ct; + register int a0_out asm("a0"); + + asm volatile("call __strcmp_generic\n\t" + : "=r"(a0_out) + : "r"(a0), "r"(a1) + : "ra", "t0", "t1", "t2"); + + return a0_out; +#endif +} + +#define __HAVE_ARCH_STRNCMP +extern asmlinkage int __strncmp_generic(const char *cs, + const char *ct, size_t count); +extern asmlinkage int __strncmp_zbb(const char *cs, + const char *ct, size_t count); + +static __always_inline int strncmp(const char *cs, const char *ct, size_t count) +{ +#ifdef RISCV_EFISTUB + return __strncmp_generic(cs, ct, count); +#else + register const char* a0 asm("a0") = cs; + register const char* a1 asm("a1") = ct; + register size_t a2 asm("a2") = count; + register int a0_out asm("a0"); + + asm volatile("call __strncmp_generic\n\t" + : "=r"(a0_out) + : "r"(a0), "r"(a1), "r"(a2) + : "ra", "t0", "t1", "t2"); + + return a0_out; +#endif +} + +#define __HAVE_ARCH_STRLEN +extern asmlinkage __kernel_size_t __strlen_generic(const char *); + +static __always_inline __kernel_size_t strlen(const char *s) +{ + register const char* a0 asm("a0") = s; + register int a0_out asm("a0"); + + asm volatile( + "call __strlen_generic\n\t" + : "=r"(a0_out) + : "r"(a0) + : "ra", "t0", "t1"); + + return a0_out; +} + +#define __HAVE_ARCH_STRSTARTS +static inline bool strstarts(const char *str, const char *prefix) +{ +#ifdef RISCV_EFISTUB + return __strncmp_generic(str, prefix, __strlen_generic(prefix)) == 0; +#else + return strncmp(str, prefix, strlen(prefix)) == 0; +#endif +} + +#define __HAVE_ARCH_STRCHR +char *strchr(const char *s, int c); + /* For those files which don't want to check by kasan. */ #if defined(CONFIG_KASAN) && !defined(__SANITIZE_ADDRESS__) #define memcpy(dst, src, len) __memcpy(dst, src, len) diff --git a/arch/riscv/kernel/image-vars.h b/arch/riscv/kernel/image-vars.h index d6e5f739905e..2f270b9fde63 100644 --- a/arch/riscv/kernel/image-vars.h +++ b/arch/riscv/kernel/image-vars.h @@ -25,10 +25,10 @@ */ __efistub_memcmp = memcmp; __efistub_memchr = memchr; -__efistub_strlen = strlen; +__efistub___strlen_generic = __strlen_generic; __efistub_strnlen = strnlen; -__efistub_strcmp = strcmp; -__efistub_strncmp = strncmp; +__efistub___strcmp_generic = __strcmp_generic; +__efistub___strncmp_generic = __strncmp_generic; __efistub_strrchr = strrchr; __efistub__start = _start; diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 25d5c9664e57..38a18ce9acef 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -3,6 +3,10 @@ lib-y += delay.o lib-y += memcpy.o lib-y += memset.o lib-y += memmove.o +lib-y += string.o +lib-y += strcmp.o +lib-y += strlen.o +lib-y += strncmp.o lib-$(CONFIG_MMU) += uaccess.o lib-$(CONFIG_64BIT) += tishift.o diff --git a/arch/riscv/lib/strcmp.S b/arch/riscv/lib/strcmp.S new file mode 100644 index 000000000000..c74742699cd5 --- /dev/null +++ b/arch/riscv/lib/strcmp.S @@ -0,0 +1,25 @@ +#include +#include +#include + +/* int __strcmp_generic(const char *cs, const char *ct) */ +ENTRY(__strcmp_generic) + mv t2, a1 +1: + lbu t1, 0(a0) + lbu t0, 0(a1) + addi a0, a0, 1 + addi a1, a1, 1 + beq t1, t0, 3f + li a0, 1 + bgeu t1, t0, 2f + li a0, -1 +2: + mv a1, t2 + ret +3: + bnez t1, 1b + li a0, 0 + j 2b +END(__strcmp_generic) +EXPORT_SYMBOL(__strcmp_generic) diff --git a/arch/riscv/lib/string.c b/arch/riscv/lib/string.c new file mode 100644 index 000000000000..b595c95d0f23 --- /dev/null +++ b/arch/riscv/lib/string.c @@ -0,0 +1,20 @@ +#include +#include +#include + +/** + * strchr - Find the first occurrence of a character in a string + * @s: The string to be searched + * @c: The character to search for + * + * Note that the %NUL-terminator is considered part of the string, and can + * be searched for. + */ +char *strchr(const char *s, int c) +{ + for (; *s != (char)c; ++s) + if (*s == '\0') + return NULL; + return (char *)s; +} +EXPORT_SYMBOL(strchr); diff --git a/arch/riscv/lib/strlen.S b/arch/riscv/lib/strlen.S new file mode 100644 index 000000000000..ed27b933ddcb --- /dev/null +++ b/arch/riscv/lib/strlen.S @@ -0,0 +1,17 @@ +#include +#include +#include + +/* int __strlen_generic(const char *s) */ +ENTRY(__strlen_generic) + mv t1, a0 +1: + lbu t0, 0(t1) + bnez t0, 2f + sub a0, t1, a0 + ret +2: + addi t1, t1, 1 + j 1b +END(__strlen_generic) +EXPORT_SYMBOL(__strlen_generic) diff --git a/arch/riscv/lib/strncmp.S b/arch/riscv/lib/strncmp.S new file mode 100644 index 000000000000..9dbb85490127 --- /dev/null +++ b/arch/riscv/lib/strncmp.S @@ -0,0 +1,27 @@ +#include +#include +#include + +/* int __strncmp_generic(const char *cs, const char *ct, size_t count) */ +ENTRY(__strncmp_generic) + li t0, 0 +1: + beq a2, t0, 4f + add t1, a0, t0 + add t2, a1, t0 + lbu t1, 0(t1) + lbu t2, 0(t2) + beq t1, t2, 3f + li a0, 1 + bgeu t1, t2, 2f + li a0, -1 +2: + ret +3: + addi t0, t0, 1 + bnez t1, 1b +4: + li a0, 0 + j 2b +END(__strncmp_generic) +EXPORT_SYMBOL(__strncmp_generic) From patchwork Fri Nov 4 22:51:52 2022 Content-Type: text/plain; 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Fri, 04 Nov 2022 23:52:06 +0100 From: Heiko Stuebner To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com, conor@kernel.org, philipp.tomsich@vrull.eu, Heiko Stuebner Subject: [PATCH RFC 8/9] HACK: RISC-V: add zbb support to string functions Date: Fri, 4 Nov 2022 23:51:52 +0100 Message-Id: <20221104225153.2710873-9-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104225153.2710873-1-heiko@sntech.de> References: <20221104225153.2710873-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_155210_471690_57DC7692 X-CRM114-Status: GOOD ( 28.96 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Preliminary work on using ZBB to optimize some string functions. The ZBB-optimized variants itself do not like me yet, so I'm using copies of the generic functions to test the call-offset adaptions. Signed-off-by: Heiko Stuebner --- arch/riscv/Kconfig | 23 ++++++++ arch/riscv/include/asm/errata_list.h | 3 +- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/string.h | 27 +++++++-- arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 18 ++++++ arch/riscv/lib/Makefile | 6 ++ arch/riscv/lib/strcmp_tmp.S | 25 ++++++++ arch/riscv/lib/strcmp_zbb.S | 70 +++++++++++++++++++++++ arch/riscv/lib/strlen_tmp.S | 17 ++++++ arch/riscv/lib/strlen_zbb.S | 80 ++++++++++++++++++++++++++ arch/riscv/lib/strncmp_tmp.S | 27 +++++++++ arch/riscv/lib/strncmp_zbb.S | 85 ++++++++++++++++++++++++++++ 13 files changed, 378 insertions(+), 5 deletions(-) create mode 100644 arch/riscv/lib/strcmp_tmp.S create mode 100644 arch/riscv/lib/strcmp_zbb.S create mode 100644 arch/riscv/lib/strlen_tmp.S create mode 100644 arch/riscv/lib/strlen_zbb.S create mode 100644 arch/riscv/lib/strncmp_tmp.S create mode 100644 arch/riscv/lib/strncmp_zbb.S diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index acfc4d298aab..9efb1d4844df 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -411,6 +411,29 @@ config RISCV_ISA_SVPBMT If you don't know what to do here, say Y. +config TOOLCHAIN_HAS_ZBB + bool + default y + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zbb) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zbb) + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900 + +config RISCV_ISA_ZBB + bool "Zbb extension support for " + depends on TOOLCHAIN_HAS_ZBB + depends on !XIP_KERNEL && MMU + select RISCV_ALTERNATIVE + default y + help + Adds support to dynamically detect the presence of the ZBB + extension (...) and enable its + usage. + + The Zbb extension can be used to handle for example + ... + + If you don't know what to do here, say Y. + config TOOLCHAIN_HAS_ZICBOM bool default y diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 4180312d2a70..95e626b7281e 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -24,7 +24,8 @@ #define CPUFEATURE_SVPBMT 0 #define CPUFEATURE_ZICBOM 1 -#define CPUFEATURE_NUMBER 2 +#define CPUFEATURE_ZBB 2 +#define CPUFEATURE_NUMBER 3 #ifdef __ASSEMBLY__ diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b22525290073..ac5555fd9788 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -59,6 +59,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ZIHINTPAUSE, RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_SVINVAL, + RISCV_ISA_EXT_ZBB, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h index 41eef000d18f..25c8ab2cba2d 100644 --- a/arch/riscv/include/asm/string.h +++ b/arch/riscv/include/asm/string.h @@ -6,6 +6,8 @@ #ifndef _ASM_RISCV_STRING_H #define _ASM_RISCV_STRING_H +#include +#include #include #include @@ -21,6 +23,7 @@ extern asmlinkage void *__memmove(void *, const void *, size_t); #define __HAVE_ARCH_STRCMP extern asmlinkage int __strcmp_generic(const char *cs, const char *ct); +extern asmlinkage int __strcmp_tmp(const char *cs, const char *ct); static __always_inline int strcmp(const char *cs, const char *ct) { @@ -31,7 +34,11 @@ static __always_inline int strcmp(const char *cs, const char *ct) register const char* a1 asm("a1") = ct; register int a0_out asm("a0"); - asm volatile("call __strcmp_generic\n\t" + asm volatile( + ALTERNATIVE( + "call __strcmp_generic\n\t", + "call __strcmp_tmp\n\t", + 0, CPUFEATURE_ZBB, CONFIG_RISCV_ISA_ZBB) : "=r"(a0_out) : "r"(a0), "r"(a1) : "ra", "t0", "t1", "t2"); @@ -43,7 +50,7 @@ static __always_inline int strcmp(const char *cs, const char *ct) #define __HAVE_ARCH_STRNCMP extern asmlinkage int __strncmp_generic(const char *cs, const char *ct, size_t count); -extern asmlinkage int __strncmp_zbb(const char *cs, +extern asmlinkage int __strncmp_tmp(const char *cs, const char *ct, size_t count); static __always_inline int strncmp(const char *cs, const char *ct, size_t count) @@ -56,7 +63,11 @@ static __always_inline int strncmp(const char *cs, const char *ct, size_t count) register size_t a2 asm("a2") = count; register int a0_out asm("a0"); - asm volatile("call __strncmp_generic\n\t" + asm volatile( + ALTERNATIVE( + "call __strncmp_generic\n\t", + "call __strncmp_tmp\n\t", + 0, CPUFEATURE_ZBB, CONFIG_RISCV_ISA_ZBB) : "=r"(a0_out) : "r"(a0), "r"(a1), "r"(a2) : "ra", "t0", "t1", "t2"); @@ -67,19 +78,27 @@ static __always_inline int strncmp(const char *cs, const char *ct, size_t count) #define __HAVE_ARCH_STRLEN extern asmlinkage __kernel_size_t __strlen_generic(const char *); +extern asmlinkage __kernel_size_t __strlen_tmp(const char *); static __always_inline __kernel_size_t strlen(const char *s) { +#ifdef RISCV_EFISTUB + return __strlen_generic(s); +#else register const char* a0 asm("a0") = s; register int a0_out asm("a0"); asm volatile( - "call __strlen_generic\n\t" + ALTERNATIVE( + "call __strlen_generic\n\t", + "call __strlen_tmp\n\t", + 0, CPUFEATURE_ZBB, CONFIG_RISCV_ISA_ZBB) : "=r"(a0_out) : "r"(a0) : "ra", "t0", "t1"); return a0_out; +#endif } #define __HAVE_ARCH_STRSTARTS diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index bf9dd6764bad..66ff36a57e20 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -166,6 +166,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 22f3453d6db8..0c296fd1b1a5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -201,6 +201,7 @@ void __init riscv_fill_hwcap(void) } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); + SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); @@ -278,6 +279,20 @@ static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) return true; } +static bool __init_or_module cpufeature_probe_zbb(unsigned int stage) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_ZBB)) + return false; + + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) + return false; + + if (!riscv_isa_extension_available(NULL, ZBB)) + return false; + + return true; +} + /* * Probe presence of individual extensions. * @@ -295,6 +310,9 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage) if (cpufeature_probe_zicbom(stage)) cpu_req_feature |= BIT(CPUFEATURE_ZICBOM); + if (cpufeature_probe_zbb(stage)) + cpu_req_feature |= BIT(CPUFEATURE_ZBB); + return cpu_req_feature; } diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 38a18ce9acef..e9701fcec72c 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -5,8 +5,14 @@ lib-y += memset.o lib-y += memmove.o lib-y += string.o lib-y += strcmp.o +lib-y += strcmp_tmp.o +lib-$(CONFIG_RISCV_ISA_ZBB) += strcmp_zbb.o lib-y += strlen.o +lib-y += strlen_tmp.o +lib-$(CONFIG_RISCV_ISA_ZBB) += strlen_zbb.o lib-y += strncmp.o +lib-y += strncmp_tmp.o +lib-$(CONFIG_RISCV_ISA_ZBB) += strncmp_zbb.o lib-$(CONFIG_MMU) += uaccess.o lib-$(CONFIG_64BIT) += tishift.o diff --git a/arch/riscv/lib/strcmp_tmp.S b/arch/riscv/lib/strcmp_tmp.S new file mode 100644 index 000000000000..b8a6cfdc261b --- /dev/null +++ b/arch/riscv/lib/strcmp_tmp.S @@ -0,0 +1,25 @@ +#include +#include +#include + +/* int __strcmp_tmp(const char *cs, const char *ct) */ +ENTRY(__strcmp_tmp) + mv t2, a1 +1: + lbu t1, 0(a0) + lbu t0, 0(a1) + addi a0, a0, 1 + addi a1, a1, 1 + beq t1, t0, 3f + li a0, 1 + bgeu t1, t0, 2f + li a0, -1 +2: + mv a1, t2 + ret +3: + bnez t1, 1b + li a0, 0 + j 2b +END(__strcmp_tmp) +EXPORT_SYMBOL(__strcmp_tmp) diff --git a/arch/riscv/lib/strcmp_zbb.S b/arch/riscv/lib/strcmp_zbb.S new file mode 100644 index 000000000000..3137d0912a90 --- /dev/null +++ b/arch/riscv/lib/strcmp_zbb.S @@ -0,0 +1,70 @@ +#include +#include +#include + +#define src1 a0 +#define result a0 +#define src2 a1 +#define data1 a2 +#define data2 a3 +#define align a4 +#define data1_orcb t0 +#define m1 t2 + +.option push +.option arch,+zbb + +ENTRY(__strcmp_zbb) + or align, src1, src2 + li m1, -1 + and align, align, SZREG-1 + bnez align, 3f + /* Main loop for aligned string. */ + .p2align 3 +1: + REG_L data1, 0(src1) + REG_L data2, 0(src2) + orc.b data1_orcb, data1 + bne data1_orcb, m1, 2f + addi src1, src1, SZREG + addi src2, src2, SZREG + beq data1, data2, 1b + + /* Words don't match, and no null byte in the first + * word. Get bytes in big-endian order and compare. */ +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + rev8 data1, data1 + rev8 data2, data2 +#endif + /* Synthesize (data1 >= data2) ? 1 : -1 in a branchless sequence. */ + sltu result, data1, data2 + neg result, result + ori result, result, 1 + ret + +2: + /* Found a null byte. + * If words don't match, fall back to simple loop. */ + bne data1, data2, 3f + + /* Otherwise, strings are equal. */ + li result, 0 + ret + + /* Simple loop for misaligned strings. */ + .p2align 3 +3: + lbu data1, 0(src1) + lbu data2, 0(src2) + addi src1, src1, 1 + addi src2, src2, 1 + bne data1, data2, 4f + bnez data1, 3b + +4: + sub result, data1, data2 + ret +END(__strcmp_zbb) +EXPORT_SYMBOL(__strcmp_zbb) + +.option pop diff --git a/arch/riscv/lib/strlen_tmp.S b/arch/riscv/lib/strlen_tmp.S new file mode 100644 index 000000000000..45a7d1f6dfad --- /dev/null +++ b/arch/riscv/lib/strlen_tmp.S @@ -0,0 +1,17 @@ +#include +#include +#include + +/* int __strlen_tmp(const char *s) */ +ENTRY(__strlen_tmp) + mv t1, a0 +1: + lbu t0, 0(t1) + bnez t0, 2f + sub a0, t1, a0 + ret +2: + addi t1, t1, 1 + j 1b +END(__strlen_tmp) +EXPORT_SYMBOL(__strlen_tmp) diff --git a/arch/riscv/lib/strlen_zbb.S b/arch/riscv/lib/strlen_zbb.S new file mode 100644 index 000000000000..9bcd3fecd099 --- /dev/null +++ b/arch/riscv/lib/strlen_zbb.S @@ -0,0 +1,80 @@ +#include +#include +#include + +#define src a0 +#define result a0 +#define addr a1 +#define data a2 +#define offset a3 +#define offset_bits a3 +#define valid_bytes a4 +#define m1 a4 + +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +# define CZ clz +# define SHIFT sll +#else +# define CZ ctz +# define SHIFT srl +#endif + +.option push +.option arch,+zbb + +ENTRY(__strlen_zbb) + /* Number of irrelevant bytes in the first word. */ + andi offset, src, SZREG-1 + /* Align pointer. */ + andi addr, src, -SZREG + + li valid_bytes, SZREG + sub valid_bytes, valid_bytes, offset + slli offset_bits, offset, RISCV_LGPTR + + /* Get the first word. */ + REG_L data, 0(addr) + /* Shift away the partial data we loaded to remove the irrelevant bytes + * preceeding the string with the effect of adding NUL bytes at the + * end of the string. */ + SHIFT data, data, offset_bits + /* Convert non-NUL into 0xff and NUL into 0x00. */ + orc.b data, data + /* Convert non-NUL into 0x00 and NUL into 0xff. */ + not data, data + /* Search for the first set bit (corresponding to a NUL byte in the + * original chunk). */ + CZ data, data + /* The first chunk is special: commpare against the number + * of valid bytes in this chunk. */ + srli result, data, 3 + bgtu valid_bytes, result, 3f + + /* Prepare for the word comparison loop. */ + addi offset, addr, SZREG + li m1, -1 + + /* Our critical loop is 4 instructions and processes data in + * 4 byte or 8 byte chunks. */ + .p2align 3 +1: + REG_L data, SZREG(addr) + addi addr, addr, SZREG + orc.b data, data + beq data, m1, 1b +2: + not data, data + CZ data, data + /* Get number of processed words. */ + sub offset, addr, offset + /* Add number of characters in the first word. */ + add result, result, offset + srli data, data, 3 + /* Add number of characters in the last word. */ + add result, result, data +3: + ret +END(__strlen_zbb) +EXPORT_SYMBOL(__strlen_zbb) + +.option pop diff --git a/arch/riscv/lib/strncmp_tmp.S b/arch/riscv/lib/strncmp_tmp.S new file mode 100644 index 000000000000..01c10c8b58b0 --- /dev/null +++ b/arch/riscv/lib/strncmp_tmp.S @@ -0,0 +1,27 @@ +#include +#include +#include + +/* int __strncmp_tmp(const char *cs, const char *ct, size_t count) */ +ENTRY(__strncmp_tmp) + li t0, 0 +1: + beq a2, t0, 4f + add t1, a0, t0 + add t2, a1, t0 + lbu t1, 0(t1) + lbu t2, 0(t2) + beq t1, t2, 3f + li a0, 1 + bgeu t1, t2, 2f + li a0, -1 +2: + ret +3: + addi t0, t0, 1 + bnez t1, 1b +4: + li a0, 0 + j 2b +END(__strncmp_tmp) +EXPORT_SYMBOL(__strncmp_tmp) diff --git a/arch/riscv/lib/strncmp_zbb.S b/arch/riscv/lib/strncmp_zbb.S new file mode 100644 index 000000000000..e9bd94ebac25 --- /dev/null +++ b/arch/riscv/lib/strncmp_zbb.S @@ -0,0 +1,85 @@ +#include +#include +#include + +#define src1 a0 +#define result a0 +#define src2 a1 +#define len a2 +#define data1 a2 +#define data2 a3 +#define align a4 +#define data1_orcb a5 +#define limit t0 +#define m1 t1 + +.option push +.option arch,+zbb + +ENTRY(__strncmp_zbb) + or align, src1, src2 + li m1, -1 + and align, align, SZREG-1 + add limit, src1, len + bnez align, 4f + + /* Adjust limit for fast-path. */ + addi limit, limit, -SZREG + /* Main loop for aligned string. */ + .p2align 3 +1: + bgt src1, limit, 3f + REG_L data1, 0(src1) + REG_L data2, 0(src2) + orc.b data1_orcb, data1 + bne data1_orcb, m1, 2f + addi src1, src1, SZREG + addi src2, src2, SZREG + beq data1, data2, 1b + + /* Words don't match, and no null byte in the first + * word. Get bytes in big-endian order and compare. */ +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + rev8 data1, data1 + rev8 data2, data2 +#endif + /* Synthesize (data1 >= data2) ? 1 : -1 in a branchless sequence. */ + sltu result, data1, data2 + neg result, result + ori result, result, 1 + ret + +2: + /* Found a null byte. + * If words don't match, fall back to simple loop. */ + bne data1, data2, 3f + + /* Otherwise, strings are equal. */ + li result, 0 + ret + + /* Simple loop for misaligned strings. */ +3: + /* Restore limit for slow-path. */ + addi limit, limit, SZREG + .p2align 3 +4: + bge src1, limit, 6f + lbu data1, 0(src1) + lbu data2, 0(src2) + addi src1, src1, 1 + addi src2, src2, 1 + bne data1, data2, 5f + bnez data1, 4b + +5: + sub result, data1, data2 + ret + +6: + li result, 0 + ret +END(__strncmp_zbb) +EXPORT_SYMBOL(__strncmp_zbb) + +.option pop From patchwork Fri Nov 4 22:51:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Heiko_St=C3=BCbner?= X-Patchwork-Id: 13032686 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02789C43219 for ; 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Fri, 04 Nov 2022 22:52:14 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1or5Xi-0001sc-HL; Fri, 04 Nov 2022 23:52:06 +0100 From: Heiko Stuebner To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com, conor@kernel.org, philipp.tomsich@vrull.eu, Heiko Stuebner Subject: [PATCH RFC 9/9] HACK: disable strchr call in overlay-fs Date: Fri, 4 Nov 2022 23:51:53 +0100 Message-Id: <20221104225153.2710873-10-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221104225153.2710873-1-heiko@sntech.de> References: <20221104225153.2710873-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221104_225212_400758_28FF5801 X-CRM114-Status: GOOD ( 11.49 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Although the standard strchr function does _not_ use strlen at all, the compiled result with the str*-alternatives somehow wants to link against a then-nonexistent strlen symbol. All real strlen invocations everywhere else will use the correct functions though. Need to investigate what happens here. Signed-off-by: Heiko Stuebner --- fs/overlayfs/super.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/overlayfs/super.c b/fs/overlayfs/super.c index a29a8afe9b26..9e36d0bd7f02 100644 --- a/fs/overlayfs/super.c +++ b/fs/overlayfs/super.c @@ -1833,7 +1833,8 @@ static struct ovl_entry *ovl_get_lowerstack(struct super_block *sb, if (err) goto out_err; - lower = strchr(lower, '\0') + 1; +//FIXME: this somehow then wants to access a non-existent _strlen_ symbol +// lower = strchr(lower, '\0') + 1; } err = -EINVAL;