From patchwork Mon Nov 7 12:09:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13034285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41E58C433FE for ; Mon, 7 Nov 2022 12:09:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229638AbiKGMJv (ORCPT ); Mon, 7 Nov 2022 07:09:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230313AbiKGMJu (ORCPT ); Mon, 7 Nov 2022 07:09:50 -0500 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 212FBB48 for ; Mon, 7 Nov 2022 04:09:49 -0800 (PST) Received: by mail-lj1-x22d.google.com with SMTP id u11so15906817ljk.6 for ; Mon, 07 Nov 2022 04:09:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=FcNmjKLMj/t6peWOXBMwpkGFM+kDqqzNyUK1wLaHjNo=; b=x34/wz6HPrZKgl9RBCOY+gcBinrGwOY4bj8Y09jZ3yDrs3L+SkqTxyNlDDFwrSpaS+ K5rhVK4fsJEYoGuBGBUjEPkosKAFyWq9oEkMCdWkf53BrnF7GQ+neh1OwHP2slSsPVoG YhkR0dGw4f7j4MTneb2KUquvZ9RK0eb0ImtvZCtEef15tPl0baiPdiw8NGbQCMNmsloC DdLEEw6oeAvessQGKZAYmOtZlGJUMiqDtZissshzrmLfbFXNxJgKyf5pWFRqKB0SrRYD LsRXndaC+90j0q48RHgm56cYbcuE2g9CWGq4HmTQf7OY749dQ/n7nYwaqt4tgb4/S35/ 1bdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=FcNmjKLMj/t6peWOXBMwpkGFM+kDqqzNyUK1wLaHjNo=; b=XDO9G2Ed3VEkYp4UaJNXv1a3uoZRCDcTJkITrB1laz7GAnHH7QSHVpz3sT72aOtw2e zl6ni8V9VK82eV4hA5Hz+gyq4ViwziKOI1/AQq5LlV5CjVWRQM0+PzQHQTZ5w2vFLtgX EwU6LHtrVyb81AdjSYijw/05Q0FIt3aaHLOAVzcb1K7rUb3J5l5vjSMoRQkBnf/qM6DO hpFtQx+dLqYW7pTqMGbsHS0SeCFt8Ibr/CZI1woRiRrWofwpfbUMGFwOVAv7diamLkht uAsOrU8oQ07gQRW6Y5s7BtqT0YBKdT4cyVWJh2jyB8t0DP73lEc6AY3t2sDyuZZEc+Oc G1uw== X-Gm-Message-State: ACrzQf3Ha/0s/fz+suTtImWk5xKBnuoJwZ+RA+1A1+NpBSHAXjKf5VC4 n8J68EXVwXy5JIyTuP1IkNHwl/N1IMVMOLKq X-Google-Smtp-Source: AMsMyM63NQrLj4DKJt1HJx8Vhdp/BXHoB9xFL7eImzgcvwzFh6Te6cBloUm1ANuX4TjPEsV97XHCyA== X-Received: by 2002:a2e:8811:0:b0:26d:fd3f:c5c3 with SMTP id x17-20020a2e8811000000b0026dfd3fc5c3mr5209739ljh.494.1667822987249; Mon, 07 Nov 2022 04:09:47 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id p13-20020ac24ecd000000b004a608ec6d8csm1219723lfr.27.2022.11.07.04.09.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 04:09:46 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Robin Murphy , Luca Weiss , Chanho Park , Thierry Reding , Iskren Chernev , Stephan Gerhold , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND v3 1/4] dt-bindings: arm: cpus: Add Kryo 660 CPUs Date: Mon, 7 Nov 2022 13:09:16 +0100 Message-Id: <20221107120920.12593-1-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Konrad Dybcio Add a compatible for Kryo 660 CPUs found in at least Qualcomm SM6375. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski --- Changes since v2: - Add second S-o-b Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 5c13b73e4d57..b2058345bb8e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -183,6 +183,7 @@ properties: - qcom,kryo485 - qcom,kryo560 - qcom,kryo570 + - qcom,kryo660 - qcom,kryo685 - qcom,kryo780 - qcom,scorpion From patchwork Mon Nov 7 12:09:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13034286 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C6D6C43219 for ; Mon, 7 Nov 2022 12:09:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230363AbiKGMJx (ORCPT ); Mon, 7 Nov 2022 07:09:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231294AbiKGMJv (ORCPT ); Mon, 7 Nov 2022 07:09:51 -0500 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8B9FC19 for ; Mon, 7 Nov 2022 04:09:50 -0800 (PST) Received: by mail-lj1-x241.google.com with SMTP id z24so15918586ljn.4 for ; Mon, 07 Nov 2022 04:09:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pFPA7Nxa+A29+qXbNJAfRlr+gr6r5BOHPFWJnJ71dzU=; b=kJI5bK6O0WEoQyaLCbPd4PgULSDZ01Vy+MTdytmJKbo9YkRxshuBDWu5waTNCs9Liy fNgOVllQQC38I1stQjKle6Lt2Kh/JFUdvfjsIi1J6NOjmkZgV5n2E1pKPlsPdwtBtME3 yB1pcBp+Ue5PGZNDexocGhs3eLcw6XCrLQz8ufAdZj5JQqjst0wtN9X4ImOP8iASqjox +IlYQZ2mLIT92aJ6n6SfZ3Z33BPA1DcgIQkJF0q2iFQBy7qoZMZjxxKsB6/M/Y1/1hdo 3Y6nVVjDOLnwFJaYQYutPhgKMXcGEum+QU34utoHvpXTPxPADqU79o78GQe7bVUHbk32 9pNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pFPA7Nxa+A29+qXbNJAfRlr+gr6r5BOHPFWJnJ71dzU=; b=hVpId5zXNDhAe0epcuypbKrNP7xY/vl+WZGcSTg+PSnaAvwC9N7RhAI1tgU20CSMcm +OgOWrEXohtaBtHEkU8l9Kr1aGJWIIPWdXuTC8qFPmd+Coriynv0Q2zW06X9+VwmtLHr 4LnITiBxJgNVbE23uMsfs+obPINWyNUoDjYcnJupJl5KYT7AEx76Z2j/ogU2JQckvTPv tOgYk5EQKRv/5OLPD1lJQ/8WhO91941qq45qHiTl7UuhPlupdO7XjhPCWZsNeljZxlbt FbCvaO1iWkrNA2nudQVn16HfjnKqdypBsFfKFljisYu4dAWIHJQM2ps/qu4eHuQltBaD Jqiw== X-Gm-Message-State: ACrzQf15m7wPNe0Kpv2NNjQFFDgu0IKX1xXkNsrro0HTD4UsYzJaUKii G3jPvMDB40pJP+kaU2bUNe14snhsXglnd90W X-Google-Smtp-Source: AMsMyM7ypMPbhVj2KLCVyuL4+ZlVgGcGVwdCHeT6s9J5MytaQj5cQ+64jLMbcVHBVMxvVz2EeBexJg== X-Received: by 2002:a2e:b521:0:b0:277:14cf:6da2 with SMTP id z1-20020a2eb521000000b0027714cf6da2mr5096216ljm.94.1667822988747; Mon, 07 Nov 2022 04:09:48 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id p13-20020ac24ecd000000b004a608ec6d8csm1219723lfr.27.2022.11.07.04.09.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 04:09:48 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Robin Murphy , Luca Weiss , Chanho Park , Thierry Reding , Iskren Chernev , Stephan Gerhold , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND v3 2/4] dt-bindings: arm: qcom: Document SM6375 & Xperia 10 IV Date: Mon, 7 Nov 2022 13:09:17 +0100 Message-Id: <20221107120920.12593-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221107120920.12593-1-konrad.dybcio@linaro.org> References: <20221107120920.12593-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Konrad Dybcio Add compatibles for Sony Xperia 10 IV (PDX225) and the SM6375 SoC it's based on. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- Changes since v2: - Add second S-o-b Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 207e28260206..35e22cf15f9f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -56,6 +56,7 @@ description: | sdx65 sm6125 sm6350 + sm6375 sm7225 sm8150 sm8250 @@ -718,6 +719,11 @@ properties: - sony,pdx213 - const: qcom,sm6350 + - items: + - enum: + - sony,pdx225 + - const: qcom,sm6375 + - items: - enum: - fairphone,fp4 From patchwork Mon Nov 7 12:09:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13034287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EABFCC433FE for ; Mon, 7 Nov 2022 12:10:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231653AbiKGMKA (ORCPT ); Mon, 7 Nov 2022 07:10:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231600AbiKGMJ4 (ORCPT ); Mon, 7 Nov 2022 07:09:56 -0500 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF049E12 for ; Mon, 7 Nov 2022 04:09:53 -0800 (PST) Received: by mail-lj1-x22a.google.com with SMTP id l8so15889800ljh.13 for ; Mon, 07 Nov 2022 04:09:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u+lAbRgTpfN0i9mLuZNIjk415UTzAxU/M0hToNSGsr4=; b=XNRpkuhXiP4QuwrxVtZQ0hwnZ4dEMxy0m/d0I20QUCouCfFz5rZ7ZnpN4uMl3415D6 nWnyeiYKpNIeCiLrwd2UruvSEwt8USOR1Nwr8KTFYMMufP/u4VibXIlzo9JYFly2uafJ 2M1KxYJUu0q/PWlv2BS+W0BjmT4qioB1f0ntUXCf1Io8t5DqwYP4/LxTSC4QlP7Q9e0P KNFlB73XRWEVx6pfZoZb7AsHpoJGB5gQqMbT59Jxy6gdKcoh1HQTeA1t91jxYmM/VKkD W4IxttjBOEKHrl5ERbySXANSumqUYXvJxe939xHEz5YTtrlPFvRSdpUUB9cI9BCb9Q6W FC8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u+lAbRgTpfN0i9mLuZNIjk415UTzAxU/M0hToNSGsr4=; b=iQoMxaagp8x6RG3mK0PG/9oZvQP2WZ6ueSxdT7xDz8eeIedpO+mTb2+zu/fAN5YT/z zEq3EiiCPyk9WfoZJVnCOfcyVpJnRlDXFJNdDJnGnHjIwiKOliDphpgHrAyUIbGjwxck VSaXxPRYnAgqEea6CWfSaXH11jKNsFI1KT1/8o3Zk03gpMLdSVfoU9tZDSgNDPOwGbb6 22XaQjGOyEfHZTiEQ1Pukr1xwvcDddn/BP2emm1O8KX7S+Z1tnp4cDYa9guwSVkhzOUN xe2RzEHIa3pG0aPHbnizQpp5pYqmE/1VpHnGrvQjkrZMVaY/5iaRgC8GflIMpUTSLhGl QgIQ== X-Gm-Message-State: ACrzQf3SbcJyyixSTsMsd8+hnKB/GYo2Tv9tSNEmTEE6lYyiISj0V1L5 KjQHZnCAtpB/gwiact0Gcs6HSn7jTFkshiDK X-Google-Smtp-Source: AMsMyM6nhK7y419ZVBmT4MBhDdG/lLfik+awbwtUQ9dzK/kORH0Lw91RU2Snb4qsixed5cRQwWN7Pg== X-Received: by 2002:a2e:7005:0:b0:277:1cfb:95c6 with SMTP id l5-20020a2e7005000000b002771cfb95c6mr16742853ljc.146.1667822991718; Mon, 07 Nov 2022 04:09:51 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id p13-20020ac24ecd000000b004a608ec6d8csm1219723lfr.27.2022.11.07.04.09.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 04:09:51 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Robin Murphy , Luca Weiss , Chanho Park , Thierry Reding , Iskren Chernev , Stephan Gerhold , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND v3 3/4] arm64: dts: qcom: Add initial device tree for SM6375 Date: Mon, 7 Nov 2022 13:09:18 +0100 Message-Id: <20221107120920.12593-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221107120920.12593-1-konrad.dybcio@linaro.org> References: <20221107120920.12593-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Konrad Dybcio Add an initial device tree for the SM6375 (SD695) SoC. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio --- Changes since v2: - Add second s-o-b - Collapse the smem node into its mem region - Use non-generic node names for reserved-memory children - Feed rpmcc the xo clock - Remove clock-output-names from xo - Rename xo-board to xo-board-clk and remove clk-output-names - Move xo clk freq to device DTS arch/arm64/boot/dts/qcom/sm6375.dtsi | 804 +++++++++++++++++++++++++++ 1 file changed, 804 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6375.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi new file mode 100644 index 000000000000..9b1a497e5ca7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -0,0 +1,804 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Konrad Dybcio + */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo660"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-collapse"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + local-timer-stop; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sm6375", "qcom,scm"; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hypervisor@80000000 { + reg = <0 0x80000000 0 0x600000>; + no-map; + }; + + xbl_aop_mem: xbl-aop@80700000 { + reg = <0 0x80700000 0 0x100000>; + no-map; + }; + + reserved_xbl_uefi: xbl-uefi-res@80880000 { + reg = <0 0x80880000 0 0x14000>; + no-map; + }; + + smem_mem: smem@80900000 { + compatible = "qcom,smem"; + reg = <0 0x80900000 0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + fw_mem: fw@80b00000 { + reg = <0 0x80b00000 0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 { + reg = <0 0x80c00000 0 0x1e00000>; + no-map; + }; + + dfps_data_mem: dpfs-data@85e00000 { + reg = <0 0x85e00000 0 0x100000>; + no-map; + }; + + pil_wlan_mem: pil-wlan@86500000 { + reg = <0 0x86500000 0 0x200000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@86700000 { + reg = <0 0x86700000 0 0x2000000>; + no-map; + }; + + pil_cdsp_mem: pil-cdsp@88700000 { + reg = <0 0x88700000 0 0x1e00000>; + no-map; + }; + + pil_video_mem: pil-video@8a500000 { + reg = <0 0x8a500000 0 0x500000>; + no-map; + }; + + pil_ipa_fw_mem: pil-ipa-fw@8aa00000 { + reg = <0 0x8aa00000 0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 { + reg = <0 0x8aa10000 0 0xa000>; + no-map; + }; + + pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 { + reg = <0 0x8aa1a000 0 0x2000>; + no-map; + }; + + pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 { + reg = <0 0x8b800000 0 0x10000000>; + no-map; + }; + + removed_mem: removed@c0000000 { + reg = <0 0xc0000000 0 0x5100000>; + no-map; + }; + + debug_mem: debug@ffb00000 { + reg = <0 0xffb00000 0 0xc0000>; + no-map; + }; + + last_log_mem: lastlog@ffbc0000 { + reg = <0 0xffbc0000 0 0x80000>; + no-map; + }; + + cmdline_region: cmdline@ffd00000 { + reg = <0 0xffd00000 0 0x1000>; + no-map; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6375"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; + clocks = <&xo_board_clk>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6375-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo_no_cpr: opp9 { + opp-level = ; + }; + }; + }; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + ipcc: mailbox@208000 { + compatible = "qcom,sm6375-ipcc", "qcom,ipcc"; + reg = <0 0x00208000 0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x00340000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,sm6375-tlmm"; + reg = <0 0x00500000 0 0x800000>; + interrupts = ; + gpio-ranges = <&tlmm 0 0 157>; + /* TODO: Hook up MPM as wakeup-parent when it's there */ + interrupt-controller; + gpio-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,sm6375-gcc"; + reg = <0 0x01400000 0 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + #power-domain-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + usb_1_hsphy: phy@162b000 { + compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x0162b000 0 0x400>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + #phy-cells = <0>; + + status = "disabled"; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x01c40000 0 0x1100>, + <0 0x01e00000 0 0x2000000>, + <0 0x03e00000 0 0x100000>, + <0 0x03f00000 0 0xa0000>, + <0 0x01c0a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0 0x045f0000 0 0x7000>; + }; + + usb_1: usb@4ef8800 { + compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; + reg = <0 0x04ef8800 0 0x400>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + /* + * This property is there to allow USB2 to work, as + * USB3 is not implemented yet - (re)move it when + * proper support is in place. + */ + qcom,select-utmi-as-pipe-clk; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0 0x04e00000 0 0xcd00>; + interrupts = ; + maximum-speed = "high-speed"; + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0xe0 0x0>; + + /* Yes, this impl *does* have an unfunny number of quirks.. */ + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; + reg = <0 0x0c600000 0 0x100000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>, + <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC>, + <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; + #global-interrupts = <1>; + #iommu-cells = <2>; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ + <0x0 0x0f240000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + #redistributor-regions = <1>; + #interrupt-cells = <3>; + redistributor-stride = <0 0x20000>; + interrupt-controller; + }; + + timer@f420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0 0x0f420000 0 0x1000>; + ranges = <0 0 0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@f421000 { + reg = <0x0f421000 0x1000>, <0x0f422000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@f423000 { + reg = <0x0f243000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@f425000 { + reg = <0x0f425000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@f427000 { + reg = <0x0f427000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@f429000 { + reg = <0x0f429000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@f42b000 { + reg = <0x0f42b000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@f42d000 { + reg = <0x0f42d000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + cpufreq_hw: cpufreq@fd91000 { + compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + #freq-domain-cells = <1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From patchwork Mon Nov 7 12:09:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13034288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A310C4332F for ; Mon, 7 Nov 2022 12:10:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231998AbiKGMKO (ORCPT ); Mon, 7 Nov 2022 07:10:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231286AbiKGMKJ (ORCPT ); Mon, 7 Nov 2022 07:10:09 -0500 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDFBBE55 for ; Mon, 7 Nov 2022 04:09:56 -0800 (PST) Received: by mail-lj1-x22a.google.com with SMTP id h12so15885312ljg.9 for ; Mon, 07 Nov 2022 04:09:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AxKWVOswdBco5ma866B6Lf4pSuG2XDt8/IH4jcoYTSQ=; b=jmAhlMLKWKm2L2oRzwVLoe/YclTG857LI5aHsp4261khfuvRx867Kd4EyOHyfjq4e1 YSzoHEeHnP7b6TbUEkcB48FwaedLYR7Fd7KOoS3MPQDLLJq9EG/cwS11IjopccNSIBIc vnC5HJ9Sw0H7fLMl3SlZ255iHxW7xZW/UyF4hcgJ/7XXdNCcAf5DUoSGF3DmYKKuXGUP k1HlljnYPkHC4w6ldXkjCDbh5F/YeS7ysdaUDCJRw+ipeI8CO7S8YpqOa7xvoIr9uQym 4AsTKxo6iCCoEF8NnYXJLFtaJKiBaFkIH9x0w/Jnr4BgqUciegje2Xnk+iBJJy8SKGF3 sv+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AxKWVOswdBco5ma866B6Lf4pSuG2XDt8/IH4jcoYTSQ=; b=uyHLZF4bnWRk+/AXkyGolHVOUjvLv9g+1BoZpS2VFA/nnIWu2vski7fR/K2XYbaXB6 AXu8+KnqoCBL26me4NDoDtAq5NUCzLdKKv8EHX1MmjaxE22tBB1+lsDUIGKh9xnKd8rW 32qVnJMQBGdQv/HkFsQmV4Xq+JLhhvd/1XMWoz0PxCnjc5UU5HXsedOlzfkYU0GgOWNU qtceOQHd+iKyrmp8zcM4yKN6K/iMky2wd5yE7h/JMoWBpThUbC+oq13w5Hp2r90xRX/o U6tXuQlyKpceC6bLHvIZWT2EUTkgJnzhxS6l4nSBMjW/u8LbUgrowHL12Oi55vsTe8Qu jr4g== X-Gm-Message-State: ACrzQf1ssaGsSrKG5t4cF579KHiFzYlAr6F9otvTmm+q4UZWVmD7lE5S 27nlfxOSg5u0rOhgXUskYGuVqEZiD4bfI98/ X-Google-Smtp-Source: AMsMyM7S/PSn5TZVi5GtjxfZrpsY7HoYZwinRMq7G0i1mRqfmZEuMUkrWSB9imGJumnH7MIIbD+yJQ== X-Received: by 2002:a2e:834c:0:b0:277:24e1:7b80 with SMTP id l12-20020a2e834c000000b0027724e17b80mr16375564ljh.302.1667822994621; Mon, 07 Nov 2022 04:09:54 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id p13-20020ac24ecd000000b004a608ec6d8csm1219723lfr.27.2022.11.07.04.09.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 07 Nov 2022 04:09:54 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Robin Murphy , Luca Weiss , Chanho Park , Thierry Reding , Iskren Chernev , Stephan Gerhold , Lorenzo Pieralisi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kees Cook , Tony Luck , "Guilherme G. Piccoli" , linux-hardening@vger.kernel.org Subject: [PATCH RESEND v3 4/4] arm64: dts: qcom: Add device tree for Sony Xperia 10 IV Date: Mon, 7 Nov 2022 13:09:19 +0100 Message-Id: <20221107120920.12593-4-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221107120920.12593-1-konrad.dybcio@linaro.org> References: <20221107120920.12593-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Konrad Dybcio Add support for Sony Xperia 10 IV, a.k.a PDX225. This device is a part of the SoMC SM6375 Murray platform and currently it is the only device based on that board, so no -common DTSI is created until (if?) other Murray devices appear. This commit brings support for: * USB (only USB2 for now) * Display via simplefb To create a working boot image, you need to run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm6375-sony-xperia-\ murray-pdx225.dtb > .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline "SOME_CMDLINE" \ --dtb_offset 0x1f00000 \ --header_version 1 \ --os_version 12 \ --os_patch_level 2022-04 \ # or newer -o boot.img-sony-xperia-pdx225 Then, you need to flash it on the device and get rid of all the vendor_boot/dtbo mess: First, you need to get rid of vendor_boot. However, the bootloader is utterly retarded and it will not let you neither flash nor erase it. There are a couple ways to handle this: you can either dd /dev/zero to it from Android (if you have root) or a custom recovery or from fastbootd (fastboot/adb reboot fastboot). You will not be able to boot Android images on your phone unless you lock the bootloader (fastboot oem lock) and restore the factory image with Xperia Companion Windows-and-macOS-only software. The best way so far is probably to use the second (_b) slot and flash mainline there. This will however require you to flash some partitions manually, as they are not populated from factory: (boot_b, dtbo_b, vendor_boot_b, vbmeta_b, vbmeta_system_b) - these we don't really care about as we nuke/replace them (dsp_b, imagefv_b, modem_b, oem_b, rdimage_b) - these you NEED to populate to get a successful boot on slot B, otherwise you will have limited / no functionality. To switch slots, simply run: fastboot --set-active=a //or =b The rest assumes you are on slot A. // You have to either pull vbmeta{"","_system"} from // /dev/block/bootdevice/by-name/ or build one as a part of AOSP fastboot --disable-verity --disable-verification flash vbmeta_b vbmeta.img fastboot --disable-verity --disable-verification flash vbmeta_system_b \ vbmeta_system.img fastboot flash boot_b boot.img-sony-xperia-pdx225 fastboot reboot fastboot // entering fastbootd fastboot flash vendor_boot_b emptything.img fastboot flash dtbo_b emptything.img fastboot reboot bootloader // entering bootloader fastboot fastboot --set-active=b fastboot reboot // mainline time! Where emptything.img is a tiny file that consists of 2 bytes (all zeroes), doing a "fastboot erase" won't cut it, the bootloader will go crazy and things will fall apart when it tries to overlay random bytes from an empty partition onto a perfectly good appended DTB. From there on you can flash new mainline builds by simply flashing boot.img that you create after each kernel rebuild. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- Changes since v2: - Add second S-o-b - Move xo freq to this DTS arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 86 +++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index b0558d3389e5..0292d116c25b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -144,6 +144,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts new file mode 100644 index 000000000000..450d4a557df1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Konrad Dybcio + */ + +/dts-v1/; + +#include +#include "sm6375.dtsi" +#include "pmr735a.dtsi" + +/ { + model = "Sony Xperia 10 IV"; + compatible = "sony,pdx225", "qcom,sm6375"; + chassis-type = "handset"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@85200000 { + compatible = "simple-framebuffer"; + reg = <0 0x85200000 0 0xc00000>; + + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + /* + * That's (going to be) a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet + */ + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + }; + }; + + reserved-memory { + cont_splash_mem: memory@85200000 { + reg = <0 0x85200000 0 0xc00000>; + no-map; + }; + + ramoops@ffc40000 { + compatible = "ramoops"; + reg = <0 0xffc40000 0 0xb0000>; + record-size = <0x10000>; + console-size = <0x60000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + ecc-size = <16>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&tlmm { + gpio-reserved-ranges = <13 4>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <19200000>; +};