From patchwork Thu Aug 9 12:32:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 10561373 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A1B0613AC for ; Thu, 9 Aug 2018 12:33:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E16F2A12C for ; Thu, 9 Aug 2018 12:33:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8154C2A507; Thu, 9 Aug 2018 12:33:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 326FC2A12C for ; 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b=IhdUGWIiCQwweSZinNndVlE2oS6ujRvH0elCM/xjhc3dTmXiGZl6iyj6o+P88Mu5IK sFdF2koo8VrkAGFMxkhcTPvxBlm/rmPnGtVYaH59fSpWMDb1m0znPUNIetjBR+fj3Wbe tsqAXBASEpPcuVOMwoLu1wB6NDsBX4YR8nMQt/+tq14lq0apYkirUcD3PA35tqMH8/Pm DVJgZw4QVv8ZpfkVhnX+XqfQllSNIM8WHfNDhzqm7ddokB3pvwt3t8xCx/gDk+vCp3OT M/GHW2Ve4+QBsaCRJF2+VF3B8DH9N9eUDX/4SQ8WWYzXPqQmeBn2/LA6aF9iY/XTIqu5 VGsA== X-Gm-Message-State: AOUpUlFBpiwHtokMkkifJminzGds8zxwG79E0UlD8j1JMFFsm51uymmo FX7O3xo2h7XfspAB0jXiBX/O0w== X-Google-Smtp-Source: AA+uWPynNbgSQQ9l/E1L3209WPLgCT7lV5BhDtWZ/Il0/Cm1U8gFwDoKDqPAPWZltPnd5jdW8qvJ1g== X-Received: by 2002:a63:8f03:: with SMTP id n3-v6mr2051619pgd.166.1533817978957; Thu, 09 Aug 2018 05:32:58 -0700 (PDT) Received: from localhost ([45.113.251.134]) by smtp.gmail.com with ESMTPSA id r1-v6sm20812005pfi.17.2018.08.09.05.32.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Aug 2018 05:32:58 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Subject: [PATCH v1 01/10] arm/arm64: dts: msm8974/msm8916: thermal: Split address space into two Date: Thu, 9 Aug 2018 18:02:33 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180809_053310_046009_5E9F1952 X-CRM114-Status: GOOD ( 15.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, dianders@chromium.org, rnayak@codeaurora.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, Will Deacon , smohanad@codeaurora.org, Rob Herring , bjorn.andersson@linaro.org, edubezval@gmail.com, David Brown , mka@chromium.org, Catalin Marinas , andy.gross@linaro.org, Zhang Rui , linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for the remaining platforms that have a similar register layout and make corresponding changes to the get_temp_common() function used by these platforms. Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT). This is OK since the code doesn't really use the SROT functionality yet. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke --- arch/arm/boot/dts/qcom-msm8974.dtsi | 6 ++++-- arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 ++++-- drivers/thermal/qcom/tsens-common.c | 5 +++-- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index d9019a49b292..3c4b81c29798 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -427,11 +427,13 @@ }; }; - tsens: thermal-sensor@fc4a8000 { + tsens: thermal-sensor@fc4a9000 { compatible = "qcom,msm8974-tsens"; - reg = <0xfc4a8000 0x2000>; + reg = <0xfc4a9000 0x1000>, /* TM */ + <0xfc4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; + #qcom,sensors = <11>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index cc1040eacdf5..abf84df5a7bc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -774,11 +774,13 @@ }; }; - tsens: thermal-sensor@4a8000 { + tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens"; - reg = <0x4a8000 0x2000>; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cell-names = "calib", "calib_sel"; + #qcom,sensors = <5>; #thermal-sensor-cells = <1>; }; diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 6207d8d92351..478739543bbc 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -21,7 +21,7 @@ #include #include "tsens.h" -#define S0_ST_ADDR 0x1030 +#define STATUS_OFFSET 0x30 #define SN_ADDR_OFFSET 0x4 #define SN_ST_TEMP_MASK 0x3ff #define CAL_DEGC_PT1 30 @@ -107,8 +107,9 @@ int get_temp_common(struct tsens_device *tmdev, int id, int *temp) unsigned int status_reg; int last_temp = 0, ret; - status_reg = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET; + status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * SN_ADDR_OFFSET; ret = regmap_read(tmdev->map, status_reg, &code); + if (ret) return ret; last_temp = code & SN_ST_TEMP_MASK; From patchwork Thu Aug 9 12:32:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 10561393 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 00C501390 for ; Thu, 9 Aug 2018 12:48:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E0E2A2B015 for ; Thu, 9 Aug 2018 12:48:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D4A902B020; Thu, 9 Aug 2018 12:48:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 53C5D2B015 for ; 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Thu, 09 Aug 2018 05:33:27 -0700 (PDT) Received: from localhost ([45.113.251.134]) by smtp.gmail.com with ESMTPSA id f65-v6sm23210298pfj.46.2018.08.09.05.33.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Aug 2018 05:33:27 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Subject: [PATCH v1 09/10] arm64: dts: qcom: Add reg-names for all tsens nodes Date: Thu, 9 Aug 2018 18:02:41 +0530 Message-Id: <188c07144d98bfbe2bbbb7d1f2941acdcf4e6682.1533815718.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180809_133340_418913_A083EBF6 X-CRM114-Status: GOOD ( 13.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, dianders@chromium.org, rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, Will Deacon , smohanad@codeaurora.org, Rob Herring , bjorn.andersson@linaro.org, edubezval@gmail.com, David Brown , mka@chromium.org, Catalin Marinas , andy.gross@linaro.org, linux-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Instead of showing up as thermal-sensor@, the nodes will show up as tsens0_tm, tsen1_tm, tsens1_srot, etc. in /proc/iomem making it easier to read. IOW, 0c222000-0c2221fe : thermal-sensor@c263000 0c223000-0c2231fe : thermal-sensor@c265000 0c263000-0c2631fe : thermal-sensor@c263000 0c265000-0c2651fe : thermal-sensor@c265000 becomes 0c222000-0c2221fe : tsens0_srot 0c223000-0c2231fe : tsens1_srot 0c263000-0c2631fe : tsens0_tm 0c265000-0c2651fe : tsens1_tm Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke --- arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ 4 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 3c4b81c29798..64c9f81ddd90 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -431,6 +431,7 @@ compatible = "qcom,msm8974-tsens"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ + reg-names = "tsens_tm", "tsens_srot"; nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; #qcom,sensors = <11>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index abf84df5a7bc..4e6a5e462a91 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -778,6 +778,7 @@ compatible = "qcom,msm8916-tsens"; reg = <0x4a9000 0x1000>, /* TM */ <0x4a8000 0x1000>; /* SROT */ + reg-names = "tsens_tm", "tsens_srot"; nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cell-names = "calib", "calib_sel"; #qcom,sensors = <5>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c2dca3a30091..7e5982daa2ed 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -969,6 +969,7 @@ compatible = "qcom,msm8996-tsens"; reg = <0x4a9000 0x1000>, /* TM */ <0x4a8000 0x1000>; /* SROT */ + reg-names = "tsens0_tm", "tsens0_srot"; #qcom,sensors = <13>; #thermal-sensor-cells = <1>; }; @@ -977,6 +978,7 @@ compatible = "qcom,msm8996-tsens"; reg = <0x4ad000 0x1000>, /* TM */ <0x4ac000 0x1000>; /* SROT */ + reg-names = "tsens1_tm", "tsens1_srot"; #qcom,sensors = <8>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index f722785df26b..efd5d7abd1cd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1531,6 +1531,7 @@ compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; reg = <0xc263000 0x1ff>, /* TM */ <0xc222000 0x1ff>; /* SROT */ + reg-names = "tsens0_tm", "tsens0_srot"; #qcom,sensors = <13>; #thermal-sensor-cells = <1>; }; @@ -1539,6 +1540,7 @@ compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; reg = <0xc265000 0x1ff>, /* TM */ <0xc223000 0x1ff>; /* SROT */ + reg-names = "tsens1_tm", "tsens1_srot"; #qcom,sensors = <8>; #thermal-sensor-cells = <1>; };