From patchwork Wed Nov 9 11:12:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13037396 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 193BFC433FE for ; Wed, 9 Nov 2022 11:12:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229540AbiKILMp (ORCPT ); Wed, 9 Nov 2022 06:12:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229586AbiKILMo (ORCPT ); Wed, 9 Nov 2022 06:12:44 -0500 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46EDB27CEB for ; Wed, 9 Nov 2022 03:12:43 -0800 (PST) Received: by mail-ed1-x536.google.com with SMTP id v27so26702114eda.1 for ; Wed, 09 Nov 2022 03:12:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LdDDG+VwCgLPntFF4oa/ykOGwGyduN4fHiF8yU6o5TA=; b=w4s581JvQ2Mn8GOCY2YVAROxVhZovQ9F6aNxHdQUXuymakEOCP2ZNLp6bqPiYK7s6A 4BW3fGjCZuZwV5NgN9p8Vg9pir2tqs3jr/ebZJPupmDhMxMXpJhTrMRCcVrYmypedaEE ee8A3Isajf/DU8pb9GPHuqc1u8s3bLijg/X/0inlV3eVtSSMl1mhQJZIdQQOknulHBFs 6AgTOizdTJY77Iyilk3DbIagWrgza8v513pO8KYfT1CM6Z/spqAYZdDMZsXnlrP7RXt6 qvl73H5cSVpXUFxRJFB/4qwcz/cBhYWfLKzvRdwr57mWPxV+Em9gbbnZUXecwwcYYkmG aLlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LdDDG+VwCgLPntFF4oa/ykOGwGyduN4fHiF8yU6o5TA=; b=uabQgr6U4WXr6WTkOh3IN6cvySg25RZibiS7/8Lc5SGKaEhxEIniPc9RtZpEo8NKpn IVNXvw7SUgJqXt45IUuz+LN4+ia8INamKVvGO8fdu9Oe9w7KoL29l8gckgtR5H2Cjzge 5eJu0zdUID5wUF6LzBK+ZYS1ghv0KQfTQR0z0dK1uPPCqfJsKaJuyriNqocT1CehxoH9 p70N4SlWG2OsTWKykazys3LTbEr9C2IhYxa6zGN7hXE6xIp177oMTtMe3/E17Ttcp2mo HYeIcwt07Yt98m7+FLzHCGFhO5eCwP2nJ+ctlYNDK1dlMU5WWGuFeiv9r5rGfb98JWNW IqEg== X-Gm-Message-State: ACrzQf2oyyWCSDMBOxh6nl/WuxD/Ce3aw7A/jrzI4zppz0K8GsNHgmG0 Le8w4YMhTrQtOxlOBWVe5kBnAMyucrTlYVSi X-Google-Smtp-Source: AMsMyM6s7MoJlv0Fg8yZvsH1IMDvfa7NtIwgSGlQvWA4gVOn/ZBLMC2W12W0VttsA8gaNjq3FwuIZw== X-Received: by 2002:aa7:ca50:0:b0:461:9845:d9d2 with SMTP id j16-20020aa7ca50000000b004619845d9d2mr59012120edt.163.1667992361655; Wed, 09 Nov 2022 03:12:41 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id k8-20020a1709062a4800b007ad9c826d75sm5825899eje.61.2022.11.09.03.12.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Nov 2022 03:12:41 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/10] dt-bindings: arm-smmu: Allow up to 3 power-domains Date: Wed, 9 Nov 2022 12:12:26 +0100 Message-Id: <20221109111236.46003-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221109111236.46003-1-konrad.dybcio@linaro.org> References: <20221109111236.46003-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some SMMUs require that a vote is held on as much as 3 separate PDs (hello Qualcomm). Allow it in bindings. Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 9066e6df1ba1..1897d0d4d820 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -159,7 +159,7 @@ properties: through the TCU's programming interface. power-domains: - maxItems: 1 + maxItems: 3 nvidia,memory-controller: description: | From patchwork Wed Nov 9 11:12:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13037397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9512C43219 for ; Wed, 9 Nov 2022 11:12:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229588AbiKILMs (ORCPT ); Wed, 9 Nov 2022 06:12:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229669AbiKILMq (ORCPT ); Wed, 9 Nov 2022 06:12:46 -0500 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAE6127CEB for ; Wed, 9 Nov 2022 03:12:44 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id l11so26693492edb.4 for ; Wed, 09 Nov 2022 03:12:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f/pc7jhWkIohCmzvLPeFxuZOhmufYr1Nl7f4rSC4zF4=; b=CuYAPoJXdqq8N/Hkqw6+Dyphx6DZiSKDjujPOlLyWRAxasWQOjLGr0mDvDWXoz0LfG wd/cMAMguAOFiOumC2hM7NQhgDNWyucdDdBhx1PBoqFhG9rQKfUsjRbWMBTWDao31/Tg Xnyzbg6Alum5LrezL0ZhqG+bsaka3rGY4Ml5QHHrbdMxBJft0Ul42cT0TDRvPikeulk2 Wh6kyjBF0Z6TOY2Ab081x7OjhMv05XhAHbELPiMGftSpoJUpYyuCs968qPwY2o1PDfiJ Bfhgc4K491D9RUQ2zyN7ClaRF2KojHazUQ5NfCSSS8FSWlXR/xUGgReuaIiyk0h0Ccyu DLIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f/pc7jhWkIohCmzvLPeFxuZOhmufYr1Nl7f4rSC4zF4=; b=6c7bwcQc5nAWMJ9iL6V81gRrO5W2v4xxqgKOJEASV8L4Etxdbm5iJKhIe1bzo+XnBn Q/nJXxu/P9wWOWq0qhfFAiwdKekMpYf9QjmHDHa3D4YHfN3S/FF0eDos4ZX16i1ngrWM K6XVGZBTo+L356uSsXGOfDeRSRcfWktdS9RNy0D5TzDczf8Kf63UJSWSg1H/4xCRWXSG PJ6hFfsE5dZB4eZPx7dHCfvgNVL7/8klpiVinzgdGtVonLYaAVyW0qTJUiaJs6CHi40w GEvqw1183YILYsSroBEhhuLlTSlOT8HZyRsgKzBq2p3rU2BTG3uKRO94PNX/zGtkkUpX DJvQ== X-Gm-Message-State: ACrzQf2q9p4VNRyATnI1+AYKdlgvxxbzVdH97WQtqB87SYAqnATc+BEd tirWcmscqhxTAtKiX/4eDnAAoOmzhlVi7OYF X-Google-Smtp-Source: AMsMyM7GeVr/zvBHi6rK2a85LLgMSVm6NEWavbdp+4Oo2zE/I5mfFViR3XR+UwerJ7HyyO3kN5UJqw== X-Received: by 2002:a05:6402:2793:b0:462:39d7:3bbc with SMTP id b19-20020a056402279300b0046239d73bbcmr59490539ede.47.1667992363232; Wed, 09 Nov 2022 03:12:43 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id k8-20020a1709062a4800b007ad9c826d75sm5825899eje.61.2022.11.09.03.12.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Nov 2022 03:12:42 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Vinod Koul , Rob Herring , Krzysztof Kozlowski , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/10] dt-bindings: dmaengine: qcom: gpi: add compatible for SM6375 Date: Wed, 9 Nov 2022 12:12:27 +0100 Message-Id: <20221109111236.46003-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221109111236.46003-1-konrad.dybcio@linaro.org> References: <20221109111236.46003-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the compatible for GPI DMA controller on SM6375 SoC. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index 232895fa1d8d..e7ba1c47a88e 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -26,6 +26,7 @@ properties: - enum: - qcom,sc7280-gpi-dma - qcom,sm6115-gpi-dma + - qcom,sm6375-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma - const: qcom,sm6350-gpi-dma From patchwork Wed Nov 9 11:12:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13037398 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 685BFC433FE for ; Wed, 9 Nov 2022 11:12:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229993AbiKILMx (ORCPT ); Wed, 9 Nov 2022 06:12:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229853AbiKILMu (ORCPT ); Wed, 9 Nov 2022 06:12:50 -0500 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE33127CEB for ; Wed, 9 Nov 2022 03:12:48 -0800 (PST) Received: by mail-ed1-x536.google.com with SMTP id z18so26682599edb.9 for ; Wed, 09 Nov 2022 03:12:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dw8yiTzUnE0/1jed/kvyGb1dCoZQTp6ZbqhV1sxsfZ0=; b=LgW7dKax1lUQHPezWxwMRSeDeHZcYqMQBQqKjPC55A582VnN+e75uJI772OUM4vS6A zf9WuuxvZUZ9YCXKczzJ4tNiiiZXrkaAjARV7vJfp80FasOdqBIqIRaCLavH07eQGFj9 iIlBLdHzhkbGnrHkDVR+fE7/l3m4V+YSkRJdc2QOCip4Wjhf+LlfWEMhCaYqP9tjGL1i Uc57G1u09ZU+8s0WakgNHJ+I9azokFhmdQjx9yqO3yDpiOqT4BbfUp7FzWUvjlRVnjUl uxH55k5Cf7gpVa0/FLQsgx6mFFvxA+gUYTJIvvobMeJEK+H7sXBSWxfkM5IW1WuNzq6p Wncw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dw8yiTzUnE0/1jed/kvyGb1dCoZQTp6ZbqhV1sxsfZ0=; b=KV5xIRGupdlRyRlLXo9p8ZSKXHUCbuHo+g7993tvspQpLBz70HwFDPpq9fPPsRn26P fVpLyIL3tp2Zo1inlx+XNUwSUsDNHYUPq1FJt1KLV8X83EvGMxba/HzZQz6nksLibkSA eFj7zB5ZzhenjBcUWNW73mD2PuGiIc1ZBTMu5/UEjQw1rUbwW6gc0g6F3nnfJfjKQK2s aQwUcMeSf6wB6jEjzVTGhuLvy2YI0iuaE5bEO1Z17ullVoJ7TM/JUQ9GldjMGa7+8pHY +vRpMavC5gmgA4nmAGjS0AfsZv5e9RS1l4eDcTN5pLxjo5/ZvBSIBCHKzl4ktBZxoYZ3 LtQw== X-Gm-Message-State: ACrzQf06v6C/ndJFE9ZP6qjTuxN1rYre1XXkv1GtHQJ/KhlDvCknbEwL yR68L7P/IFohhI6ZRjUVuku75FglMzuKQ4lB X-Google-Smtp-Source: AMsMyM4AkeeOBGLFE9c17vhZZpE95yA+NmUlhsM0m0/uy0qQjk/oLXIWqskqcLe4+RlXjAkxr4ZVnA== X-Received: by 2002:a50:c302:0:b0:463:26d6:25fb with SMTP id a2-20020a50c302000000b0046326d625fbmr55347903edb.204.1667992367157; Wed, 09 Nov 2022 03:12:47 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id k8-20020a1709062a4800b007ad9c826d75sm5825899eje.61.2022.11.09.03.12.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Nov 2022 03:12:46 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/10] arm64: dts: qcom: Add a device tree for PMK8350 on SID6 Date: Wed, 9 Nov 2022 12:12:28 +0100 Message-Id: <20221109111236.46003-4-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221109111236.46003-1-konrad.dybcio@linaro.org> References: <20221109111236.46003-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PMK8350 is shipped on SID6 with some SoCs, for example with SM6375. Add a DT with the SID changed to allow it to work. Unfortunately, the entire DT needs to be copied even if the diff is very little, as the node names are not unique. Including pm6125 and pmk8350 together for example, would make pmk8350 overwrite the pm6125 node, as both are defined as 'pmic@0'. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmk8350_sid6.dtsi | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmk8350_sid6.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmk8350_sid6.dtsi b/arch/arm64/boot/dts/qcom/pmk8350_sid6.dtsi new file mode 100644 index 000000000000..00390f8b9c97 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmk8350_sid6.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include + +&spmi_bus { + pmk8350: pmic@6 { + compatible = "qcom,pmk8350", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8350_pon: pon@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>; + + pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x6 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + status = "disabled"; + }; + + pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x6 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; + }; + + pmk8350_vadc: adc@3100 { + compatible = "qcom,spmi-adc7"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x6 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells = <1>; + }; + + pmk8350_adc_tm: adc-tm@3400 { + compatible = "qcom,adc-tm7"; + reg = <0x3400>; + interrupts = <0x6 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + pmk8350_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x6 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + pmk8350_gpios: gpio@b000 { + compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio"; + reg = <0xb000>; + gpio-controller; + gpio-ranges = <&pmk8350_gpios 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From patchwork Wed Nov 9 11:12:29 2022 Content-Type: text/plain; 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Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 9b1a497e5ca7..62a64dd731a0 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -567,6 +567,46 @@ rpm_msg_ram: sram@45f0000 { reg = <0 0x045f0000 0 0x7000>; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x16 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + gpi_dma1: dma-controller@4c00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04c00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0xd6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Wed Nov 9 11:12:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13037400 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D363DC433FE for ; Wed, 9 Nov 2022 11:13:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230226AbiKILNF (ORCPT ); Wed, 9 Nov 2022 06:13:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230046AbiKILMz (ORCPT ); Wed, 9 Nov 2022 06:12:55 -0500 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0116529803 for ; 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Wed, 09 Nov 2022 03:12:49 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/10] arm64: dts: qcom: sm6375: Add pin configs for some QUP configurations Date: Wed, 9 Nov 2022 12:12:30 +0100 Message-Id: <20221109111236.46003-6-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221109111236.46003-1-konrad.dybcio@linaro.org> References: <20221109111236.46003-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the pin setup for SPI/I2C configurations that are supported downstream. I can guesstimate the correct settings for other buses, but: - I have no hardware to test it on - Some QUPs are straight up missing pin funcs in TLMM - Vendors probably didn't really care and used whatever was there in the reference design and BSP - should any other be used, they can be configured at a later time Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 62a64dd731a0..952156891476 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -519,6 +519,49 @@ tlmm: pinctrl@500000 { gpio-controller; #interrupt-cells = <2>; #gpio-cells = <2>; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup00"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio61", "gpio62"; + function = "qup01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio45", "gpio46"; + function = "qup02"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio19", "gpio20"; + /* TLMM, GCC and vendor DT all have different indices.. */ + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio4", "gpio5"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup00"; + drive-strength = <6>; + bias-disable; + }; }; gcc: clock-controller@1400000 { From patchwork Wed Nov 9 11:12:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13037401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84B27C433FE for ; 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Wed, 09 Nov 2022 03:12:51 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/10] arm64: dts: qcom: sm6375: Add QUPs and corresponding SPI/I2C hosts Date: Wed, 9 Nov 2022 12:12:31 +0100 Message-Id: <20221109111236.46003-7-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221109111236.46003-1-konrad.dybcio@linaro.org> References: <20221109111236.46003-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add necessary nodes to support various QUP configurations. Note that: - QUP3/4/5 and 11 are straight up missing - There may be more QUPs physically on the SoC that work perfectly fine, but Qualcomm decided not to expose them on the downstream kernel - Many are missing pinctrls, as there are both missing pin funcs in the TLMM driver and missing configuration settings (though they are possible to guesstimate quite easily) Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 306 +++++++++++++++++++++++++++ 1 file changed, 306 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 952156891476..6adffd927a8e 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -317,6 +318,25 @@ CLUSTER_PD: cpu-cluster0 { }; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -630,6 +650,125 @@ gpi_dma0: dma-controller@4a00000 { status = "disabled"; }; + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* + * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. + * There is a comment in the included DTSI of another SoC saying that they + * are not "bolled out" (probably meaning not routed to solder balls) + * TLMM driver however, suggests there are as many as 15 QUPs in total! + * Most of which don't even have pin configurations for.. Sad stuff! + */ + }; + gpi_dma1: dma-controller@4c00000 { compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x04c00000 0 0x60000>; @@ -650,6 +789,173 @@ gpi_dma1: dma-controller@4c00000 { status = "disabled"; }; + qupv3_id_1: geniqup@4cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04cc0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xc3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c6: i2c@4c80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@4c80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@4c84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@4c84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@4c88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@4c88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@4c8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@4c8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@4c90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@4c90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Wed Nov 9 11:12:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13037402 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 872C4C4332F for ; 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Wed, 09 Nov 2022 03:12:53 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/10] arm64: dts: qcom: sm6375-pdx225: Enable QUPs & GPI DMA Date: Wed, 9 Nov 2022 12:12:32 +0100 Message-Id: <20221109111236.46003-8-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221109111236.46003-1-konrad.dybcio@linaro.org> References: <20221109111236.46003-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable QUPs & GPI DMA on the Xperia 10 IV. Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 450d4a557df1..6a0f4c0bf7ad 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -65,6 +65,22 @@ vph_pwr: vph-pwr-regulator { }; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <13 4>; }; From patchwork Wed Nov 9 11:12:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13037404 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1DFDC4332F for ; Wed, 9 Nov 2022 11:13:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230407AbiKILN2 (ORCPT ); Wed, 9 Nov 2022 06:13:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230288AbiKILNL (ORCPT ); Wed, 9 Nov 2022 06:13:11 -0500 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C8F82A270 for ; Wed, 9 Nov 2022 03:12:56 -0800 (PST) Received: by mail-ed1-x52c.google.com with SMTP id a13so26755237edj.0 for ; Wed, 09 Nov 2022 03:12:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6f2LrcsgR15wJRkGdfTFJiQo01CUBHznKnMZobnWz+8=; b=jbeyJb5ob7NpZGkqriRapnKnilBk48C5JhljQ5fysKxijGd2YrjVhDc4KEULFyP15l sMYkOaMXKOn7XT4SRpZuu7pF9+0Yo/Hi8kub+wPqNpnsgmQSf1C+EOFzPpPriONysYvx JHnaB7k5buWjcm08TtjSlTMsF1IU8KM+uNmYVWXmzGl3yOJDyTgzXd6Zsuq5eF1cZQyq eDk9YK62Z6nOMMRbgAlKx1k/Ro3xxNMMiXtCJDyPu5C4pce5oJBF6xXcdfx9MGooUZHS RIufoOyma4fUeTd6J1wLlSnCUiEMIgTIkcTwioO2ktABPTLsCvzDu+MgZGPAPOAgZB32 CCNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6f2LrcsgR15wJRkGdfTFJiQo01CUBHznKnMZobnWz+8=; b=yaGomD6N2y6HmyAvX+MnCtK7i2H/muINYb3IKXwHXxKR8tc4k/DfG9Hprxv66kQkrD 4sIDWdpHhB95UQb58sz84IZT61yox/iHDagKQFUDTFYK8kA59K5vUZsL7xda8KDqjBZr LzjqUj539yYp8k1V2onAty3TXveWkZ8bbsLBLq/jvrOrreK/Qk3+/XaO8QIkZuVxGv6T zxzOvL3azmM5gJ4PiO7/I+O55+LpQ8+Ee8l5qyoCauQpNP2UjST8ZydqY/zWTA23L/8q Ya3FcTZX/7713TZ5Em/VzEGBaHiOf7Da+r+tq1OoaElHtPfWdqBw5fxIcEOECz302bXX ascg== X-Gm-Message-State: ACrzQf1mkK0FRn9s9Li55SgDkON2QL7VrtjoFkNBfTuo1OCFLfhvAdQA TomgA9iv0hqS8C5ChmcG3wW7fvDER0X2ay3A X-Google-Smtp-Source: AMsMyM7lel/1OkX5J/4oo4yUmP8DjOI1S49KUGKyvOTnAOCgmrD8bXdNyuDs6sWYCHTsy1N9aquLdQ== X-Received: by 2002:a05:6402:274c:b0:461:9cbd:8ad5 with SMTP id z12-20020a056402274c00b004619cbd8ad5mr60295954edd.349.1667992374978; Wed, 09 Nov 2022 03:12:54 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id k8-20020a1709062a4800b007ad9c826d75sm5825899eje.61.2022.11.09.03.12.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Nov 2022 03:12:54 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/10] arm64: dts: qcom: sm6375-pdx225: Add PMIC peripherals Date: Wed, 9 Nov 2022 12:12:33 +0100 Message-Id: <20221109111236.46003-9-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221109111236.46003-1-konrad.dybcio@linaro.org> References: <20221109111236.46003-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add and enable PMIC peripherals for PM6125, PMR735a and PMK8350 on the Xperia 10 IV. Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 6a0f4c0bf7ad..d34b4b96e1b9 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -7,8 +7,13 @@ #include #include "sm6375.dtsi" +#include "pm6125.dtsi" +#include "pmk8350_sid6.dtsi" #include "pmr735a.dtsi" +/* PM6125 PON is used and we can't have duplicate labels */ +/delete-node/ &pmk8350_pon; + / { model = "Sony Xperia 10 IV"; compatible = "sony,pdx225", "qcom,sm6375"; @@ -73,6 +78,23 @@ &gpi_dma1 { status = "okay"; }; +&pmk8350_adc_tm { + status = "okay"; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Wed Nov 9 11:12:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13037403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C4A4C433FE for ; Wed, 9 Nov 2022 11:13:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230402AbiKILN1 (ORCPT ); Wed, 9 Nov 2022 06:13:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230285AbiKILNL (ORCPT ); Wed, 9 Nov 2022 06:13:11 -0500 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CF6F29836 for ; Wed, 9 Nov 2022 03:12:57 -0800 (PST) Received: by mail-ej1-x62c.google.com with SMTP id ft34so9382108ejc.12 for ; Wed, 09 Nov 2022 03:12:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qBu0DAqnkYkL46/OegDUIMhoEPze3QFWuGsvoEBwl2o=; b=gVtzcJ1byX8sZ9YhGkkBHz4BPLUdhB/GBMuoiJKeMG3vwJnn0sVv9lpDp6qHnhtFwn 7Pk59pAhnJJTq+tYRRWQ5ChctRlux3yUChdvGcPwwhHVCimfKK/7XnJFuaqp3g048hGe 7RkOT20iOCiBQa5oIAbpX76l26IfatlYmP0fsESP3KeT3ogJBW3l/4jlKqBRD0QpVtbs p7Q7dvXsp46DFfN2fsiWbqt3hpUZ1yrD1EXWKVRIVzTUNrMPL3MnXDfuaZ9hf9Tk3RlD Fbugwhrm09Qq6G5JzGX6H+qAy323n1sj7NcWyQDGwRznHy5tfGOLddL6F9gNMKQew0Cz x/pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qBu0DAqnkYkL46/OegDUIMhoEPze3QFWuGsvoEBwl2o=; b=1Gtsd/jwN5wo4r8LxjSDUUZNpM4tNt9ckZ0s/Z+PUDfo8llQ9fl09WvZ9GzYRDZstK OETeusjWhQV7UpwG4UcqMKf8KGNkrW7SEsLITMb0FaN9EgCDKIk/bwyrXZAOIl7JcpPt kP5SLG/mZ6ez6Lb+bw3pUi0e9XDOrzgy8qz78Ebh7XcuU+oJEni0URpGcEp5Jn1XEqtz 6TWPbrGUCxyWhorawK48fT6o4cmnHQxSLEsSbcrTx4Ylydg/djKIgX+OCKISaTeO79Fu JcvZHKEcQKQgsqDDAbMmVESQ3Kr/UXtHuMq2RlAYDAXf7Ct3wnTBZQWBqu21dp/HbFNY DhJQ== X-Gm-Message-State: ACrzQf1+sMUpPtRp2Te3PoRdnLMVSTZnOEjiNWij7wc6lybYo8YnyWAy qkEVgzMFKIbMVzpdUT3xgllT/z15dWypj9jv X-Google-Smtp-Source: AMsMyM4w7fwX852mFaI/PVuvOoFvMYsBNRUhjoiOvMM3yx/cLRntUQ2JTgNFVwUtnEKMfdSWZ6ac8A== X-Received: by 2002:a17:906:5a49:b0:7ad:d063:901a with SMTP id my9-20020a1709065a4900b007add063901amr48974054ejc.323.1667992376546; Wed, 09 Nov 2022 03:12:56 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id k8-20020a1709062a4800b007ad9c826d75sm5825899eje.61.2022.11.09.03.12.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Nov 2022 03:12:56 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/10] arm64: dts: qcom: sm6375-pdx225: Configure SMD RPM regulators Date: Wed, 9 Nov 2022 12:12:34 +0100 Message-Id: <20221109111236.46003-10-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221109111236.46003-1-konrad.dybcio@linaro.org> References: <20221109111236.46003-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Configure regulators present on the Xperia 10 IV that are reachable via SMD RPM. Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 182 ++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index d34b4b96e1b9..17094e588a3a 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -95,6 +95,188 @@ &pon_resin { status = "okay"; }; +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + pm6125_s5: s5 { + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1120000>; + }; + + pm6125_s6: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1374000>; + }; + + pm6125_s7: s7 { + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + }; + + /* + * S8 is VDD_GFX + * L1 is VDD_LPI_CX + */ + + pm6125_l2: l2 { + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l3: l3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l4: l4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l5: l5 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3050000>; + }; + + pm6125_l6: l6 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l7: l7 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + pm6125_l8: l8 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l9: l9 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l10: l10 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l11: l11 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l12: l12 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l13: l13 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l14: l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + pm6125_l15: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l16: l16 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + /* L17 is VDD_LPI_MX */ + + pm6125_l18: l18 { + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + pm6125_l19: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l20: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l21: l21 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l22: l22 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pmr735a-regulators"; + + /* + * S1 is VDD_MX + * S2 is VDD_CX + */ + + pmr735a_l1: l1 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + pmr735a_l2: l2 { + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <796000>; + }; + + pmr735a_l3: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pmr735a_l4: l4 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pmr735a_l5: l5 { + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + pmr735a_l6: l6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <868000>; + }; + + pmr735a_l7: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + }; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Wed Nov 9 11:12:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13037405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C1EDC433FE for ; Wed, 9 Nov 2022 11:13:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230440AbiKILNf (ORCPT ); Wed, 9 Nov 2022 06:13:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230208AbiKILNP (ORCPT ); Wed, 9 Nov 2022 06:13:15 -0500 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3E8829C9B for ; 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Wed, 09 Nov 2022 03:12:57 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/10] arm64: dts: qcom: sm6375-pdx225: Configure Samsung touchscreen Date: Wed, 9 Nov 2022 12:12:35 +0100 Message-Id: <20221109111236.46003-11-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221109111236.46003-1-konrad.dybcio@linaro.org> References: <20221109111236.46003-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a pretty bog-standard-for-Xperias-for-the-past-3-years touchscreen setup. The OEM that built the Xperia 10 IV for SONY decided to use some kind of a GPIO regulator that needs to be enabled at all times for both the touch panel and the display panel to function. Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 17094e588a3a..33083f18755b 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -78,6 +78,23 @@ &gpi_dma1 { status = "okay"; }; +&i2c8 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + + vdd-supply = <&pm6125_l13>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default &ts_avdd_default>; + }; +}; + &pmk8350_adc_tm { status = "okay"; }; @@ -287,6 +304,20 @@ &qupv3_id_1 { &tlmm { gpio-reserved-ranges = <13 4>; + + ts_int_default: ts-int-default-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_avdd_default: ts-avdd-default-state { + pins = "gpio59"; + function = "gpio"; + drive-strength = <8>; + output-high; + }; }; &usb_1 {