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([94.12.112.226]) by smtp.gmail.com with ESMTPSA id v18-20020adfe292000000b00228dbf15072sm13331922wri.62.2022.11.09.06.30.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Nov 2022 06:30:13 -0800 (PST) From: Mark Jackson To: =?utf-8?q?Beno=C3=AEt_Cousson?= , Tony Lindgren , Mark Jackson , Rob Herring , Krzysztof Kozlowski , linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: dts: Update Nanobone DTS Date: Wed, 9 Nov 2022 14:30:03 +0000 Message-Id: <20221109143003.81463-1-mpfj@newflow.co.uk> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Update Nanobone DTS file as follows:- - Fix GPIO settings for RTS/CTS pins on UART3 & 4 - Enable RS485 mode for UART3 & 4 - Enable LM75 temperature sensor - Fix GPIO settings for MMC pins - Enable USB --- arch/arm/boot/dts/am335x-nano.dts | 33 +++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index b6f2567bd65a..1f613e879c53 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -120,8 +120,8 @@ AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd uart3_pins: uart3_pins { pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data10.gpio2[16] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) /* lcd_data11.gpio2[17] */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ >; @@ -129,8 +129,8 @@ AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in uart4_pins: uart4_pins { pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data12.gpio0[8] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) /* lcd_data13.gpio0[9] */ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */ >; @@ -188,12 +188,22 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; status = "okay"; + rts-gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rx-during-tx; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins>; status = "okay"; + rts-gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rx-during-tx; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; }; &uart5 { @@ -220,6 +230,12 @@ tps: tps@24 { reg = <0x24>; }; + lm75@48 { + compatible = "lm75"; + reg = <0x48>; + status = "okay"; + }; + eeprom@53 { compatible = "microchip,24c02", "atmel,24c02"; reg = <0x53>; @@ -403,8 +419,13 @@ &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; bus-width = <4>; - cd-gpios = <&gpio3 8 0>; - wp-gpios = <&gpio3 18 0>; + cd-debounce-delay-ms = <5>; + cd-gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +}; + +&usb0 { + dr_mode = "host"; }; #include "tps65217.dtsi"