From patchwork Thu Nov 17 10:52:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13046572 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76A8FC43217 for ; Thu, 17 Nov 2022 10:53:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239622AbiKQKxn (ORCPT ); Thu, 17 Nov 2022 05:53:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234058AbiKQKxG (ORCPT ); Thu, 17 Nov 2022 05:53:06 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D51275E9E5; Thu, 17 Nov 2022 02:52:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668682377; x=1700218377; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gNtn9WfsbwYVLh4+RkqUoRwPVNMtyYltmpBOWMDfWsw=; b=sRHyVYoFhEXKVU58uS4G4lS9tKNIIeHwI7o5d1sT6uHzqZotaqPR8JgY GE5VuxTTjqUNDlJ7/9y165D2U/voNyLsmf+U3qT8CFObA+3zkyl9c3W5D RNxPujqFzSGS1bPWzk2/+YPG/i0pxiKfMOOfvqJKVv4EfG07tk88kcIS2 DK8gje8bJKJAPN5UtIPWxHw2ReVTh8UX8OUwjDkEO2rJNEfgVQerhu7q9 UzkSE6EIshgToMfLPyy+OoqLBxcQSfn2a1IbIA7Zw9LnnYhBP/4TIwle+ Z4s8nKRzsya8PHEyqlK+GFkauoQBzKNe+bAeWCLcWcL7EQ3YRCOwHnvgF A==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="123873129" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 03:52:56 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 03:52:56 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:52:53 -0700 From: Tudor Ambarus To: , , , , , CC: , , , , , Tudor Ambarus Subject: [PATCH 1/8] spi: dt-bindings: Introduce spi-cs-setup-ns property Date: Thu, 17 Nov 2022 12:52:42 +0200 Message-ID: <20221117105249.115649-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com> References: <20221117105249.115649-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org SPI NOR flashes have specific cs-setup time requirements without which they can't work at frequencies close to their maximum supported frequency, as they miss the first bits of the instruction command. Unrecognized commands are ignored, thus the flash will be unresponsive. Introduce the spi-cs-setup-ns property to allow spi devices to specify their cs setup time. Signed-off-by: Tudor Ambarus --- .../devicetree/bindings/spi/spi-peripheral-props.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index dca677f9e1b9..ead2cccf658f 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -44,6 +44,11 @@ properties: description: Maximum SPI clocking speed of the device in Hz. + spi-cs-setup-ns: + description: + Delay in nanosecods to be introduced by the controller after CS is + asserted. + spi-rx-bus-width: description: Bus width to the SPI bus used for read transfers. From patchwork Thu Nov 17 10:52:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13046573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 900E4C4332F for ; Thu, 17 Nov 2022 10:53:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239378AbiKQKxn (ORCPT ); Thu, 17 Nov 2022 05:53:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239321AbiKQKxG (ORCPT ); Thu, 17 Nov 2022 05:53:06 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 845D05E9FA; Thu, 17 Nov 2022 02:53:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668682381; x=1700218381; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pNGHdixQJ8kphWteopGCeA+0rgR0b/xkVnhBdzmmawA=; b=J9vZ00vo4O562sGrr9HkM+ApUT/RJYNA4qwTwf3PoIVCfpBknhJTc3OI AxhEnkkc0Yv5h7KQ80VgVwBPEgO2PfbNjAPj4JnBc02Lb5VwVipVYl1Fu z635yxzentFqyexrBYq4q5/ptKyN6mdKA0aKN+bCBO6POV4b4ri6FLAdW tddWBwSBhWes642mzi05usUABB9jvyy8G4izjqIYQOk6tbaaK+Nkg/dEj 1KE5bhL8raydCqY5YXWAMaL8PHVwi/iuEIavDDlKGzqg56JaH7Zq9KbTy hUKoPAIPXZ5kpAEu5K1K0089fZizyNUoGTFUan194lUzvBHGAYgHhZO17 g==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="183965612" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 03:53:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 03:52:59 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:52:56 -0700 From: Tudor Ambarus To: , , , , , CC: , , , , , Tudor Ambarus Subject: [PATCH 2/8] spi: Introduce spi-cs-setup-ns property Date: Thu, 17 Nov 2022 12:52:43 +0200 Message-ID: <20221117105249.115649-3-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com> References: <20221117105249.115649-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org SPI NOR flashes have specific cs-setup time requirements without which they can't work at frequencies close to their maximum supported frequency, as they miss the first bits of the instruction command. Unrecognized commands are ignored, thus the flash will be unresponsive. Introduce the spi-cs-setup-ns property to allow spi devices to specify their cs setup time. Signed-off-by: Tudor Ambarus --- drivers/spi/spi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 4ddd250481f5..b93a6085d9a0 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2224,6 +2224,7 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, struct device_node *nc) { u32 value; + u16 cs_setup; int rc; /* Mode (clock phase/polarity/etc.) */ @@ -2309,6 +2310,11 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, if (!of_property_read_u32(nc, "spi-max-frequency", &value)) spi->max_speed_hz = value; + if (!of_property_read_u16(nc, "spi-cs-setup-ns", &cs_setup)) { + spi->cs_setup.value = cs_setup; + spi->cs_setup.unit = SPI_DELAY_UNIT_NSECS; + } + return 0; } From patchwork Thu Nov 17 10:52:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13046574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DC9CC433FE for ; Thu, 17 Nov 2022 10:53:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239647AbiKQKxq (ORCPT ); Thu, 17 Nov 2022 05:53:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239368AbiKQKxM (ORCPT ); Thu, 17 Nov 2022 05:53:12 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB62418B1E; Thu, 17 Nov 2022 02:53:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668682385; x=1700218385; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PTd3Xp7lnmGYxmQRmdmHm6G+V0PfC+jWfJFuvF44HB8=; b=DT/s+jRTftfi9Bdcsv/fhjNmRmpTxkSwR2lFG2505M4h3dyNYvUZjqY8 wsCmGonx25ady+M7bsp7w5qwpMQ7X85CY2IOp4XIuMWCGVStt+DZ8+Mbk NdTkYvZ3Dx0TOd6FNwPGhLzIK7JnBFbK9X/KXb+1uzZazGzHtL6mGOV5y QBF46kbPBy4jQwNyXHIAcrqNXsnZBfeywi+kYwNRXF6dk+BivCccmE3S6 Ktxa28pOGLHlIB9PP3yoFFUlgAyvyXavytQtsK6tKOrYZgWI+Xes6JUpn CgXYl+iyknQ7F3InUnE8tmGJYu+cczv7JbMT/Y9R/1HPBtwlild7xSroa w==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="183965621" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 03:53:04 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 03:53:02 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:52:59 -0700 From: Tudor Ambarus To: , , , , , CC: , , , , , Tudor Ambarus Subject: [PATCH 3/8] spi: Reintroduce spi_set_cs_timing() Date: Thu, 17 Nov 2022 12:52:44 +0200 Message-ID: <20221117105249.115649-4-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com> References: <20221117105249.115649-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org commit 4ccf359849ce ("spi: remove spi_set_cs_timing()"), removed the method as noboby used it. Nobody used it probably because some SPI controllers use some default large cs-setup time that covers the usual cs-setup time required by the spi devices. There are though SPI controllers that have a smaller granularity for the cs-setup time and their default value can't fulfill the spi device requirements. That's the case for the at91 QSPI IPs where the default cs-setup time is half of the QSPI clock period. This was observed when using an sst26vf064b SPI NOR flash which needs a spi-cs-setup-ns = <7>; in order to be operated close to its maximum 104 MHz frequency. Call spi_set_cs_timing() in spi_setup() just before calling spi_set_cs(), as the latter needs the CS timings already set. If spi->controller->set_cs_timing is not set, the method will return 0. There's no functional impact expected for the existing drivers. Even if the spi-mt65xx.c and spi-tegra114.c drivers set the set_cs_timing method, there's no user for them as of now. The only tested user of this support will be a SPI NOR flash that comunicates with the Atmel QSPI controller for which the support follows in the next patches. One will notice that this support is a bit different from the one that was removed in commit 4ccf359849ce ("spi: remove spi_set_cs_timing()"), because this patch adapts to the changes done after the removal: the move of the cs delays to the spi device, the retirement of the lelgacy GPIO handling. The mutex handling was removed from spi_set_cs_timing() because we now always call spi_set_cs_timing() in spi_setup(), which already handles the spi->controller->io_mutex, so use the mutex handling from spi_setup(). Signed-off-by: Tudor Ambarus --- drivers/spi/spi.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index b93a6085d9a0..3cc7bb4d03de 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -3621,6 +3621,37 @@ static int __spi_validate_bits_per_word(struct spi_controller *ctlr, return 0; } +/** + * spi_set_cs_timing - configure CS setup, hold, and inactive delays + * @spi: the device that requires specific CS timing configuration + * + * Return: zero on success, else a negative error code. + */ +static int spi_set_cs_timing(struct spi_device *spi) +{ + struct device *parent = spi->controller->dev.parent; + int status = 0; + + if (spi->controller->set_cs_timing && !spi->cs_gpiod) { + if (spi->controller->auto_runtime_pm) { + status = pm_runtime_get_sync(parent); + if (status < 0) { + pm_runtime_put_noidle(parent); + dev_err(&spi->controller->dev, "Failed to power device: %d\n", + status); + return status; + } + + status = spi->controller->set_cs_timing(spi); + pm_runtime_mark_last_busy(parent); + pm_runtime_put_autosuspend(parent); + } else { + status = spi->controller->set_cs_timing(spi); + } + } + return status; +} + /** * spi_setup - setup SPI mode and clock rate * @spi: the device whose settings are being modified @@ -3717,6 +3748,12 @@ int spi_setup(struct spi_device *spi) } } + status = spi_set_cs_timing(spi); + if (status) { + mutex_unlock(&spi->controller->io_mutex); + return status; + } + if (spi->controller->auto_runtime_pm && spi->controller->set_cs) { status = pm_runtime_resume_and_get(spi->controller->dev.parent); if (status < 0) { From patchwork Thu Nov 17 10:52:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13046575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87AF5C433FE for ; Thu, 17 Nov 2022 10:54:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239657AbiKQKyB (ORCPT ); Thu, 17 Nov 2022 05:54:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239518AbiKQKxO (ORCPT ); Thu, 17 Nov 2022 05:53:14 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D942E5ADE2; Thu, 17 Nov 2022 02:53:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668682390; x=1700218390; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IV3iY/5nH2v6r5LMDzPfNG3LT1Nn/MAxR36s7csPy5k=; b=U9kX07y6nRcNudQwmHcO4ZBs1IB8awZk2TdS44EIWq32WbLdjGt0we0/ 0UMb/QjkbrCkk7T4ByizojGgYFdEGl+DygYDHu8RsChRhXIvkiaz5SZGc RZ1IMN9o+xfXORuhUNgmA8wjuOZ4RIc1mzrN/jslijHdcTVX+2Y2hsQy5 +zceDMnnPqWE2HXZOcZW2ASBAnKepI/BPB8kNqk6zUzQJ+7ksY6KQfebq q7Q6Nr3luWoo3MSJ7iNWcnM9D2SQ4PqnqBMR6ITKU6ss304cy+D6UeA+1 TllPLZ1t8M2fKG6NWHnZq16qLm10nqaMUaed6nQuWhNi9NP97nEXoPVjF A==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="183965627" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 03:53:09 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 03:53:05 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:53:02 -0700 From: Tudor Ambarus To: , , , , , CC: , , , , , Tudor Ambarus Subject: [PATCH 4/8] spi: atmel-quadspi: Add support for configuring CS timing Date: Thu, 17 Nov 2022 12:52:45 +0200 Message-ID: <20221117105249.115649-5-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com> References: <20221117105249.115649-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The at91 QSPI IP uses a default value of half of the period of the QSPI clock period for the cs-setup time, which is not always enough, an example being the sst26vf064b SPI NOR flash which requires a minimum cs-setup time of 5 ns. It was observed that none of the at91 SoCs can fulfill the minimum CS setup time for the aforementioned flash, as they operate at high frequencies and half a period does not suffice for the required CS setup time. Add support for configuring the CS timing in the controller. Signed-off-by: Tudor Ambarus --- drivers/spi/atmel-quadspi.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 976a217e356d..70637e46290a 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -510,6 +510,39 @@ static int atmel_qspi_setup(struct spi_device *spi) return 0; } +static int atmel_qspi_set_cs_timing(struct spi_device *spi) +{ + struct spi_controller *ctrl = spi->master; + struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); + unsigned long clk_rate; + u32 cs_setup; + int delay; + int ret; + + delay = spi_delay_to_ns(&spi->cs_setup, NULL); + if (delay <= 0) + return delay; + + clk_rate = clk_get_rate(aq->pclk); + if (!clk_rate) + return -EINVAL; + + cs_setup = DIV_ROUND_UP((delay * DIV_ROUND_UP(clk_rate, 1000000)), + 1000); + + ret = pm_runtime_resume_and_get(ctrl->dev.parent); + if (ret < 0) + return ret; + + aq->scr |= QSPI_SCR_DLYBS(cs_setup); + atmel_qspi_write(aq->scr, aq, QSPI_SCR); + + pm_runtime_mark_last_busy(ctrl->dev.parent); + pm_runtime_put_autosuspend(ctrl->dev.parent); + + return 0; +} + static void atmel_qspi_init(struct atmel_qspi *aq) { /* Reset the QSPI controller */ @@ -555,6 +588,7 @@ static int atmel_qspi_probe(struct platform_device *pdev) ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; ctrl->setup = atmel_qspi_setup; + ctrl->set_cs_timing = atmel_qspi_set_cs_timing; ctrl->bus_num = -1; ctrl->mem_ops = &atmel_qspi_mem_ops; ctrl->num_chipselect = 1; From patchwork Thu Nov 17 10:52:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13046577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50380C43217 for ; Thu, 17 Nov 2022 10:54:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239669AbiKQKyO (ORCPT ); Thu, 17 Nov 2022 05:54:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239524AbiKQKxR (ORCPT ); Thu, 17 Nov 2022 05:53:17 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFC165B5AD; Thu, 17 Nov 2022 02:53:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668682391; x=1700218391; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V+B/oow35dGgcpcT99slHtwXN+81/1x8fB2BGyRH3ZM=; b=ZyH/St2Np4muxa8WcdPP+tqUDbW62bytbVIg57RPAfYBLXX4nOwXB0NJ 98RvqoA+csqF0/mhcogdD6+gdI5VSrS9GiQshykWWp78cV5dsjUf80cLg RXJlaY/gkPvgYCz2yITrX0HwF6qkMvRGJhJycK5C8cFcDVJLaw9QmWCmF i/txwxacyY15VENiIUq5IifkFfReoygh458Uot6roxbJpjoerwJy0hbUI w/H81gb2AtxluaP0KxT9Fc8PEIuINrmLRmHNcwGDX7tO8ZF/4+LH2mvcZ CDHNOrTRzk792uGMKik/AEfTtNY2+tGhHrNLPiaZof11SoYcTqYvEpco7 g==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="189356168" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 03:53:11 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 03:53:08 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:53:06 -0700 From: Tudor Ambarus To: , , , , , CC: , , , , , Tudor Ambarus Subject: [PATCH 5/8] ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency Date: Thu, 17 Nov 2022 12:52:46 +0200 Message-ID: <20221117105249.115649-6-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com> References: <20221117105249.115649-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi index 83bcf9fe0152..20caf40b4755 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -220,7 +220,8 @@ qspi1_flash: flash@0 { #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = /bits/ 16 <7>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; m25p,fast-read; From patchwork Thu Nov 17 10:52:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13046576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 150F4C4332F for ; Thu, 17 Nov 2022 10:54:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234051AbiKQKyO (ORCPT ); Thu, 17 Nov 2022 05:54:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233096AbiKQKxU (ORCPT ); Thu, 17 Nov 2022 05:53:20 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6FBC5ADE0; Thu, 17 Nov 2022 02:53:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668682398; x=1700218398; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=H6jfv/98Y/BHItdiM3LYtojQb8Xu3XwDeExUAi0R+zs=; b=z1cYFK+OLBZGxMMogW4KNZ2mZnOIBPB5I7ZKsfP0zBTAN4G8F0vZ2Qp6 27tt07qT2VKT4jd5iI7td9BzTtmwf5A7deukzgAZG1RudHILh/NQjGdvW THu9UVdrBYkVo8zkQZ2w17W8yK2PQumzXpb6vlfSFJL4UBjCh2v/bJEl3 qzBzn7ucOU7icbNNncN/4soQomq/qikfkeTbW8r/OW5QykpxtJcFhUxlj YQCHoEQyRCyVeULAGLRESxPhfSqPTUxbr02p2Pgw5SYdnqXvN+bRkodax IBAO897VxOHNiZwTe4eMFX4GMV+D+Hj5v32ju+9Mhg0TGDf5quD4+WAHy w==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="183965650" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 03:53:15 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 03:53:11 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:53:09 -0700 From: Tudor Ambarus To: , , , , , CC: , , , , , Tudor Ambarus Subject: [PATCH 6/8] ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency Date: Thu, 17 Nov 2022 12:52:47 +0200 Message-ID: <20221117105249.115649-7-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com> References: <20221117105249.115649-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org sama5d27-som1 populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index 8aa9e8dea337..243f09f40761 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -43,7 +43,8 @@ flash@0 { #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = /bits/ 16 <7>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; From patchwork Thu Nov 17 10:52:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13046578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CFE2C433FE for ; Thu, 17 Nov 2022 10:54:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239674AbiKQKyP (ORCPT ); Thu, 17 Nov 2022 05:54:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239267AbiKQKxV (ORCPT ); Thu, 17 Nov 2022 05:53:21 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6AD55BD4C; Thu, 17 Nov 2022 02:53:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668682399; x=1700218399; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pub4+zHZreJmfMrR4t0OMZDURmCLD6tCvA9jmlzzuIg=; b=uwYiwXedumA2nE/77X4Fiu9LAmA9GY0Q979vmoG6/GVq/gaXV8AunBRD wI5SsCNe3RRM6cBBHBiHVuf0dXSibP322sUfS8YDiMrMPO4BF4Fzg1iLC 849cP+4de408Rof3pPXHfX4x2ZkKxwUKJRe7xreItgs9ZS3JRiihOibIL kDlzhZyvxoX313YH86W/ugUcdsHd7SbjwbIy/Ta/noj0Yg3UFyfL7qksy JxN0jhtEitDaSQGRTsNTDegH3ZMsbGcQ9O//0n3jwuRSyh1CtqlwD3PVu o0pPOqu6abGC4XUNZQLNTeoTCy2Y73Cp3ve+SuYR923StvaSwtmVpxt2h A==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="183965652" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 03:53:17 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 03:53:14 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:53:12 -0700 From: Tudor Ambarus To: , , , , , CC: , , , , , Tudor Ambarus Subject: [PATCH 7/8] ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency Date: Thu, 17 Nov 2022 12:52:48 +0200 Message-ID: <20221117105249.115649-8-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com> References: <20221117105249.115649-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/at91-sama5d2_icp.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index dd1dec9d4e07..ffd9627874c9 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -669,7 +669,8 @@ flash@0 { #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = /bits/ 16 <7>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; From patchwork Thu Nov 17 10:52:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13046579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6886BC433FE for ; Thu, 17 Nov 2022 10:54:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239421AbiKQKyU (ORCPT ); Thu, 17 Nov 2022 05:54:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239379AbiKQKx3 (ORCPT ); Thu, 17 Nov 2022 05:53:29 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42D6F5595; Thu, 17 Nov 2022 02:53:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668682407; x=1700218407; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uWkuOl/J8eDUGqINokgFVHKc4s1F8Y1WbCaW1XUAocc=; b=h8YW220uZYycXNF+d+P+4j5sjN3rNwggUMtEg+0BNnb1KCeEnibR5OX5 jb6XZFxwVcW5hFTiM+/6Ced6CZ2XJgRano4rrXmg2Bv9UwiwnhWCDR57Q F2FZVn1YwqI55+UI9hrF+pE8LOutURSAYSTq6IHVQPWSFllaQBw8R5kU+ 0Yf4sk2f2FXDNbFxNn+5ZmKtrQGvI0wzn6p5t87ZicpO7lNhcQoxGpgqa 5obCbOUg4vZrbgbdFfLygbwRcDWGF3Ca6oMdZ/Ph+pgOZhUb1MXxMNIxE XBPGrt2FszY1Cn+Hu7iImpRCth9SvKzbeaqsHpf/TrRQYPd6hts1oYmZz g==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="183965664" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 03:53:19 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 03:53:17 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:53:15 -0700 From: Tudor Ambarus To: , , , , , CC: , , , , , Tudor Ambarus Subject: [PATCH 8/8] ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency Date: Thu, 17 Nov 2022 12:52:49 +0200 Message-ID: <20221117105249.115649-9-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com> References: <20221117105249.115649-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org sam9x60ek populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~33%. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/at91-sam9x60ek.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index 4ba52ba11dc6..6cbb4e0d9938 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -612,7 +612,8 @@ flash@0 { #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = /bits/ 16 <7>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read;