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Received: from mail.kernel.org ([198.145.29.99]) by casper.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fnmPZ-0004wU-Im for linux-arm-kernel@lists.infradead.org; Thu, 09 Aug 2018 14:59:39 +0000 Received: from jouet.infradead.org (179-240-153-38.3g.claro.net.br [179.240.153.38]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 210A221D62; Thu, 9 Aug 2018 14:59:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1533826766; bh=TeFC1Rxf6RqJJ9B6jvy3+XSiElSaSUB04XZd7Dqma+c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VXdDXvteNrjSLlH7AlTystzPBuAcEYsiArfTUFPyHR+fkYcZW93r9AGjgHpT2uCG0 YbGJBFtkB4M0sgtIjvOiYubtlvws9tx2YQF/9nxs5VwWvpt/hs4MUi1PUV8+NILvba TEVCVRGt5MRPorqO+uDW5OGiAbJ5NM7tN1z2LnUI= From: Arnaldo Carvalho de Melo To: Ingo Molnar Subject: [PATCH 10/44] perf vendor events arm64: Enable JSON events for eMAG Date: Thu, 9 Aug 2018 11:57:48 -0300 Message-Id: <20180809145822.21391-11-acme@kernel.org> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180809145822.21391-1-acme@kernel.org> References: <20180809145822.21391-1-acme@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180809_155937_748412_C63CBBA0 X-CRM114-Status: GOOD ( 14.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Arnaldo Carvalho de Melo , Clark Williams , Will Deacon , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Alexander Shishkin , Peter Zijlstra , Ganapatrao Kulkarni , Namhyung Kim , Sean V Kelley , Jiri Olsa , William Cohen , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sean V Kelley This patch adds the Ampere Computing eMAG file. This platform follows the ARMv8 recommended IMPLEMENTATION DEFINED events, where applicable. Signed-off-by: Sean V Kelley Reviewed-by: John Garry Cc: Alexander Shishkin Cc: Ganapatrao Kulkarni Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Will Deacon Cc: William Cohen Cc: linux-arm-kernel@lists.infradead.org LPU-Reference: 20180803041811.17065-1-seanvk.dev@oregontracks.org Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/arm64/ampere/emag/core-imp-def.json | 32 ++++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 2 files changed, 33 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json new file mode 100644 index 000000000000..bc03c06c3918 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json @@ -0,0 +1,32 @@ +[ + { + "ArchStdEvent": "L1D_CACHE_RD", + }, + { + "ArchStdEvent": "L1D_CACHE_WR", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD", + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR", + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD", + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR", + }, + { + "ArchStdEvent": "L1D_TLB_RD", + }, + { + "ArchStdEvent": "L1D_TLB_WR", + }, + { + "ArchStdEvent": "BUS_ACCESS_RD", + }, + { + "ArchStdEvent": "BUS_ACCESS_WR", + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index f03e26ecb658..59cd8604b0bd 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -16,3 +16,4 @@ 0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000430f0af0,v1,cavium/thunderx2,core 0x00000000480fd010,v1,hisilicon/hip08,core +0x00000000500f0000,v1,ampere/emag,core