From patchwork Fri Nov 25 09:27:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13055654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA00CC4167B for ; Fri, 25 Nov 2022 09:28:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229796AbiKYJ25 (ORCPT ); Fri, 25 Nov 2022 04:28:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229771AbiKYJ2j (ORCPT ); Fri, 25 Nov 2022 04:28:39 -0500 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCA7812AFC for ; Fri, 25 Nov 2022 01:28:37 -0800 (PST) Received: by mail-ej1-x634.google.com with SMTP id vp12so7709864ejc.8 for ; Fri, 25 Nov 2022 01:28:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=mpP1Fb3xrzGRgQcSv/nFJciJPCBP7tqCxTn34nBqums=; b=M3AG39iyzVs6kp0nC+H6PpKMBHKps2QdCUkARwCOOsrhaQzvV03csXlDQrasZJfxXq 5++2hBLuysDfDyTuchXNvhK0/xi/Itvpo6NplBuZk7h6f+vuMyT2zIryoZu4RDAjpH9u 1kG8hhmksgxiGXsd1m8NOYhDz6dv/mVQbu/+mILE1rjce+4lB6agNnAWS4RYUHNpEZZ2 YfMq7mLnGCP1mG1Z8uAYt5dy87jP+gpppV548B0WAKVeVImMIXjTJC26xRJyrzY5jdC4 6vw4cdnVVsBX+MO9sczMwjyzNDYHPZFxsHGOZhipN926gnKVQc0Oy/o1+msxlp0ixOLj odMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=mpP1Fb3xrzGRgQcSv/nFJciJPCBP7tqCxTn34nBqums=; b=cR9j04zP4J0PA08mYHi5ShwxHD7ct0kTZ7DEYDqx9atfMO08dHtWAU6zFwmC3fZuNK 89nIIQS+f6D6FVwxQxlp3vDKSZ/CYQH51laMwbYoCxIWRVKNVSSrLEW0KIYsbDs7U9Hy kxFFZpdfz6JOZuUiKiiEB5Kd3VjiLTQdI88F15J1ntC6ku4z64kxDTadswZ8SoChrx1e 5RROKPwtK+GcUUa+qx2Zvkvida6vrBuC1nj8m2dzxirlShMbR6hzQtBS5OSCi8DrcmhF 9NblN4aRyLIPEKeAjCj8BtfUNJVJEYQGawsWu6Vgbr1AZM8fpmyWfo7w67yiID+sHI5R AafQ== X-Gm-Message-State: ANoB5pmYgGElsB4zglZri1ivXuqMw/GuuRmu9UbWgOyfHwyg9NzL0dH4 drvXt11hwZ9mMktV+ioIWwbtHdNXshAX6A== X-Google-Smtp-Source: AA0mqf6hp96XZKNkOkLtlvlp1dyiIjtsY9pIgqXvv7XvMMs9JbLaxGUy326AbqovFjsY5Em9g7F0/Q== X-Received: by 2002:a17:906:d281:b0:782:7790:f132 with SMTP id ay1-20020a170906d28100b007827790f132mr15514892ejb.649.1669368516112; Fri, 25 Nov 2022 01:28:36 -0800 (PST) Received: from otso.. (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id q10-20020a170906b28a00b007b47748d22fsm1329315ejz.220.2022.11.25.01.28.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 01:28:35 -0800 (PST) From: Luca Weiss To: linux-arm-msm@vger.kernel.org, Johan Hovold Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss , Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatible Date: Fri, 25 Nov 2022 10:27:47 +0100 Message-Id: <20221125092749.46073-1-luca.weiss@fairphone.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the compatible describing the combo phy found on SM6350. Signed-off-by: Luca Weiss --- @Johan Hovold, I've sent this v2 as RFC because there are several things where I have questions on how it should be done. In this patch, you can see there's cfg_ahb (&xo_board) and power-domains is not set. In msm-4.19 &gcc_usb30_prim_gdsc is only used in the ssusb@a600000 node, or should I also add it to qmpphy? .../bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml index 6f31693d9868..3e39e3e0504d 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml @@ -17,16 +17,18 @@ properties: compatible: enum: - qcom,sc8280xp-qmp-usb43dp-phy + - qcom,sm6350-qmp-usb3-dp-phy reg: maxItems: 1 clocks: - maxItems: 4 + maxItems: 5 clock-names: items: - const: aux + - const: cfg_ahb - const: ref - const: com_aux - const: usb3_pipe @@ -61,7 +63,6 @@ required: - reg - clocks - clock-names - - power-domains - resets - reset-names - vdda-phy-supply From patchwork Fri Nov 25 09:27:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13055655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25B50C4332F for ; Fri, 25 Nov 2022 09:29:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230008AbiKYJ3K (ORCPT ); Fri, 25 Nov 2022 04:29:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229840AbiKYJ2m (ORCPT ); Fri, 25 Nov 2022 04:28:42 -0500 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0ADB3AC10 for ; Fri, 25 Nov 2022 01:28:38 -0800 (PST) Received: by mail-ej1-x630.google.com with SMTP id kt23so8997358ejc.7 for ; Fri, 25 Nov 2022 01:28:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c2hwsnxelidzuxT5vbVM4C+YfhopOxytMt7ErRm7Hlk=; b=eGXUvIoyyB68RsblUZtQUSFNv4jF4G6D4gpT+oLYtG8Vhlx5eEBttRn56LdOzwqIxe bT/1l571ZllnPOwM7uXiG1I8apJc9eJ+Gzn/5fOEK/PMkk1lduJfZvM4RUB8QLcCZdIE D+amjHoysZDTJj4lCCXa+EejINVfPrin9yXDMWh+CgZGHiH55Xp0uk03NpKt6rxNXs6F BFunzbYZfeU2lSfaiLG3kkDzheKTKNYwylpvoTuJSaGM9qswHoCz5Ugfoek01HBYU5pI +S6f3iy+3YcIKfUlOJLnlq/p3SFpjLCZ35iQucSx12tSeta6yxNOAqJbHzUHh/r4Kbca znkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c2hwsnxelidzuxT5vbVM4C+YfhopOxytMt7ErRm7Hlk=; b=iMt9BmJeilR+M78IXCWpbuzqE+0/fOeDxjkfeywH3aDhUiDqM7gAGddHgE+b43i2WR bxxFcQ8ShdTWcvb+8I18MMhrWs+9UnlOjZ1piQPPOUVKSSfYiJtglZx7OGfCU2/SCvjJ 8yiI9CrHp5uT3ejVO0fkuLuBTa1tMQxJePZFw9VTjCkUdSIcv1vpm5u62WPIOSF3cFvE atEXDPvHpjvvYzjCrd1DjRkb1XMkqyC+oY0O8MJQtNchL9iOMenlnYpU3OC1tMLs+RP0 Y0n2lYkloQnC9RUB7MvgEOXfRRkL1K11mkDfamwfxer215VfLok0ecWgrYGE5Ga7SOxO CU6g== X-Gm-Message-State: ANoB5pl1NxptPDNFpKzL313gjH/uVfITShvnMO1qHnBF5eek20pawxHi rjMq6C/dxxT9Jwe5GNSBlOcucX5HuvjZcA== X-Google-Smtp-Source: AA0mqf5D5J4IIdpP3ebDF/zsdWUnuXLzfYMjB0uRhixy4JIW0LKEMLzrYKqAm+7GnFKQl++0gnscGQ== X-Received: by 2002:a17:906:130b:b0:7ad:92c5:637a with SMTP id w11-20020a170906130b00b007ad92c5637amr31267694ejb.87.1669368517102; Fri, 25 Nov 2022 01:28:37 -0800 (PST) Received: from otso.. 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id q10-20020a170906b28a00b007b47748d22fsm1329315ejz.220.2022.11.25.01.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 01:28:36 -0800 (PST) From: Luca Weiss To: linux-arm-msm@vger.kernel.org, Johan Hovold Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss , Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 2/3] phy: qcom-qmp-combo: Add config for SM6350 Date: Fri, 25 Nov 2022 10:27:48 +0100 Message-Id: <20221125092749.46073-2-luca.weiss@fairphone.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221125092749.46073-1-luca.weiss@fairphone.com> References: <20221125092749.46073-1-luca.weiss@fairphone.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the tables and config for the combo phy found on SM6350. Signed-off-by: Luca Weiss --- @Johan Hovold, here I've added dp_txa & dp_txb, I believe otherwise qmp->dp_tx would be wrong. Is this different on sc8280xp or was this a mistake on your side? I think this should probably be split out to another patch to not mix things up too much. I think other than that this patch is good. drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 134 +++++++++++++++++++++- 1 file changed, 132 insertions(+), 2 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 77052c66cf70..58c241b8844a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -311,6 +311,70 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), }; +static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), +}; + +static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { + /* FLL settings */ + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), + + /* Lock Det settings */ + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), + + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), + QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), +}; + static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), @@ -809,6 +873,8 @@ struct qmp_combo_offsets { u16 usb3_pcs; u16 usb3_pcs_usb; u16 dp_serdes; + u16 dp_txa; + u16 dp_txb; u16 dp_dp_phy; }; @@ -975,6 +1041,21 @@ static const char * const sc7180_usb3phy_reset_l[] = { "phy", }; +static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { + .com = 0x0000, + .txa = 0x1200, + .rxa = 0x1400, + .txb = 0x1600, + .rxb = 0x1800, + .usb3_serdes = 0x1000, + .usb3_pcs_misc = 0x1a00, + .usb3_pcs = 0x1c00, + .dp_serdes = 0x2000, + .dp_txa = 0x2200, + .dp_txb = 0x2600, + .dp_dp_phy = 0x2c00, +}; + static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { .com = 0x0000, .txa = 0x0400, @@ -1172,6 +1253,51 @@ static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { .regs = qmp_v4_usb3phy_regs_layout, }; +static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { + .offsets = &qmp_combo_offsets_v3, + + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = sm6350_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), + .pcs_tbl = sm6350_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), + + .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, + .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), + .dp_tx_tbl = qmp_v3_dp_tx_tbl, + .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), + + .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), + .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), + .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), + + .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, + + .dp_aux_init = qmp_v3_dp_aux_init, + .configure_dp_tx = qmp_v3_configure_dp_tx, + .configure_dp_phy = qmp_v3_configure_dp_phy, + .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, + + .clk_list = qmp_v3_phy_clk_l, + .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), + .reset_list = msm8996_usb3phy_reset_l, + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = qmp_v3_usb3phy_regs_layout, +}; + static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { .serdes_tbl = sm8150_usb3_serdes_tbl, .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), @@ -2641,8 +2767,8 @@ static int qmp_combo_parse_dt(struct qmp_combo *qmp) qmp->pcs_usb = base + offs->usb3_pcs_usb; qmp->dp_serdes = base + offs->dp_serdes; - qmp->dp_tx = base + offs->txa; - qmp->dp_tx2 = base + offs->txb; + qmp->dp_tx = base + offs->dp_txa; + qmp->dp_tx2 = base + offs->dp_txb; qmp->dp_dp_phy = base + offs->dp_dp_phy; qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); @@ -2789,6 +2915,10 @@ static const struct of_device_id qmp_combo_of_match_table[] = { .compatible = "qcom,sdm845-qmp-usb3-dp-phy", .data = &sdm845_usb3dpphy_cfg, }, + { + .compatible = "qcom,sm6350-qmp-usb3-dp-phy", + .data = &sm6350_usb3dpphy_cfg, + }, { .compatible = "qcom,sm8250-qmp-usb3-dp-phy", .data = &sm8250_usb3dpphy_cfg, From patchwork Fri Nov 25 09:27:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 13055656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3371BC46467 for ; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id q10-20020a170906b28a00b007b47748d22fsm1329315ejz.220.2022.11.25.01.28.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 01:28:37 -0800 (PST) From: Luca Weiss To: linux-arm-msm@vger.kernel.org, Johan Hovold Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Luca Weiss , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 3/3] arm64: dts: qcom: sm6350: Use specific qmpphy compatible Date: Fri, 25 Nov 2022 10:27:49 +0100 Message-Id: <20221125092749.46073-3-luca.weiss@fairphone.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221125092749.46073-1-luca.weiss@fairphone.com> References: <20221125092749.46073-1-luca.weiss@fairphone.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The sc7180 phy compatible works fine for some cases, but it turns out sm6350 does need proper phy configuration in the driver, so use the newly added sm6350 compatible. Because the sm6350 compatible is using the new binding, we need to change the node quite a bit to match it. This fixes qmpphy init when no USB cable is plugged in during bootloader stage. Signed-off-by: Luca Weiss --- @Johan Hovold, in this patch there's also the question about cfg_ahb, power-domains but I'm also not happy about using the QMP_USB43DP_USB3_PHY define for the phy reference. Do you think it's a good idea to introduce e.g. QMP_USB3DP_USB3_PHY with the same value so it's essentially just an alias to the other? This series is tested on next-20221124 with next branch of linux-phy repo (commit bea3ce759b46) merged in. arch/arm64/boot/dts/qcom/sm6350.dtsi | 46 +++++++--------------------- 1 file changed, 11 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 0f01ff4feb55..923c8bb7e5f8 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -1119,50 +1120,25 @@ usb_1_hsphy: phy@88e3000 { resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sc7180-qmp-usb3-dp-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x40>, - <0 0x088ea000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1_qmpphy: phy@88e8000 { + compatible = "qcom,sm6350-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&xo_board>, <&rpmhcc RPMH_QLINK_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux", "usb3_pipe"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: usb3-phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; + #clock-cells = <1>; + #phy-cells = <1>; - dp_phy: dp-phy@88ea200 { - reg = <0 0x088ea200 0 0x200>, - <0 0x088ea400 0 0x200>, - <0 0x088eac00 0 0x400>, - <0 0x088ea600 0 0x200>, - <0 0x088ea800 0 0x200>, - <0 0x088eaa00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <1>; - }; + status = "disabled"; }; dc_noc: interconnect@9160000 { @@ -1236,7 +1212,7 @@ usb_1_dwc3: usb@a600000 { snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; }; };