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Tue, 29 Nov 2022 22:38:18 GMT Received: from maru.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 29 Nov 2022 14:38:17 -0800 From: Jae Hyun Yoo To: Joel Stanley CC: Jamie Iles , Graeme Gregory , Jae Hyun Yoo , , Subject: [PATCH] ARM: dts: aspeed-g6: Add more UART controller nodes Date: Tue, 29 Nov 2022 14:38:05 -0800 Message-ID: <20221129223805.815027-1-quic_jaehyoo@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: roAmhsvQwMLUnz_U8Lncun9aCJsOEbce X-Proofpoint-ORIG-GUID: roAmhsvQwMLUnz_U8Lncun9aCJsOEbce X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-29_13,2022-11-29_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 bulkscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 clxscore=1011 mlxlogscore=888 suspectscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211290135 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221129_143830_350892_461B65BA X-CRM114-Status: GOOD ( 15.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add nodes for UART10, UART11, UART12 and UART13 into aspeed-g6.dtsi. UART12 and UART13 have two mappable pin groups so their pinmux setting should be specified in a board dts instead like below. UART12: pinctrl-0 = <&pinctrl_uart12g0_default>; or pinctrl-0 = <&pinctrl_uart12g1_default>; UART13: pinctrl-0 = <&pinctrl_uart13g0_default>; or pinctrl-0 = <&pinctrl_uart13g1_default>; Signed-off-by: Jae Hyun Yoo --- arch/arm/boot/dts/aspeed-g6.dtsi | 52 ++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index b94ccdb5213d..afc356416d53 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -816,6 +816,58 @@ uart9: serial@1e790300 { status = "disabled"; }; + uart10: serial@1e790400 { + compatible = "ns16550a"; + reg = <0x1e790400 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART10CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart10_default>; + + status = "disabled"; + }; + + uart11: serial@1e790500 { + compatible = "ns16550a"; + reg = <0x1e790500 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART11CLK>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart11_default>; + + status = "disabled"; + }; + + uart12: serial@1e790600 { + compatible = "ns16550a"; + reg = <0x1e790600 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART12CLK>; + no-loopback-test; + + status = "disabled"; + }; + + uart13: serial@1e790700 { + compatible = "ns16550a"; + reg = <0x1e790700 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_UART13CLK>; + no-loopback-test; + + status = "disabled"; + }; + i2c: bus@1e78a000 { compatible = "simple-bus"; #address-cells = <1>;