From patchwork Thu Dec 1 16:49:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 13061576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D12EC43217 for ; Thu, 1 Dec 2022 16:50:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7382410E650; Thu, 1 Dec 2022 16:50:34 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id B941310E154; Thu, 1 Dec 2022 16:50:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669913431; x=1701449431; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=SCbvrgXzJAhOLtaz9ksQWo2bjBmnvo2WVkUQ/vEBep8=; b=B05lrHLa2wmBzVpIA/656+qCyMXz9t6sNvd8GJijFpKVc7o1yhj3H08l louYNsUgO5VMOBsGpJpl69Rob0S7H5Binj4OZozIW+/y2dG+bHrN/VE4U CYnuDpiYI2gyHd9eDrzukJC0dsgiMlY9lbwXuHnAgC+7g2Hh/4LtRvEqM sggCv4kaoKLucAHeX0z6L3obcWONVqVSdV+5Wc5s7thi/g+NAGgT4+L8z 0rEAUgVCdhcRqSR7xLnONBQppYtXLnc7NoRb9UCEPijY6c5HlPqgMbUts T6s7mqQWcnFNiFud60xfppT0J5NDDyO4BKvLRF18zY5B8czoGypub5Be9 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="316889051" X-IronPort-AV: E=Sophos;i="5.96,209,1665471600"; d="scan'208";a="316889051" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 08:50:27 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="708139966" X-IronPort-AV: E=Sophos;i="5.96,209,1665471600"; d="scan'208";a="708139966" Received: from tlehuche-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.3.239]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 08:50:25 -0800 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Thu, 1 Dec 2022 16:49:43 +0000 Message-Id: <20221201164944.327019-1-matthew.auld@intel.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 1/2] lib/dmabuf_sync_file: move common stuff into lib X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Andrzej Hajda , Nirmoy Das Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" So we can use this across different tests. Signed-off-by: Matthew Auld Cc: Kamil Konieczny Cc: Andrzej Hajda Cc: Nirmoy Das --- lib/dmabuf_sync_file.c | 138 +++++++++++++++++++++++++++++++++++++++ lib/dmabuf_sync_file.h | 19 ++++++ lib/meson.build | 1 + tests/dmabuf_sync_file.c | 135 ++------------------------------------ 4 files changed, 164 insertions(+), 129 deletions(-) create mode 100644 lib/dmabuf_sync_file.c create mode 100644 lib/dmabuf_sync_file.h diff --git a/lib/dmabuf_sync_file.c b/lib/dmabuf_sync_file.c new file mode 100644 index 00000000..24e0f96d --- /dev/null +++ b/lib/dmabuf_sync_file.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: MIT + +#ifdef __linux__ +#include +#endif +#include + +#include "igt.h" +#include "igt_vgem.h" +#include "sw_sync.h" + +#include "dmabuf_sync_file.h" + +struct igt_dma_buf_sync_file { + __u32 flags; + __s32 fd; +}; + +#define IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE _IOWR(DMA_BUF_BASE, 2, struct igt_dma_buf_sync_file) +#define IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE _IOW(DMA_BUF_BASE, 3, struct igt_dma_buf_sync_file) + +bool has_dmabuf_export_sync_file(int fd) +{ + struct vgem_bo bo; + int dmabuf, ret; + struct igt_dma_buf_sync_file arg; + + bo.width = 1; + bo.height = 1; + bo.bpp = 32; + vgem_create(fd, &bo); + + dmabuf = prime_handle_to_fd(fd, bo.handle); + gem_close(fd, bo.handle); + + arg.flags = DMA_BUF_SYNC_WRITE; + arg.fd = -1; + + ret = igt_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE, &arg); + close(dmabuf); + igt_assert(ret == 0 || errno == ENOTTY); + + return ret == 0; +} + +int dmabuf_export_sync_file(int dmabuf, uint32_t flags) +{ + struct igt_dma_buf_sync_file arg; + + arg.flags = flags; + arg.fd = -1; + do_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE, &arg); + + return arg.fd; +} + +bool has_dmabuf_import_sync_file(int fd) +{ + struct vgem_bo bo; + int dmabuf, timeline, fence, ret; + struct igt_dma_buf_sync_file arg; + + bo.width = 1; + bo.height = 1; + bo.bpp = 32; + vgem_create(fd, &bo); + + dmabuf = prime_handle_to_fd(fd, bo.handle); + gem_close(fd, bo.handle); + + timeline = sw_sync_timeline_create(); + fence = sw_sync_timeline_create_fence(timeline, 1); + sw_sync_timeline_inc(timeline, 1); + + arg.flags = DMA_BUF_SYNC_RW; + arg.fd = fence; + + ret = igt_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE, &arg); + close(dmabuf); + close(fence); + igt_assert(ret == 0 || errno == ENOTTY); + + return ret == 0; +} + +void dmabuf_import_sync_file(int dmabuf, uint32_t flags, int sync_fd) +{ + struct igt_dma_buf_sync_file arg; + + arg.flags = flags; + arg.fd = sync_fd; + do_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE, &arg); +} + +void +dmabuf_import_timeline_fence(int dmabuf, uint32_t flags, + int timeline, uint32_t seqno) +{ + int fence; + + fence = sw_sync_timeline_create_fence(timeline, seqno); + dmabuf_import_sync_file(dmabuf, flags, fence); + close(fence); +} + +bool dmabuf_busy(int dmabuf, uint32_t flags) +{ + struct pollfd pfd = { .fd = dmabuf }; + + /* If DMA_BUF_SYNC_WRITE is set, we don't want to set POLLIN or + * else poll() may return a non-zero value if there are only read + * fences because POLLIN is ready even if POLLOUT isn't. + */ + if (flags & DMA_BUF_SYNC_WRITE) + pfd.events |= POLLOUT; + else if (flags & DMA_BUF_SYNC_READ) + pfd.events |= POLLIN; + + return poll(&pfd, 1, 0) == 0; +} + +bool sync_file_busy(int sync_file) +{ + struct pollfd pfd = { .fd = sync_file, .events = POLLIN }; + return poll(&pfd, 1, 0) == 0; +} + +bool dmabuf_sync_file_busy(int dmabuf, uint32_t flags) +{ + int sync_file; + bool busy; + + sync_file = dmabuf_export_sync_file(dmabuf, flags); + busy = sync_file_busy(sync_file); + close(sync_file); + + return busy; +} diff --git a/lib/dmabuf_sync_file.h b/lib/dmabuf_sync_file.h new file mode 100644 index 00000000..08da8150 --- /dev/null +++ b/lib/dmabuf_sync_file.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ + +#ifndef DMABUF_SYNC_FILE_H +#define DMABUF_SYNC_FILE_H + +#include +#include + +bool has_dmabuf_export_sync_file(int fd); +bool has_dmabuf_import_sync_file(int fd); +int dmabuf_export_sync_file(int dmabuf, uint32_t flags); +void dmabuf_import_sync_file(int dmabuf, uint32_t flags, int sync_fd); +void dmabuf_import_timeline_fence(int dmabuf, uint32_t flags, + int timeline, uint32_t seqno); +bool dmabuf_busy(int dmabuf, uint32_t flags); +bool sync_file_busy(int sync_file); +bool dmabuf_sync_file_busy(int dmabuf, uint32_t flags); + +#endif diff --git a/lib/meson.build b/lib/meson.build index cef2d0ff..896d5733 100644 --- a/lib/meson.build +++ b/lib/meson.build @@ -1,5 +1,6 @@ lib_sources = [ 'drmtest.c', + 'dmabuf_sync_file.c', 'huc_copy.c', 'i915/gem.c', 'i915/gem_context.c', diff --git a/tests/dmabuf_sync_file.c b/tests/dmabuf_sync_file.c index 2179a76d..f59be125 100644 --- a/tests/dmabuf_sync_file.c +++ b/tests/dmabuf_sync_file.c @@ -1,140 +1,17 @@ // SPDX-License-Identifier: MIT +#ifdef __linux__ +#include +#endif +#include + #include "igt.h" #include "igt_vgem.h" #include "sw_sync.h" - -#include -#include +#include "dmabuf_sync_file.h" IGT_TEST_DESCRIPTION("Tests for sync_file support in dma-buf"); -struct igt_dma_buf_sync_file { - __u32 flags; - __s32 fd; -}; - -#define IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE _IOWR(DMA_BUF_BASE, 2, struct igt_dma_buf_sync_file) -#define IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE _IOW(DMA_BUF_BASE, 3, struct igt_dma_buf_sync_file) - -static bool has_dmabuf_export_sync_file(int fd) -{ - struct vgem_bo bo; - int dmabuf, ret; - struct igt_dma_buf_sync_file arg; - - bo.width = 1; - bo.height = 1; - bo.bpp = 32; - vgem_create(fd, &bo); - - dmabuf = prime_handle_to_fd(fd, bo.handle); - gem_close(fd, bo.handle); - - arg.flags = DMA_BUF_SYNC_WRITE; - arg.fd = -1; - - ret = igt_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE, &arg); - close(dmabuf); - igt_assert(ret == 0 || errno == ENOTTY); - - return ret == 0; -} - -static int dmabuf_export_sync_file(int dmabuf, uint32_t flags) -{ - struct igt_dma_buf_sync_file arg; - - arg.flags = flags; - arg.fd = -1; - do_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_EXPORT_SYNC_FILE, &arg); - - return arg.fd; -} - -static bool has_dmabuf_import_sync_file(int fd) -{ - struct vgem_bo bo; - int dmabuf, timeline, fence, ret; - struct igt_dma_buf_sync_file arg; - - bo.width = 1; - bo.height = 1; - bo.bpp = 32; - vgem_create(fd, &bo); - - dmabuf = prime_handle_to_fd(fd, bo.handle); - gem_close(fd, bo.handle); - - timeline = sw_sync_timeline_create(); - fence = sw_sync_timeline_create_fence(timeline, 1); - sw_sync_timeline_inc(timeline, 1); - - arg.flags = DMA_BUF_SYNC_RW; - arg.fd = fence; - - ret = igt_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE, &arg); - close(dmabuf); - close(fence); - igt_assert(ret == 0 || errno == ENOTTY); - - return ret == 0; -} - -static void dmabuf_import_sync_file(int dmabuf, uint32_t flags, int sync_fd) -{ - struct igt_dma_buf_sync_file arg; - - arg.flags = flags; - arg.fd = sync_fd; - do_ioctl(dmabuf, IGT_DMA_BUF_IOCTL_IMPORT_SYNC_FILE, &arg); -} - -static void -dmabuf_import_timeline_fence(int dmabuf, uint32_t flags, - int timeline, uint32_t seqno) -{ - int fence; - - fence = sw_sync_timeline_create_fence(timeline, seqno); - dmabuf_import_sync_file(dmabuf, flags, fence); - close(fence); -} - -static bool dmabuf_busy(int dmabuf, uint32_t flags) -{ - struct pollfd pfd = { .fd = dmabuf }; - - /* If DMA_BUF_SYNC_WRITE is set, we don't want to set POLLIN or - * else poll() may return a non-zero value if there are only read - * fences because POLLIN is ready even if POLLOUT isn't. - */ - if (flags & DMA_BUF_SYNC_WRITE) - pfd.events |= POLLOUT; - else if (flags & DMA_BUF_SYNC_READ) - pfd.events |= POLLIN; - - return poll(&pfd, 1, 0) == 0; -} - -static bool sync_file_busy(int sync_file) -{ - struct pollfd pfd = { .fd = sync_file, .events = POLLIN }; - return poll(&pfd, 1, 0) == 0; -} - -static bool dmabuf_sync_file_busy(int dmabuf, uint32_t flags) -{ - int sync_file; - bool busy; - - sync_file = dmabuf_export_sync_file(dmabuf, flags); - busy = sync_file_busy(sync_file); - close(sync_file); - - return busy; -} - static void test_export_basic(int fd) { struct vgem_bo bo; From patchwork Thu Dec 1 16:49:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 13061577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C077C4321E for ; Thu, 1 Dec 2022 16:50:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 12D0110E654; Thu, 1 Dec 2022 16:50:36 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6B6C710E640; Thu, 1 Dec 2022 16:50:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669913431; x=1701449431; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z2pxZMNPI6P+afHMNiSd0vqNRo/Hmpp3szV6QaAFnOg=; b=NIn471C+JDhNuXbxOyBZEMp3QCow0dr6zxoSaiRpg02Lg5CfkD0uWw9J UQdRupKWL1p3U5C0dl0kEc+EX7T4iRv9sjCAgiUDaKguZoe/SCAiWjhyK t4y1encQUAvmqvSf3nIwxHmRn2LPd+rjvc5xNhctUKKePLlRfI4Ddhy0Z wwToJf4JAtiKkZFU+aimQvCPHzBJeXYH0D9vyC75SBAdBhe460//CsEFV EzgnoKIbzkH2AmweO7vDkR0IONE8AHgCBKCQPW4yrBWibaMULTm7MiPIC ez0x0SQFCno6smciD+/s7qUqkGfWXjPgXfsIjWbjUzfy4gfbRZa76QdNq A==; X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="316889059" X-IronPort-AV: E=Sophos;i="5.96,209,1665471600"; d="scan'208";a="316889059" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 08:50:29 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10548"; a="708139976" X-IronPort-AV: E=Sophos;i="5.96,209,1665471600"; d="scan'208";a="708139976" Received: from tlehuche-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.3.239]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2022 08:50:27 -0800 From: Matthew Auld To: igt-dev@lists.freedesktop.org Date: Thu, 1 Dec 2022 16:49:44 +0000 Message-Id: <20221201164944.327019-2-matthew.auld@intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221201164944.327019-1-matthew.auld@intel.com> References: <20221201164944.327019-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 2/2] tests/i915/gem_exec_balancer: exercise dmabuf import X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Andrzej Hajda , Nirmoy Das Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With parallel submission it should be easy to get a fence array as the output fence. Try importing this into dma-buf reservation object, to see if anything explodes. v2: (Kamil) - Use ifdef __linux__ for linux headers - Add igt_describe() for new test References: https://gitlab.freedesktop.org/drm/intel/-/issues/7532 Signed-off-by: Matthew Auld Cc: Kamil Konieczny Cc: Andrzej Hajda Cc: Nirmoy Das Reviewed-by: Andrzej Hajda --- tests/i915/gem_exec_balancer.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c index 4300dbd1..8a68c341 100644 --- a/tests/i915/gem_exec_balancer.c +++ b/tests/i915/gem_exec_balancer.c @@ -22,11 +22,15 @@ */ #include +#ifdef __linux__ +#include +#endif #include #include #include #include +#include "dmabuf_sync_file.h" #include "i915/gem.h" #include "i915/gem_engine_topology.h" #include "i915/gem_create.h" @@ -2856,6 +2860,7 @@ static void logical_sort_siblings(int i915, #define PARALLEL_SUBMIT_FENCE (0x1 << 3) #define PARALLEL_CONTEXTS (0x1 << 4) #define PARALLEL_VIRTUAL (0x1 << 5) +#define PARALLEL_OUT_FENCE_DMABUF (0x1 << 6) static void parallel_thread(int i915, unsigned int flags, struct i915_engine_class_instance *siblings, @@ -2871,6 +2876,8 @@ static void parallel_thread(int i915, unsigned int flags, uint32_t target_bo_idx = 0; uint32_t first_bb_idx = 1; intel_ctx_cfg_t cfg; + uint32_t dmabuf_handle; + int dmabuf; igt_assert(bb_per_execbuf < 32); @@ -2924,11 +2931,20 @@ static void parallel_thread(int i915, unsigned int flags, execbuf.buffers_ptr = to_user_pointer(obj); execbuf.rsvd1 = ctx->id; + if (flags & PARALLEL_OUT_FENCE_DMABUF) { + dmabuf_handle = gem_create(i915, 4096); + dmabuf = prime_handle_to_fd(i915, dmabuf_handle); + } + for (n = 0; n < PARALLEL_BB_LOOP_COUNT; ++n) { execbuf.flags &= ~0x3full; gem_execbuf_wr(i915, &execbuf); if (flags & PARALLEL_OUT_FENCE) { + if (flags & PARALLEL_OUT_FENCE_DMABUF) + dmabuf_import_sync_file(dmabuf, DMA_BUF_SYNC_WRITE, + execbuf.rsvd2 >> 32); + igt_assert_eq(sync_fence_wait(execbuf.rsvd2 >> 32, 1000), 0); igt_assert_eq(sync_fence_status(execbuf.rsvd2 >> 32), 1); @@ -2959,6 +2975,11 @@ static void parallel_thread(int i915, unsigned int flags, if (fence) close(fence); + if (flags & PARALLEL_OUT_FENCE_DMABUF) { + gem_close(i915, dmabuf_handle); + close(dmabuf); + } + check_bo(i915, obj[target_bo_idx].handle, bb_per_execbuf * PARALLEL_BB_LOOP_COUNT, true); @@ -3420,6 +3441,11 @@ igt_main igt_subtest("parallel-out-fence") parallel(i915, PARALLEL_OUT_FENCE); + igt_describe("Regression test to check that dmabuf imported sync file can handle fence array"); + igt_subtest("parallel-dmabuf-import-out-fence") + parallel(i915, PARALLEL_OUT_FENCE | + PARALLEL_OUT_FENCE_DMABUF); + igt_subtest("parallel-keep-in-fence") parallel(i915, PARALLEL_OUT_FENCE | PARALLEL_IN_FENCE);