From patchwork Wed Dec 7 19:23:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13067552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1668C63708 for ; Wed, 7 Dec 2022 19:23:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229646AbiLGTXk (ORCPT ); Wed, 7 Dec 2022 14:23:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229651AbiLGTXh (ORCPT ); Wed, 7 Dec 2022 14:23:37 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1C7D663E6 for ; Wed, 7 Dec 2022 11:23:33 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id co23so2057910wrb.4 for ; Wed, 07 Dec 2022 11:23:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GUly8uO1OUcoSESV+o668Tkb+5x4qUzBcDjwS5bQlu4=; b=qIlMt8qo1eeKSh1mVdnpDD4P/cGqRQrED9Utsx1lcz4jajJ+h51LAdNxNpUc1Pgs5C SUzG1G7F29TUO3MPa1vprsFU65xh+L/6qpV37Ms0avq1bsA2J53M8c4NhnDuaeJugm78 2vGnr4UVVTy1PXmU/4ATqb7PveHBvts+q2M/mxsJrnNosCOyqmvBtP57bZ6fuyc8k+dk vIhAgYB5kNVREdqDLjueOTQRBuKI9dO7YX3QN3RQ9xrk79em+XSJ0SM+0XG/BUMTWWhH UQkhbRh64Jnf6NgGot7kY1nnwpw/2+MDo0Pr6BnVuE8XapCaE+/9RLGm5aNmoQcuoqNP wJ/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GUly8uO1OUcoSESV+o668Tkb+5x4qUzBcDjwS5bQlu4=; b=jAMCC9vprJu+ysVd0eFbDf6rACzfpwOYJgKy0c44d1TaPAwikF/mvNA42GgD74+bA1 D8B1/E/bM77jT1bUJeYCsqtR7qzSV2zsGjwe2kA4oWRKJFv1GP7tcUpqUNOfZ8dmq0WX G0pNgW5RLQWChMGbUsHK7bFIaThuzpeYmCQ9TnuTbFJk95wF7tdK9b/9JYcHCu7hH+G3 fhMBmvlvEzVcoXicMxLmVhtZ+7toj8+gfEhwedB9vUPH23lKTNiFzO5DdH2n2e1jp4Aq pGy73rxcz4zZp9BqqkxWevlqw61hR2r8zICDr7TacdCpjEwtwS8nFggGL2iVHHttYaru 6cgQ== X-Gm-Message-State: ANoB5pm8d+XooTJLvP3hlVNiRmjpLayvaMW1MkVbt+hDlATSXiI13UZc CnM61e0XBbrSNC7u8BtkxpzZvA== X-Google-Smtp-Source: AA0mqf578qz1XUgN6HFBVYwJAXNHPJ3BBOD/Wkd1Rvq4auQ4eWm7K69XG3NJMUYIVtLB9QZwVqgcoA== X-Received: by 2002:adf:ded1:0:b0:242:673a:d9e0 with SMTP id i17-20020adfded1000000b00242673ad9e0mr8087914wrn.134.1670441012430; Wed, 07 Dec 2022 11:23:32 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id w1-20020a5d5441000000b002422b462975sm19400355wrv.34.2022.12.07.11.23.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 11:23:31 -0800 (PST) From: Neil Armstrong Date: Wed, 07 Dec 2022 20:23:23 +0100 Subject: [PATCH v3 1/5] dt-bindings: remoteproc: qcom: adsp: move memory-region and firmware-name out of pas-common MIME-Version: 1.0 Message-Id: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-1-62162a1df718@linaro.org> References: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-0-62162a1df718@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-0-62162a1df718@linaro.org> To: Amol Maheshwari , Srinivas Kandagatla , Bjorn Andersson , Krzysztof Kozlowski , Andy Gross , Konrad Dybcio , Rob Herring , Mathieu Poirier , Manivannan Sadhasivam Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Neil Armstrong , linux-remoteproc@vger.kernel.org, Abel Vesa , linux-kernel@vger.kernel.org X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move memory-region and firmware-name definitions out of qcom,pas-common.yaml since they will be redefined differently for SM8550 PAS bindings documentation. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml | 4 ++++ Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml | 8 -------- Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml | 8 ++++++++ Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml | 8 ++++++++ .../devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml | 8 ++++++++ .../devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml | 8 ++++++++ Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml | 8 ++++++++ Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml | 8 ++++++++ Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml | 8 ++++++++ Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml | 8 ++++++++ 10 files changed, 68 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml index 9af2db72b337..5b55a22182ce 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml @@ -39,6 +39,10 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: Reference to the AOSS side-channel message RAM. + memory-region: + maxItems: 1 + description: Reference to the reserved-memory for the Hexagon core + required: - compatible diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml index 1d5e01c8d8bc..171ef85de193 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml @@ -52,14 +52,6 @@ properties: minItems: 1 maxItems: 3 - firmware-name: - $ref: /schemas/types.yaml#/definitions/string - description: Firmware name for the Hexagon core - - memory-region: - maxItems: 1 - description: Reference to the reserved-memory for the Hexagon core - qcom,smem-states: $ref: /schemas/types.yaml#/definitions/phandle-array description: States used by the AP to signal the Hexagon core diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml index 007349ef51ed..5efa0e5c0439 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml @@ -41,6 +41,14 @@ properties: power-domain-names: false smd-edge: false + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml index 6fd768609a66..5cefd2c58593 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml @@ -50,12 +50,20 @@ properties: - const: mx - const: mss + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + qcom,qmp: $ref: /schemas/types.yaml#/definitions/phandle description: Reference to the AOSS side-channel message RAM. smd-edge: false + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml index 3026cfde5582..c1f8dd8d0e4c 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml @@ -37,6 +37,14 @@ properties: smd-edge: false + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml index c08274aaa6f8..f6fbc531dc28 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml @@ -37,6 +37,14 @@ properties: smd-edge: false + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml index cbeaa00ca4d4..c66e298462c7 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml @@ -45,12 +45,20 @@ properties: - const: cx - const: mss + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + qcom,qmp: $ref: /schemas/types.yaml#/definitions/phandle description: Reference to the AOSS side-channel message RAM. smd-edge: false + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml index 911529400142..fee02fa800b5 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml @@ -35,8 +35,16 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: Reference to the AOSS side-channel message RAM. + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + smd-edge: false + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml index b934252cf02b..2c085ac2c3fb 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml @@ -39,8 +39,16 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: Reference to the AOSS side-channel message RAM. + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + smd-edge: false + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml index 853f97d6879f..af24f9a3cdf1 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml @@ -42,6 +42,14 @@ properties: smd-edge: false + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + required: - compatible - reg From patchwork Wed Dec 7 19:23:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13067551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5ADEC6370A for ; Wed, 7 Dec 2022 19:23:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229840AbiLGTXk (ORCPT ); Wed, 7 Dec 2022 14:23:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229660AbiLGTXh (ORCPT ); Wed, 7 Dec 2022 14:23:37 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7215663EF for ; Wed, 7 Dec 2022 11:23:34 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id h10so19962527wrx.3 for ; Wed, 07 Dec 2022 11:23:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IKTKywHyIPCXBSUcfJeW1/Q8bxFrGPEAhsZglTH+lJs=; b=VhLcSFA69TfU3tTYA+KzSGAqs4oCfIasSQUJtqfnLkN4gidG2uNmUyFHUtyWx4ay3D jwBIfv/CSvkPZHF9dGZ3ISZpKtzbpSC30XzcGCxyDYsUezcyoeKhnnD4TPfVDyV77b7K wqM4mazTIvYP5WGQHISThrK0SSCTEUW1Ap3wvktC9o/nKK+aD6y0rFqecEVU/sXXCrGl 3fEjksXD2bAmWXTCXjPP7nqa5hfF0cH53QNBhwfCAD+xQ3qS0Wl3kbNpxWDPR/3jUW7a V7FzY7IoZcBP4vAN0cCs6ytpq4/+FeHGH8WH3VuIoYrt6f+/i+PM12hIgLkFsHnKn0bJ PLSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IKTKywHyIPCXBSUcfJeW1/Q8bxFrGPEAhsZglTH+lJs=; b=NtxAlMMPWDQowPuswaTSyl9ivNa21b9WOv0l2bmgr25nbPxhLwNRtPzv1yXAsxWOBa FGEf/vcUDcchAO5FPEW8Et8R4KiYHkgdTkbg+P8AkxH08rYl0+IBrFVvPx7iUhGevp7O wXJxcAet87DpUPZMNhH5VbVVhWB27o1GMOtyx/srmgBMmA1bNbSk0YHtXISiZo0O8ihj JMRchNKa8dzVrFrBSOKgg0sHwpdpi/f6N4kyT2TyJgM4X8tiv9ZP3Iw9292j6MsvIZsa U8Uj4Yg/v3K3TStiWspDvMuuf0Ckbqc3x82abB0KlFw2fV0uUyOHkYbIH023XaG4yzDW cpKg== X-Gm-Message-State: ANoB5pkFrHwoleXw/mp+RQVaeKBLXKga5zCiiGfYNZUahD4mzcyjP3/b VYufHCFfiLSHsE/9E2wtCEF/kA== X-Google-Smtp-Source: AA0mqf61O+6qmFAt/ReXwL6EYsS8v7RI0vpNMnZgQa158zyNM8AudnisBmfCAS/cr+4SfAq9+JJw7A== X-Received: by 2002:adf:eb02:0:b0:236:5e6a:7ee with SMTP id s2-20020adfeb02000000b002365e6a07eemr57392748wrn.618.1670441013364; Wed, 07 Dec 2022 11:23:33 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id w1-20020a5d5441000000b002422b462975sm19400355wrv.34.2022.12.07.11.23.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 11:23:33 -0800 (PST) From: Neil Armstrong Date: Wed, 07 Dec 2022 20:23:24 +0100 Subject: [PATCH v3 2/5] dt-bindings: remoteproc: qcom: adsp: document sm8550 adsp, cdsp & mpss compatible MIME-Version: 1.0 Message-Id: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-2-62162a1df718@linaro.org> References: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-0-62162a1df718@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-0-62162a1df718@linaro.org> To: Amol Maheshwari , Srinivas Kandagatla , Bjorn Andersson , Krzysztof Kozlowski , Andy Gross , Konrad Dybcio , Rob Herring , Mathieu Poirier , Manivannan Sadhasivam Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Neil Armstrong , linux-remoteproc@vger.kernel.org, Abel Vesa , linux-kernel@vger.kernel.org X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This documents the compatible for the component used to boot the aDSP, cDSP and MPSS on the SM8550 SoC. The SM8550 boot process on SM8550 now requires a secondary "Devicetree" firmware to be passed along the main Firmware, and the cDSP a new power domain named "NSP". A third memory domain for the DSM memory zone is also needed for the MPSS PAS bindings. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski --- .../bindings/remoteproc/qcom,sm8550-pas.yaml | 178 +++++++++++++++++++++ 1 file changed, 178 insertions(+) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml new file mode 100644 index 000000000000..ae612809e260 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm8550-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam + +description: + Qualcomm SM8550 SoC Peripheral Authentication Service loads and boots firmware + on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + - qcom,sm8550-cdsp-pas + - qcom,sm8550-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + items: + - description: Firmware name of the Hexagon core + - description: Firmware name of the Hexagon Devicetree + + memory-region: + minItems: 2 + items: + - description: Memory region for main Firmware authentication + - description: Memory region for Devicetree Firmware authentication + - description: DSM Memory region + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + - qcom,sm8550-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + memory-region: + maxItems: 2 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + memory-region: + minItems: 3 + + - if: + properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + + - if: + properties: + compatible: + enum: + - qcom,sm8550-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MXC power domain + power-domain-names: + items: + - const: cx + - const: mxc + - if: + properties: + compatible: + enum: + - qcom,sm8550-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MXC power domain + - description: NSP power domain + power-domain-names: + items: + - const: cx + - const: mxc + - const: nsp + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + remoteproc@30000000 { + compatible = "qcom,sm8550-adsp-pas"; + reg = <0x030000000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&adsp_mem>, <&dtb_adsp_mem>; + + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + + power-domains = <&rpmhpd_sm8550_lcx>, + <&rpmhpd_sm8550_lmx>; + power-domain-names = "lcx", "lmx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; From patchwork Wed Dec 7 19:23:25 2022 Content-Type: text/plain; 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Wed, 07 Dec 2022 11:23:34 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id w1-20020a5d5441000000b002422b462975sm19400355wrv.34.2022.12.07.11.23.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Dec 2022 11:23:34 -0800 (PST) From: Neil Armstrong Date: Wed, 07 Dec 2022 20:23:25 +0100 Subject: [PATCH v3 3/5] remoteproc: qcom_q6v5_pas: add support for dtb co-firmware loading MIME-Version: 1.0 Message-Id: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-3-62162a1df718@linaro.org> References: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-0-62162a1df718@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-0-62162a1df718@linaro.org> To: Amol Maheshwari , Srinivas Kandagatla , Bjorn Andersson , Krzysztof Kozlowski , Andy Gross , Konrad Dybcio , Rob Herring , Mathieu Poirier , Manivannan Sadhasivam Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Neil Armstrong , linux-remoteproc@vger.kernel.org, Abel Vesa , linux-kernel@vger.kernel.org X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Starting from the SM8550 SoC, starting the aDSP, cDSP and MPSS will require loading a separate "Devicetree" firmware. In order to satisfy the load & authentication order required by the SM8550 SoC, the following is implemented: - "Devicetree" firmware request & load in dedicated memory - Q6V5 prepare - Power Domain & Clocks enable - "Devicetree" firmware authentication - Main firmware load in dedicated memory - Main firmware authentication - Q6V5 startup - "Devicetree" firmware metadata release - Main metadata release When booting older platforms, the "Devicetree" steps would be bypassed and the load & authentication order would still be valid. Signed-off-by: Neil Armstrong --- drivers/remoteproc/qcom_q6v5_pas.c | 134 +++++++++++++++++++++++++++++++++---- 1 file changed, 121 insertions(+), 13 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 6afd0941e552..4fe09c7f25bd 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -35,7 +35,9 @@ struct adsp_data { int crash_reason_smem; const char *firmware_name; + const char *dtb_firmware_name; int pas_id; + int dtb_pas_id; unsigned int minidump_id; bool has_aggre2_clk; bool auto_boot; @@ -65,20 +67,29 @@ struct qcom_adsp { int proxy_pd_count; + const char *dtb_firmware_name; int pas_id; + int dtb_pas_id; unsigned int minidump_id; int crash_reason_smem; bool has_aggre2_clk; bool decrypt_shutdown; const char *info_name; + const struct firmware *firmware; + const struct firmware *dtb_firmware; + struct completion start_done; struct completion stop_done; phys_addr_t mem_phys; + phys_addr_t dtb_mem_phys; phys_addr_t mem_reloc; + phys_addr_t dtb_mem_reloc; void *mem_region; + void *dtb_mem_region; size_t mem_size; + size_t dtb_mem_size; struct qcom_rproc_glink glink_subdev; struct qcom_rproc_subdev smd_subdev; @@ -86,6 +97,7 @@ struct qcom_adsp { struct qcom_sysmon *sysmon; struct qcom_scm_pas_metadata pas_metadata; + struct qcom_scm_pas_metadata dtb_pas_metadata; }; static void adsp_minidump(struct rproc *rproc) @@ -160,6 +172,8 @@ static int adsp_unprepare(struct rproc *rproc) * here. */ qcom_scm_pas_metadata_release(&adsp->pas_metadata); + if (adsp->dtb_pas_id) + qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata); return 0; } @@ -169,20 +183,40 @@ static int adsp_load(struct rproc *rproc, const struct firmware *fw) struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; int ret; - ret = qcom_mdt_pas_init(adsp->dev, fw, rproc->firmware, adsp->pas_id, - adsp->mem_phys, &adsp->pas_metadata); - if (ret) - return ret; + /* Store firmware handle to be used in adsp_start() */ + adsp->firmware = fw; - ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, adsp->pas_id, - adsp->mem_region, adsp->mem_phys, adsp->mem_size, - &adsp->mem_reloc); - if (ret) - return ret; + if (adsp->dtb_pas_id) { + ret = request_firmware(&adsp->dtb_firmware, adsp->dtb_firmware_name, adsp->dev); + if (ret) { + dev_err(adsp->dev, "request_firmware failed for %s: %d\n", + adsp->dtb_firmware_name, ret); + return ret; + } - qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size); + ret = qcom_mdt_pas_init(adsp->dev, adsp->dtb_firmware, adsp->dtb_firmware_name, + adsp->dtb_pas_id, adsp->dtb_mem_phys, + &adsp->dtb_pas_metadata); + if (ret) + goto release_dtb_firmware; + + ret = qcom_mdt_load_no_init(adsp->dev, adsp->dtb_firmware, adsp->dtb_firmware_name, + adsp->dtb_pas_id, adsp->dtb_mem_region, + adsp->dtb_mem_phys, adsp->dtb_mem_size, + &adsp->dtb_mem_reloc); + if (ret) + goto release_dtb_metadata; + } return 0; + +release_dtb_metadata: + qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata); + +release_dtb_firmware: + release_firmware(adsp->dtb_firmware); + + return ret; } static int adsp_start(struct rproc *rproc) @@ -218,24 +252,55 @@ static int adsp_start(struct rproc *rproc) goto disable_cx_supply; } + if (adsp->dtb_pas_id) { + ret = qcom_scm_pas_auth_and_reset(adsp->dtb_pas_id); + if (ret) { + dev_err(adsp->dev, + "failed to authenticate dtb image and release reset\n"); + goto disable_px_supply; + } + } + + ret = qcom_mdt_pas_init(adsp->dev, adsp->firmware, rproc->firmware, adsp->pas_id, + adsp->mem_phys, &adsp->pas_metadata); + if (ret) + goto disable_px_supply; + + ret = qcom_mdt_load_no_init(adsp->dev, adsp->firmware, rproc->firmware, adsp->pas_id, + adsp->mem_region, adsp->mem_phys, adsp->mem_size, + &adsp->mem_reloc); + if (ret) + goto release_pas_metadata; + + qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size); + ret = qcom_scm_pas_auth_and_reset(adsp->pas_id); if (ret) { dev_err(adsp->dev, "failed to authenticate image and release reset\n"); - goto disable_px_supply; + goto release_pas_metadata; } ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000)); if (ret == -ETIMEDOUT) { dev_err(adsp->dev, "start timed out\n"); qcom_scm_pas_shutdown(adsp->pas_id); - goto disable_px_supply; + goto release_pas_metadata; } qcom_scm_pas_metadata_release(&adsp->pas_metadata); + if (adsp->dtb_pas_id) + qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata); + + /* Remove pointer to the loaded firmware, only valid in adsp_load() & adsp_start() */ + adsp->firmware = NULL; return 0; +release_pas_metadata: + qcom_scm_pas_metadata_release(&adsp->pas_metadata); + if (adsp->dtb_pas_id) + qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata); disable_px_supply: if (adsp->px_supply) regulator_disable(adsp->px_supply); @@ -251,6 +316,9 @@ static int adsp_start(struct rproc *rproc) disable_irqs: qcom_q6v5_unprepare(&adsp->q6v5); + /* Remove pointer to the loaded firmware, only valid in adsp_load() & adsp_start() */ + adsp->firmware = NULL; + return ret; } @@ -284,6 +352,12 @@ static int adsp_stop(struct rproc *rproc) if (ret) dev_err(adsp->dev, "failed to shutdown: %d\n", ret); + if (adsp->dtb_pas_id) { + ret = qcom_scm_pas_shutdown(adsp->dtb_pas_id); + if (ret) + dev_err(adsp->dev, "failed to shutdown dtb: %d\n", ret); + } + handover = qcom_q6v5_unprepare(&adsp->q6v5); if (handover) qcom_pas_handover(&adsp->q6v5); @@ -461,6 +535,28 @@ static int adsp_alloc_memory_region(struct qcom_adsp *adsp) return -EBUSY; } + if (!adsp->dtb_pas_id) + return 0; + + node = of_parse_phandle(adsp->dev->of_node, "memory-region", 1); + if (!node) { + dev_err(adsp->dev, "no dtb memory-region specified\n"); + return -EINVAL; + } + + ret = of_address_to_resource(node, 0, &r); + if (ret) + return ret; + + adsp->dtb_mem_phys = adsp->dtb_mem_reloc = r.start; + adsp->dtb_mem_size = resource_size(&r); + adsp->dtb_mem_region = devm_ioremap_wc(adsp->dev, adsp->dtb_mem_phys, adsp->dtb_mem_size); + if (!adsp->dtb_mem_region) { + dev_err(adsp->dev, "unable to map dtb memory region: %pa+%zx\n", + &r.start, adsp->dtb_mem_size); + return -EBUSY; + } + return 0; } @@ -469,7 +565,7 @@ static int adsp_probe(struct platform_device *pdev) const struct adsp_data *desc; struct qcom_adsp *adsp; struct rproc *rproc; - const char *fw_name; + const char *fw_name, *dtb_fw_name = NULL; const struct rproc_ops *ops = &adsp_ops; int ret; @@ -486,6 +582,14 @@ static int adsp_probe(struct platform_device *pdev) if (ret < 0 && ret != -EINVAL) return ret; + if (desc->dtb_firmware_name) { + dtb_fw_name = desc->dtb_firmware_name; + ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", 1, + &dtb_fw_name); + if (ret < 0 && ret != -EINVAL) + return ret; + } + if (desc->minidump_id) ops = &adsp_minidump_ops; @@ -507,6 +611,10 @@ static int adsp_probe(struct platform_device *pdev) adsp->has_aggre2_clk = desc->has_aggre2_clk; adsp->info_name = desc->sysmon_name; adsp->decrypt_shutdown = desc->decrypt_shutdown; + if (dtb_fw_name) { + adsp->dtb_firmware_name = dtb_fw_name; + adsp->dtb_pas_id = desc->dtb_pas_id; + } platform_set_drvdata(pdev, adsp); ret = device_init_wakeup(adsp->dev, true); From patchwork Wed Dec 7 19:23:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13067553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95A73C4708D for ; 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Wed, 07 Dec 2022 11:23:35 -0800 (PST) From: Neil Armstrong Date: Wed, 07 Dec 2022 20:23:26 +0100 Subject: [PATCH v3 4/5] remoteproc: qcom_q6v5_pas: add support for assigning memory to firmware MIME-Version: 1.0 Message-Id: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-4-62162a1df718@linaro.org> References: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-0-62162a1df718@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-0-62162a1df718@linaro.org> To: Amol Maheshwari , Srinivas Kandagatla , Bjorn Andersson , Krzysztof Kozlowski , Andy Gross , Konrad Dybcio , Rob Herring , Mathieu Poirier , Manivannan Sadhasivam Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Neil Armstrong , linux-remoteproc@vger.kernel.org, Abel Vesa , linux-kernel@vger.kernel.org X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Starting with SM8550, the DSM memory must now be shared to the firmware by the APPS process instead of beeing defined in the carveout memory reserved for MPSS. In order to handle that, add a region_assign_idx in adsp_data to specify with index of memory-region must be assigned to the MPSS via the qcom_scm_assign_mem() call at probe time. Signed-off-by: Neil Armstrong --- drivers/remoteproc/qcom_q6v5_pas.c | 71 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 4fe09c7f25bd..d6a288432b6c 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -49,6 +49,8 @@ struct adsp_data { const char *ssr_name; const char *sysmon_name; int ssctl_id; + + int region_assign_idx; }; struct qcom_adsp { @@ -86,10 +88,15 @@ struct qcom_adsp { phys_addr_t dtb_mem_phys; phys_addr_t mem_reloc; phys_addr_t dtb_mem_reloc; + phys_addr_t region_assign_phys; void *mem_region; void *dtb_mem_region; size_t mem_size; size_t dtb_mem_size; + size_t region_assign_size; + + int region_assign_idx; + int region_assign_perms; struct qcom_rproc_glink glink_subdev; struct qcom_rproc_subdev smd_subdev; @@ -560,6 +567,64 @@ static int adsp_alloc_memory_region(struct qcom_adsp *adsp) return 0; } +static int adsp_assign_memory_region(struct qcom_adsp *adsp) +{ + struct qcom_scm_vmperm perm; + struct device_node *node; + struct resource r; + int ret; + + if (!adsp->region_assign_idx) + return 0; + + node = of_parse_phandle(adsp->dev->of_node, "memory-region", adsp->region_assign_idx); + if (!node) { + dev_err(adsp->dev, "missing shareable memory-region\n"); + return -EINVAL; + } + + ret = of_address_to_resource(node, 0, &r); + if (ret) + return ret; + + perm.vmid = QCOM_SCM_VMID_MSS_MSA; + perm.perm = QCOM_SCM_PERM_RW; + + adsp->region_assign_phys = r.start; + adsp->region_assign_size = resource_size(&r); + adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS); + + ret = qcom_scm_assign_mem(adsp->region_assign_phys, + adsp->region_assign_size, + &adsp->region_assign_perms, + &perm, 1); + if (ret < 0) { + dev_err(adsp->dev, "assign memory failed\n"); + return ret; + } + + return 0; +} + +static void adsp_unassign_memory_region(struct qcom_adsp *adsp) +{ + struct qcom_scm_vmperm perm; + int ret; + + if (!adsp->region_assign_idx) + return; + + perm.vmid = QCOM_SCM_VMID_HLOS; + perm.perm = QCOM_SCM_PERM_RW; + + ret = qcom_scm_assign_mem(adsp->region_assign_phys, + adsp->region_assign_size, + &adsp->region_assign_perms, + &perm, 1); + if (ret < 0) + dev_err(adsp->dev, "unassign memory failed\n"); +} + static int adsp_probe(struct platform_device *pdev) { const struct adsp_data *desc; @@ -611,6 +676,7 @@ static int adsp_probe(struct platform_device *pdev) adsp->has_aggre2_clk = desc->has_aggre2_clk; adsp->info_name = desc->sysmon_name; adsp->decrypt_shutdown = desc->decrypt_shutdown; + adsp->region_assign_idx = desc->region_assign_idx; if (dtb_fw_name) { adsp->dtb_firmware_name = dtb_fw_name; adsp->dtb_pas_id = desc->dtb_pas_id; @@ -625,6 +691,10 @@ static int adsp_probe(struct platform_device *pdev) if (ret) goto free_rproc; + ret = adsp_assign_memory_region(adsp); + if (ret) + goto free_rproc; + ret = adsp_init_clock(adsp); if (ret) goto free_rproc; @@ -676,6 +746,7 @@ static int adsp_remove(struct platform_device *pdev) rproc_del(adsp->rproc); qcom_q6v5_deinit(&adsp->q6v5); + adsp_unassign_memory_region(adsp); qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev); qcom_remove_sysmon_subdev(adsp->sysmon); qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev); From patchwork Wed Dec 7 19:23:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13067555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB2A1C352A1 for ; Wed, 7 Dec 2022 19:24:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229635AbiLGTYA (ORCPT ); Wed, 7 Dec 2022 14:24:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229777AbiLGTXj (ORCPT ); Wed, 7 Dec 2022 14:23:39 -0500 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D2E468C49 for ; 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Wed, 07 Dec 2022 11:23:36 -0800 (PST) From: Neil Armstrong Date: Wed, 07 Dec 2022 20:23:27 +0100 Subject: [PATCH v3 5/5] remoteproc: qcom_q6v5_pas: add sm8550 adsp, cdsp & mpss compatible & data MIME-Version: 1.0 Message-Id: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-5-62162a1df718@linaro.org> References: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-0-62162a1df718@linaro.org> In-Reply-To: <20221114-narmstrong-sm8550-upstream-remoteproc-v3-0-62162a1df718@linaro.org> To: Amol Maheshwari , Srinivas Kandagatla , Bjorn Andersson , Krzysztof Kozlowski , Andy Gross , Konrad Dybcio , Rob Herring , Mathieu Poirier , Manivannan Sadhasivam Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Neil Armstrong , linux-remoteproc@vger.kernel.org, Abel Vesa , linux-kernel@vger.kernel.org X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This adds the compatible & data for the aDSP, cDSP and MPSS found in the SM8550 SoC. This platform requires the "Devicetree" firmware to be loaded along the main firmware. The MPSS DSM memory to be assigned to the MPSS subsystem is the third memory-region entry as defined in the bindings. Signed-off-by: Neil Armstrong --- drivers/remoteproc/qcom_q6v5_pas.c | 66 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index d6a288432b6c..2a29ffad83eb 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -1125,6 +1125,69 @@ static const struct adsp_data sm8450_mpss_resource = { .ssctl_id = 0x12, }; +static const struct adsp_data sm8550_adsp_resource = { + .crash_reason_smem = 423, + .firmware_name = "adsp.mdt", + .dtb_firmware_name = "adsp_dtb.mdt", + .pas_id = 1, + .dtb_pas_id = 0x24, + .minidump_id = 5, + .has_aggre2_clk = false, + .auto_boot = false, + .proxy_pd_names = (char*[]){ + "lcx", + "lmx", + NULL + }, + .load_state = "adsp", + .ssr_name = "lpass", + .sysmon_name = "adsp", + .ssctl_id = 0x14, +}; + +static const struct adsp_data sm8550_cdsp_resource = { + .crash_reason_smem = 601, + .firmware_name = "cdsp.mdt", + .dtb_firmware_name = "cdsp_dtb.mdt", + .pas_id = 18, + .dtb_pas_id = 0x25, + .minidump_id = 7, + .has_aggre2_clk = false, + .auto_boot = false, + .proxy_pd_names = (char*[]){ + "cx", + "mxc", + "nsp", + NULL + }, + .load_state = "cdsp", + .ssr_name = "cdsp", + .sysmon_name = "cdsp", + .ssctl_id = 0x17, +}; + +static const struct adsp_data sm8550_mpss_resource = { + .crash_reason_smem = 421, + .firmware_name = "modem.mdt", + .dtb_firmware_name = "modem_dtb.mdt", + .pas_id = 4, + .dtb_pas_id = 0x26, + .minidump_id = 3, + .has_aggre2_clk = false, + .auto_boot = false, + .decrypt_shutdown = true, + .proxy_pd_names = (char*[]){ + "cx", + "mss", + NULL + }, + .load_state = "modem", + .ssr_name = "mpss", + .sysmon_name = "modem", + .ssctl_id = 0x12, + .region_assign_idx = 2, +}; + static const struct of_device_id adsp_of_match[] = { { .compatible = "qcom,msm8226-adsp-pil", .data = &adsp_resource_init}, { .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init}, @@ -1165,6 +1228,9 @@ static const struct of_device_id adsp_of_match[] = { { .compatible = "qcom,sm8450-cdsp-pas", .data = &sm8350_cdsp_resource}, { .compatible = "qcom,sm8450-slpi-pas", .data = &sm8350_slpi_resource}, { .compatible = "qcom,sm8450-mpss-pas", .data = &sm8450_mpss_resource}, + { .compatible = "qcom,sm8550-adsp-pas", .data = &sm8550_adsp_resource}, + { .compatible = "qcom,sm8550-cdsp-pas", .data = &sm8550_cdsp_resource}, + { .compatible = "qcom,sm8550-mpss-pas", .data = &sm8550_mpss_resource}, { }, }; MODULE_DEVICE_TABLE(of, adsp_of_match);