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Peter Anvin" , Alexey Kardashevskiy Subject: [PATCH kernel v2 1/3] x86/amd: Cache values in percpu variables Date: Fri, 9 Dec 2022 15:38:02 +1100 Message-ID: <20221209043804.942352-2-aik@amd.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209043804.942352-1-aik@amd.com> References: <20221209043804.942352-1-aik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT105:EE_|MN2PR12MB4109:EE_ X-MS-Office365-Filtering-Correlation-Id: 0af23deb-bee8-412b-0377-08dad99f517f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iTyU4mXKeZbfp84yWzFEZm4QMTD1XnKd2JquxRicw9JLRVyWez0QOCgUhK7k5N8/zPXhYvpVVEz0IKpN4EJQ5i6hSb8ODt5fHAOfDeOqMXyXKJBtZMvgTF5rJNO7f6i62mZVAsm6EpNIzHhPprcy5aikCeXkbABCbGK1SFbPOwIhA5plllIcv+6YiQjC8FQ7BNMOnRdkLBqFGB9opv9vK6tpkyT+RKVUjKVNRk+DBzkeP1/XGqmHTp61RdohM4aTN7IVlhp6XyD3ta14sbSfCy9fcCtuB1SvJqrcWa5m/LrkOF8zxG0+N3jDQQCk9Uav5vmVKNIpThxeTna6PwoRfj9M2BJzVIvzagEIsXafz9LIdAnKfF1sLg2eK1eUCIkgVmqNasjAWT6xRhs2hOYVqQ17O4knlCm/RUwgOy3vmWFFTKJ9MGeZnL/ldP9DKv18jshXqjhbwyhb6FmkS88lTh7zkmZaqefaA3tZEkVMZRcZCIeTJPXxNaDTRJvWqFc3eSyYHIGVfA0k6m21M5Jnb9yfXNOWT8tNBKgDxUXgPOZOKC57lPPBMU4iIPxNRMF+o1tdOhobgiM7wafPkT2BZX7jhhSPe9te9EzF0cVPSaxLgqJ11KWiNYlS8UmZcWZmpxj706jn3YN3qEWizVY2wqOT3vQzMJ+zBqzp5S8vqInCY+Avo5Dcp5bYAzU1CT1Aly78HPShmrVtmX6ABeJNnKs7P2ocO376N3WNVjWEghw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199015)(46966006)(40470700004)(36840700001)(36860700001)(8676002)(336012)(7416002)(1076003)(16526019)(83380400001)(40480700001)(2906002)(2616005)(70586007)(40460700003)(36756003)(5660300002)(8936002)(41300700001)(356005)(54906003)(316002)(6916009)(70206006)(4326008)(81166007)(6666004)(47076005)(426003)(478600001)(26005)(82740400003)(82310400005)(186003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2022 04:39:11.5246 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0af23deb-bee8-412b-0377-08dad99f517f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT105.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4109 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Reading DR[0-3]_ADDR_MASK MSRs takes about 250 cycles which is going to be noticeable with the AMD KVM SEV-ES DebugSwap feature enabled. KVM is going to store host's DR[0-3] and DR[0-3]_ADDR_MASK before switching to a guest; the hardware is going to swap these on VMRUN and VMEXIT. Store MSR values passsed to set_dr_addr_mask() in percpu values (when changed) and return them via new amd_get_dr_addr_mask(). The gain here is about 10x. As amd_set_dr_addr_mask() uses the array too, change the @dr type to unsigned to avoid checking for <0. While at it, replace deprecated boot_cpu_has() with cpu_feature_enabled() in set_dr_addr_mask(). Signed-off-by: Alexey Kardashevskiy --- Changes: v2: * reworked to use arrays * set() skips wrmsr() when the mask is not changed * added stub for get_dr_addr_mask() * changed @dr type to unsigned * s/boot_cpu_has/cpu_feature_enabled/ * added amd_ prefix --- arch/x86/include/asm/debugreg.h | 9 +++- arch/x86/kernel/cpu/amd.c | 45 ++++++++++++++------ 2 files changed, 38 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h index cfdf307ddc01..59f97ba25d5f 100644 --- a/arch/x86/include/asm/debugreg.h +++ b/arch/x86/include/asm/debugreg.h @@ -126,9 +126,14 @@ static __always_inline void local_db_restore(unsigned long dr7) } #ifdef CONFIG_CPU_SUP_AMD -extern void set_dr_addr_mask(unsigned long mask, int dr); +extern void set_dr_addr_mask(unsigned long mask, unsigned int dr); +extern unsigned long amd_get_dr_addr_mask(unsigned int dr); #else -static inline void set_dr_addr_mask(unsigned long mask, int dr) { } +static inline void set_dr_addr_mask(unsigned long mask, unsigned int dr) { } +static inline unsigned long amd_get_dr_addr_mask(unsigned int dr) +{ + return 0; +} #endif #endif /* _ASM_X86_DEBUGREG_H */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index c75d75b9f11a..9ac5a19f89b9 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1158,24 +1158,41 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) return false; } -void set_dr_addr_mask(unsigned long mask, int dr) +DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask); + +static unsigned int amd_msr_dr_addr_masks[] = { + MSR_F16H_DR0_ADDR_MASK, + MSR_F16H_DR1_ADDR_MASK - 1 + 1, + MSR_F16H_DR1_ADDR_MASK - 1 + 2, + MSR_F16H_DR1_ADDR_MASK - 1 + 3 +}; + +void set_dr_addr_mask(unsigned long mask, unsigned int dr) { - if (!boot_cpu_has(X86_FEATURE_BPEXT)) + if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) return; - switch (dr) { - case 0: - wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); - break; - case 1: - case 2: - case 3: - wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); - break; - default: - break; - } + if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) + return; + + if (per_cpu(amd_dr_addr_mask, smp_processor_id())[dr] == mask) + return; + + wrmsr(amd_msr_dr_addr_masks[dr], mask, 0); + per_cpu(amd_dr_addr_mask, smp_processor_id())[dr] = mask; +} + +unsigned long amd_get_dr_addr_mask(unsigned int dr) +{ + if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) + return 0; + + if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) + return 0; + + return per_cpu(amd_dr_addr_mask[dr], smp_processor_id()); } +EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask); u32 amd_get_highest_perf(void) { From patchwork Fri Dec 9 04:38:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Kardashevskiy X-Patchwork-Id: 13069218 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B659CC4332F for ; Fri, 9 Dec 2022 04:40:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229772AbiLIEkV (ORCPT ); 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Thu, 8 Dec 2022 22:39:22 -0600 From: Alexey Kardashevskiy To: CC: , , Venu Busireddy , Tony Luck , Tom Lendacky , Thomas Gleixner , "Sean Christopherson" , Sandipan Das , Peter Zijlstra , Pawan Gupta , Paolo Bonzini , Michael Roth , Mario Limonciello , Jan Kara , Ingo Molnar , Huang Rui , Dave Hansen , Daniel Sneddon , Brijesh Singh , Borislav Petkov , Arnaldo Carvalho de Melo , Andrew Cooper , Alexander Shishkin , Adrian Hunter , "Jason A. Donenfeld" , "H. Peter Anvin" , Alexey Kardashevskiy Subject: [PATCH kernel v2 2/3] KVM: SEV: Enable data breakpoints in SEV-ES Date: Fri, 9 Dec 2022 15:38:03 +1100 Message-ID: <20221209043804.942352-3-aik@amd.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209043804.942352-1-aik@amd.com> References: <20221209043804.942352-1-aik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT056:EE_|CY8PR12MB8241:EE_ X-MS-Office365-Filtering-Correlation-Id: 1087852b-661b-40fc-208f-08dad99f5f4f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1QhXYmRo6AtoJS8QnfveJM+cjZ69/7kPbmOBySpsl+4w4LVvsEhe3JrL/Vpxj190GtYZ99Apw/Xu1YywZ+Jqet/0QtAwcGInR+oK76GEtB0nfE+gToa7JhoMhltM/PYSvZuefW/plH5uImS4wwMk6tL2fdIVH00BhhAWxt1daiK6bxki6VpJyeCTcBp9mgQEjdhG8mYpI8Rd0LcIOZmgj1cU+xnxIxZzVw8/Nmt3fUtxt5eSMj6gKG/WplDGUASg0F5H9QO0INxHvoEnCWVEB0dRWI18Uvi5btb8B5Y7+z6PcmXMcBAg36m0fEAQ9FJgCvcKXW2RpLjuWlgmnn3Hgd92i4Ikpuz/KDxGTx1vEqA7HOa7UdB5RzN7nGW/G/gaBMlrwn94wN/6zlauz+sRXlvsKRHf5+QwqmY4b3b3FIW0QCj3NCICn3FD+kdg2stfoCySfNQgM7jc+X/iRk91YJ5SQx+J3sHRfrh4zUin2uP8QmmVtvnsdKTZs595jFbYYoYIWQO4z0gy7IEEqlRNu0k85qtQ8kcLV5s1Mq5NG/nGtCT4fawfnNWamY5XL56M65wpRsJbZehCO7Bliyjot5PiwQZlG5SKh+IHsrf+ke/UIOpU1dFn9XTCgs3wCuoyU5GCfQvImogWBC6QThih2+HDL5ZC7ifcgvWs2Bp0olp3uTg7Wu3rh3B2+LU1TOKHuIRkK0c70hyoKn9FRBKH4rBDNy+eL7eLUII7F4j1FkY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(376002)(346002)(136003)(451199015)(36840700001)(46966006)(40470700004)(82740400003)(6666004)(36860700001)(8936002)(478600001)(8676002)(4326008)(70586007)(70206006)(40460700003)(36756003)(356005)(81166007)(41300700001)(54906003)(6916009)(40480700001)(316002)(426003)(47076005)(2616005)(336012)(1076003)(186003)(16526019)(2906002)(26005)(82310400005)(7416002)(5660300002)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2022 04:39:34.6989 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1087852b-661b-40fc-208f-08dad99f5f4f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8241 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org AMD Milan (Fam 19h) introduces support for the swapping, as type 'B', of DR[0-3] and DR[0-3]_ADDR_MASK registers. Software enables this by setting SEV_FEATURES[5] (called "DebugSwap") in the VMSA which makes data breakpoints work in SEV-ES VMs. For type 'B' swaps the hardware saves/restores the VM state on VMEXIT/VMRUN in VMSA, and restores the host state on VMEXIT. Enable DebugSwap in VMSA but only if CPUID Fn80000021_EAX[0] ("NoNestedDataBp", "Processor ignores nested data breakpoints") is supported by the SOC as otherwise a malicious guest can cause the infinite #DB loop DoS. Save DR[0-3] / DR[0-3]_ADDR_MASK in the host save area before VMRUN as type 'B' swap does not do this part. Eliminate DR7 and #DB intercepts as: - they are not needed when DebugSwap is supported; - #VC for these intercepts is most likely not supported anyway and kills the VM. Keep DR7 intercepted unless DebugSwap enabled to prevent the infinite #DB loop DoS. Signed-off-by: Alexey Kardashevskiy --- Changes: v2: * debug_swap moved from vcpu to module_param * rewrote commit log --- "DR7 access must remain intercepted for an SEV-ES guest" - I could not figure out the exact reasoning why it is there in the first place, IIUC this is to prevent loop of #DBs in the VM. --- Tested with: === int x; int main(int argc, char *argv[]) { x = 1; return 0; } === gcc -g a.c rsync a.out ruby-954vm:~/ ssh -t ruby-954vm 'gdb -ex "file a.out" -ex "watch x" -ex r' where ruby-954vm is a VM. With "/sys/module/kvm_amd/parameters/debug_swap = 0", gdb does not stop on the watchpoint, with "= 1" - gdb does. --- arch/x86/include/asm/svm.h | 1 + arch/x86/kvm/svm/svm.h | 16 ++++++++--- arch/x86/kvm/svm/sev.c | 29 ++++++++++++++++++++ arch/x86/kvm/svm/svm.c | 3 +- 4 files changed, 44 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 0361626841bc..373a0edda588 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -273,6 +273,7 @@ enum avic_ipi_failure_cause { #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL +#define SVM_SEV_FEAT_DEBUG_SWAP BIT(5) struct vmcb_seg { u16 selector; diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 199a2ecef1ce..0fae611abe4a 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -386,6 +386,8 @@ static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u3 return test_bit(bit, (unsigned long *)&control->intercepts); } +extern bool sev_es_is_debug_swap_enabled(void); + static inline void set_dr_intercepts(struct vcpu_svm *svm) { struct vmcb *vmcb = svm->vmcb01.ptr; @@ -407,8 +409,10 @@ static inline void set_dr_intercepts(struct vcpu_svm *svm) vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE); } - vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); - vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); + if (!sev_es_guest(svm->vcpu.kvm) || !sev_es_is_debug_swap_enabled()) { + vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); + vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); + } recalc_intercepts(svm); } @@ -419,8 +423,12 @@ static inline void clr_dr_intercepts(struct vcpu_svm *svm) vmcb->control.intercepts[INTERCEPT_DR] = 0; - /* DR7 access must remain intercepted for an SEV-ES guest */ - if (sev_es_guest(svm->vcpu.kvm)) { + /* + * DR7 access must remain intercepted for an SEV-ES guest unless DebugSwap + * (depends on NO_NESTED_DATA_BP) is enabled as otherwise a VM writing to DR7 + * from the #DB handler may trigger infinite loop of #DB's. + */ + if (sev_es_guest(svm->vcpu.kvm) && !sev_es_is_debug_swap_enabled()) { vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ); vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE); } diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index efaaef2b7ae1..800ea2a778cc 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "mmu.h" #include "x86.h" @@ -52,11 +53,21 @@ module_param_named(sev, sev_enabled, bool, 0444); /* enable/disable SEV-ES support */ static bool sev_es_enabled = true; module_param_named(sev_es, sev_es_enabled, bool, 0444); + +/* enable/disable SEV-ES DebugSwap support */ +static bool sev_es_debug_swap_enabled = true; +module_param_named(debug_swap, sev_es_debug_swap_enabled, bool, 0644); #else #define sev_enabled false #define sev_es_enabled false +#define sev_es_debug_swap false #endif /* CONFIG_KVM_AMD_SEV */ +bool sev_es_is_debug_swap_enabled(void) +{ + return sev_es_debug_swap_enabled; +} + static u8 sev_enc_bit; static DECLARE_RWSEM(sev_deactivate_lock); static DEFINE_MUTEX(sev_bitmap_lock); @@ -604,6 +615,9 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) save->xss = svm->vcpu.arch.ia32_xss; save->dr6 = svm->vcpu.arch.dr6; + if (sev_es_is_debug_swap_enabled()) + save->sev_features |= SVM_SEV_FEAT_DEBUG_SWAP; + pr_debug("Virtual Machine Save Area (VMSA):\n"); print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1, save, sizeof(*save), false); @@ -2249,6 +2263,9 @@ void __init sev_hardware_setup(void) out: sev_enabled = sev_supported; sev_es_enabled = sev_es_supported; + if (sev_es_debug_swap_enabled) + sev_es_debug_swap_enabled = sev_es_enabled && + boot_cpu_has(X86_FEATURE_NO_NESTED_DATA_BP); #endif } @@ -3027,6 +3044,18 @@ void sev_es_prepare_switch_to_guest(struct sev_es_save_area *hostsa) /* MSR_IA32_XSS is restored on VMEXIT, save the currnet host value */ hostsa->xss = host_xss; + + /* The DebugSwap SEV feature does Type B swaps of DR[0-3] */ + if (sev_es_is_debug_swap_enabled()) { + hostsa->dr0 = native_get_debugreg(0); + hostsa->dr1 = native_get_debugreg(1); + hostsa->dr2 = native_get_debugreg(2); + hostsa->dr3 = native_get_debugreg(3); + hostsa->dr0_addr_mask = amd_get_dr_addr_mask(0); + hostsa->dr1_addr_mask = amd_get_dr_addr_mask(1); + hostsa->dr2_addr_mask = amd_get_dr_addr_mask(2); + hostsa->dr3_addr_mask = amd_get_dr_addr_mask(3); + } } void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index ce362e88a567..697804d46545 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1189,7 +1189,8 @@ static void init_vmcb(struct kvm_vcpu *vcpu) set_exception_intercept(svm, UD_VECTOR); set_exception_intercept(svm, MC_VECTOR); set_exception_intercept(svm, AC_VECTOR); - set_exception_intercept(svm, DB_VECTOR); + if (!sev_es_is_debug_swap_enabled()) + set_exception_intercept(svm, DB_VECTOR); /* * Guest access to VMware backdoor ports could legitimately * trigger #GP because of TSS I/O permission bitmap. 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Donenfeld" , "H. Peter Anvin" , Alexey Kardashevskiy Subject: [PATCH kernel v2 3/3] x86/sev: Do not handle #VC for DR7 read/write Date: Fri, 9 Dec 2022 15:38:04 +1100 Message-ID: <20221209043804.942352-4-aik@amd.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209043804.942352-1-aik@amd.com> References: <20221209043804.942352-1-aik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT046:EE_|SA1PR12MB5614:EE_ X-MS-Office365-Filtering-Correlation-Id: 053b0ce6-40e1-4184-ff14-08dad99f796f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CiYYGB2mnN4NrnYa9ipzSwt799X2Geo0ftBZRfnBWH5BSoViPCOLEQJK1nHK2fzdWtZO0KHUckn9mVWjal5ixPsHuZEkAYdmpj8dZ+kdgZcSq4/KGoShz9g12YORbTFB75vB+/RHkOyd8x2hbGD5pseXoB4LQ54JfDfvt+mkb4Y9z3g/oAMUpjwxYzOOOmr7RVtS2LGs4GFNycpspxMpiIvNT5JQ/TsNF3Za0wPkvP6fOnvQMH7upcCYV+uqjHOFJaXujN+rtmRGY7UPdHJXAUB1gTg2GXb8/WxX6ty47Hd7wmpVzupj+4+GRnZ5id5wkLYhpNxwhyYdM+f580q3LnR7K1e2mjT19fHX0Vvi45RDkqLx7Aed/nq4hn9oxH7HA4lg4PkxdGHJYm4dQb02e6y/33l0Kv6Md+u7OUE6uSh5V1p5PUSOSnihsy0b/Ral9h9PT6UeI6IM0AgVKzDlRZLqPf6QkF0ttxy88I66FTJKSUrTSQPHlc6KjSeKULdBSW/wOJ0T1epP10xsqF3lSdRyifz513USC+dnxI5Yc1S5wBTPxchphRudezuPRR9Q8x3ZShBG6te6FPTLbi7boSiuc8WmRUDpKpVqeKr0BGZC0h46CUH/m2DJxCm/i9MA4prBjEDM6yCFHKuUDaClQuzwE7BTR2ZpgjJWd/1xgVttdvETDNOVzNNcjikiWHNIIt5tx3QSCVxINorVbB29tsjtk7uvVdwdvSfksDxq0WI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(346002)(39860400002)(376002)(451199015)(40470700004)(36840700001)(46966006)(6916009)(426003)(81166007)(54906003)(356005)(316002)(4326008)(336012)(40480700001)(47076005)(36860700001)(26005)(2616005)(16526019)(1076003)(70586007)(6666004)(70206006)(186003)(36756003)(478600001)(82310400005)(8676002)(82740400003)(41300700001)(7416002)(5660300002)(8936002)(40460700003)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2022 04:40:04.5048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 053b0ce6-40e1-4184-ff14-08dad99f796f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5614 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org With MSR_AMD64_SEV_DEBUG_SWAP enabled, the VM should not get #VC events for DR7 read/write which it rather avoided. Signed-off-by: Alexey Kardashevskiy Reviewed-by: Borislav Petkov (AMD) --- Changes: v2: * use new bit definition --- arch/x86/include/asm/msr-index.h | 1 + tools/arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/sev.c | 6 ++++++ 3 files changed, 8 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 4a2af82553e4..979ea2dd3845 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -570,6 +570,7 @@ #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) +#define MSR_AMD64_SEV_DEBUG_SWAP BIT_ULL(7) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index f17ade084720..2264ada2e26a 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -570,6 +570,7 @@ #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) +#define MSR_AMD64_SEV_DEBUG_SWAP BIT_ULL(7) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index a428c62330d3..6141c789e3d5 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1618,6 +1618,9 @@ static enum es_result vc_handle_dr7_write(struct ghcb *ghcb, long val, *reg = vc_insn_get_rm(ctxt); enum es_result ret; + if (sev_status & MSR_AMD64_SEV_DEBUG_SWAP) + return ES_VMM_ERROR; + if (!reg) return ES_DECODE_FAILED; @@ -1655,6 +1658,9 @@ static enum es_result vc_handle_dr7_read(struct ghcb *ghcb, struct sev_es_runtime_data *data = this_cpu_read(runtime_data); long *reg = vc_insn_get_rm(ctxt); + if (sev_status & MSR_AMD64_SEV_DEBUG_SWAP) + return ES_VMM_ERROR; + if (!reg) return ES_DECODE_FAILED;