From patchwork Mon Dec 12 09:55:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13070877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8194BC4167B for ; Mon, 12 Dec 2022 09:55:38 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.459252.716950 (Exim 4.92) (envelope-from ) id 1p4fWz-000379-Qh; Mon, 12 Dec 2022 09:55:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 459252.716950; Mon, 12 Dec 2022 09:55:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fWz-000370-NF; Mon, 12 Dec 2022 09:55:29 +0000 Received: by outflank-mailman (input) for mailman id 459252; Mon, 12 Dec 2022 09:55:28 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fWy-0002xh-0Q for xen-devel@lists.xenproject.org; Mon, 12 Dec 2022 09:55:28 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fWx-0001RX-Lm; Mon, 12 Dec 2022 09:55:27 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1p4fWx-0001lz-E0; Mon, 12 Dec 2022 09:55:27 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=YFTBJwfi1CbdqGKnDGX2TBZap1NQAnxcoQHLLfHNozs=; b=UnD/+x170OXbFPzYK2SWr8FZkD PJkx4RTyNWoBbbNcxM3xUu7zt4m/lqnFoYPtGHc9DJ4Es2LjU42H88I3umf1hEcJbJ2lGTvzI54oA ymsoiSHwHcFOUfBWEBn6/JKe7vRXuizlisYy0uj8giU7Y4Rmr2eZMwFIPh6NLkDl7B8U=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: michal.orzel@amd.com, Luca.Fancellu@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v3 01/18] xen/arm64: flushtlb: Reduce scope of barrier for local TLB flush Date: Mon, 12 Dec 2022 09:55:06 +0000 Message-Id: <20221212095523.52683-2-julien@xen.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212095523.52683-1-julien@xen.org> References: <20221212095523.52683-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall Per D5-4929 in ARM DDI 0487H.a: "A DSB NSH is sufficient to ensure completion of TLB maintenance instructions that apply to a single PE. A DSB ISH is sufficient to ensure completion of TLB maintenance instructions that apply to PEs in the same Inner Shareable domain. " This means barrier after local TLB flushes could be reduced to non-shareable. Note that the scope of the barrier in the workaround has not been changed because Linux v6.1-rc8 is also using 'ish' and I couldn't find anything in the Neoverse N1 suggesting that a 'nsh' would be sufficient. Signed-off-by: Julien Grall Reviewed-by: Michal Orzel Reviewed-by: Ayan Kumar Halder --- I have used an older version of the Arm Arm because the explanation in the latest (ARM DDI 0487I.a) is less obvious. I reckon the paragraph about DSB in D8.13.8 is missing the shareability. But this is implied in B2.3.11: "If the required access types of the DSB is reads and writes, the following instructions issued by PEe before the DSB are complete for the required shareability domain: [...] — All TLB maintenance instructions. " Changes in v3: - Patch added --- xen/arch/arm/include/asm/arm64/flushtlb.h | 27 ++++++++++++++--------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/include/asm/arm64/flushtlb.h b/xen/arch/arm/include/asm/arm64/flushtlb.h index 7c5431518741..39d429ace552 100644 --- a/xen/arch/arm/include/asm/arm64/flushtlb.h +++ b/xen/arch/arm/include/asm/arm64/flushtlb.h @@ -12,8 +12,9 @@ * ARM64_WORKAROUND_REPEAT_TLBI: * Modification of the translation table for a virtual address might lead to * read-after-read ordering violation. - * The workaround repeats TLBI+DSB operation for all the TLB flush operations. - * While this is stricly not necessary, we don't want to take any risk. + * The workaround repeats TLBI+DSB ISH operation for all the TLB flush + * operations. While this is stricly not necessary, we don't want to + * take any risk. * * For Xen page-tables the ISB will discard any instructions fetched * from the old mappings. @@ -21,38 +22,42 @@ * For the Stage-2 page-tables the ISB ensures the completion of the DSB * (and therefore the TLB invalidation) before continuing. So we know * the TLBs cannot contain an entry for a mapping we may have removed. + * + * Note that for local TLB flush, using non-shareable (nsh) is sufficient + * (see D5-4929 in ARM DDI 0487H.a). Althougth, the memory barrier in + * for the workaround is left as inner-shareable to match with Linux. */ -#define TLB_HELPER(name, tlbop) \ +#define TLB_HELPER(name, tlbop, sh) \ static inline void name(void) \ { \ asm volatile( \ - "dsb ishst;" \ + "dsb " # sh "st;" \ "tlbi " # tlbop ";" \ ALTERNATIVE( \ "nop; nop;", \ - "dsb ish;" \ + "dsb " # sh ";" \ "tlbi " # tlbop ";", \ ARM64_WORKAROUND_REPEAT_TLBI, \ CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ - "dsb ish;" \ + "dsb " # sh ";" \ "isb;" \ : : : "memory"); \ } /* Flush local TLBs, current VMID only. */ -TLB_HELPER(flush_guest_tlb_local, vmalls12e1); +TLB_HELPER(flush_guest_tlb_local, vmalls12e1, nsh); /* Flush innershareable TLBs, current VMID only */ -TLB_HELPER(flush_guest_tlb, vmalls12e1is); +TLB_HELPER(flush_guest_tlb, vmalls12e1is, ish); /* Flush local TLBs, all VMIDs, non-hypervisor mode */ -TLB_HELPER(flush_all_guests_tlb_local, alle1); +TLB_HELPER(flush_all_guests_tlb_local, alle1, nsh); /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ -TLB_HELPER(flush_all_guests_tlb, alle1is); +TLB_HELPER(flush_all_guests_tlb, alle1is, ish); /* Flush all hypervisor mappings from the TLB of the local processor. */ -TLB_HELPER(flush_xen_tlb_local, alle2); +TLB_HELPER(flush_xen_tlb_local, alle2, nsh); /* Flush TLB of local processor for address va. */ static inline void __flush_xen_tlb_one_local(vaddr_t va) From patchwork Mon Dec 12 09:55:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13070880 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8A17C4332F for ; Mon, 12 Dec 2022 09:55:39 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.459255.716961 (Exim 4.92) (envelope-from ) id 1p4fX1-0003O0-3B; Mon, 12 Dec 2022 09:55:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 459255.716961; Mon, 12 Dec 2022 09:55:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX0-0003Nt-Vk; Mon, 12 Dec 2022 09:55:30 +0000 Received: by outflank-mailman (input) for mailman id 459255; Mon, 12 Dec 2022 09:55:29 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fWz-00036f-8A for xen-devel@lists.xenproject.org; Mon, 12 Dec 2022 09:55:29 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fWy-0001Rj-S0; Mon, 12 Dec 2022 09:55:28 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1p4fWy-0001lz-Jn; Mon, 12 Dec 2022 09:55:28 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=9FlTAYz8wbZf3SBofaH+7s9IZ0eMB5jewpGKvz0pYMo=; b=qMt4WMfMTDElJq+s+WDQRMgPTC IcyZgM7qGuaAA1RiHJ1/I1SIXYYKZ9xMFWB3H1uDdaV21Mjq82GH5cMCGNntWIVv8fXhDZTpKFssC IjK6HsEzWD0+VrTo3rdD3o59C1k3Sl+iYWXfLtQ0lyDpHuNbBErrtG/Svo8wDrChwwAs=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: michal.orzel@amd.com, Luca.Fancellu@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v3 02/18] xen/arm64: flushtlb: Implement the TLBI repeat workaround for TLB flush by VA Date: Mon, 12 Dec 2022 09:55:07 +0000 Message-Id: <20221212095523.52683-3-julien@xen.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212095523.52683-1-julien@xen.org> References: <20221212095523.52683-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall Looking at the Neoverse N1 errata document, it is not clear to me why the TLBI repeat workaround is not applied for TLB flush by VA. The TBL flush by VA helpers are used in flush_xen_tlb_range_va_local() and flush_xen_tlb_range_va(). So if the range size if a fixed size smaller than a PAGE_SIZE, it would be possible that the compiler remove the loop and therefore replicate the sequence described in the erratum 1286807. So the TLBI repeat workaround should also be applied for the TLB flush by VA helpers. Fixes: 22e323d115d8 ("xen/arm: Add workaround for Cortex-A76/Neoverse-N1 erratum #1286807") Signed-off-by: Julien Grall Reviewed-by: Michal Orzel --- This was spotted while looking at reducing the scope of the memory barriers. I don't have any HW affected. Changes in v3: - Patch added --- xen/arch/arm/include/asm/arm64/flushtlb.h | 31 +++++++++++++++++------ 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/include/asm/arm64/flushtlb.h b/xen/arch/arm/include/asm/arm64/flushtlb.h index 39d429ace552..5b033c0cb980 100644 --- a/xen/arch/arm/include/asm/arm64/flushtlb.h +++ b/xen/arch/arm/include/asm/arm64/flushtlb.h @@ -44,6 +44,27 @@ static inline void name(void) \ : : : "memory"); \ } +/* + * FLush TLB by VA. This will likely be used in a loop, so the caller + * is responsible to use the appropriate memory barriers before/after + * the sequence. + * + * See above about the ARM64_WORKAROUND_REPEAT_TLBI sequence. + */ +#define TLB_HELPER_VA(name, tlbop) \ +static inline void name(vaddr_t va) \ +{ \ + asm volatile( \ + "tlbi " # tlbop ", %0;" \ + ALTERNATIVE( \ + "nop; nop;", \ + "dsb ish;" \ + "tlbi " # tlbop ", %0;", \ + ARM64_WORKAROUND_REPEAT_TLBI, \ + CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \ + : : "r" (va >> PAGE_SHIFT) : "memory"); \ +} + /* Flush local TLBs, current VMID only. */ TLB_HELPER(flush_guest_tlb_local, vmalls12e1, nsh); @@ -60,16 +81,10 @@ TLB_HELPER(flush_all_guests_tlb, alle1is, ish); TLB_HELPER(flush_xen_tlb_local, alle2, nsh); /* Flush TLB of local processor for address va. */ -static inline void __flush_xen_tlb_one_local(vaddr_t va) -{ - asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); -} +TLB_HELPER_VA(__flush_xen_tlb_one_local, vae2); /* Flush TLB of all processors in the inner-shareable domain for address va. */ -static inline void __flush_xen_tlb_one(vaddr_t va) -{ - asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); -} +TLB_HELPER_VA(__flush_xen_tlb_one, vae2is); #endif /* __ASM_ARM_ARM64_FLUSHTLB_H__ */ /* From patchwork Mon Dec 12 09:55:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13070878 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AACADC04FDE for ; Mon, 12 Dec 2022 09:55:39 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.459256.716966 (Exim 4.92) (envelope-from ) id 1p4fX1-0003RO-Gu; Mon, 12 Dec 2022 09:55:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 459256.716966; Mon, 12 Dec 2022 09:55:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX1-0003QV-AC; Mon, 12 Dec 2022 09:55:31 +0000 Received: by outflank-mailman (input) for mailman id 459256; Mon, 12 Dec 2022 09:55:30 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX0-0003G8-8Y for xen-devel@lists.xenproject.org; Mon, 12 Dec 2022 09:55:30 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX0-0001Rt-0o; Mon, 12 Dec 2022 09:55:30 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1p4fWz-0001lz-Pc; Mon, 12 Dec 2022 09:55:29 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=y+bWQ6fBAEgHiQywHHpvY3Ua8lvVwtQRx0GvNG0n9MA=; b=FmvNdrvi4r5Vp0Bxa+9lQ6LCmv l+BNZm0jm3wS+MmgmD29HOlHt3TALC1PgPZmpeUt/TqoJHcFlZ5X5BgX/L+um5yBb2njGjf8zEG5V 9iq+OhMZlxrMPeR+g8aDV828++OuSlfmnHWbjdF4eHH3NO03XCBl3nf+nKshUgJaj3XE=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: michal.orzel@amd.com, Luca.Fancellu@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v3 03/18] xen/arm32: flushtlb: Reduce scope of barrier for local TLB flush Date: Mon, 12 Dec 2022 09:55:08 +0000 Message-Id: <20221212095523.52683-4-julien@xen.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212095523.52683-1-julien@xen.org> References: <20221212095523.52683-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall Per G5-9224 in ARM DDI 0487I.a: "A DSB NSH is sufficient to ensure completion of TLB maintenance instructions that apply to a single PE. A DSB ISH is sufficient to ensure completion of TLB maintenance instructions that apply to PEs in the same Inner Shareable domain. " This is quoting the Armv8 specification because I couldn't find an explicit statement in the Armv7 specification. Instead, I could find bits in various places that confirm the same implementation. Furthermore, Linux has been using 'nsh' since 2013 (62cbbc42e001 "ARM: tlb: reduce scope of barrier domains for TLB invalidation"). This means barrier after local TLB flushes could be reduced to non-shareable. Signed-off-by: Julien Grall Reviewed-by: Michal Orzel --- Changes in v3: - Patch added --- xen/arch/arm/include/asm/arm32/flushtlb.h | 27 +++++++++++++---------- 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/flushtlb.h b/xen/arch/arm/include/asm/arm32/flushtlb.h index 9085e6501153..7ae6a12f8155 100644 --- a/xen/arch/arm/include/asm/arm32/flushtlb.h +++ b/xen/arch/arm/include/asm/arm32/flushtlb.h @@ -15,30 +15,33 @@ * For the Stage-2 page-tables the ISB ensures the completion of the DSB * (and therefore the TLB invalidation) before continuing. So we know * the TLBs cannot contain an entry for a mapping we may have removed. + * + * Note that for local TLB flush, using non-shareable (nsh) is sufficient + * (see G5-9224 in ARM DDI 0487I.a). */ -#define TLB_HELPER(name, tlbop) \ -static inline void name(void) \ -{ \ - dsb(ishst); \ - WRITE_CP32(0, tlbop); \ - dsb(ish); \ - isb(); \ +#define TLB_HELPER(name, tlbop, sh) \ +static inline void name(void) \ +{ \ + dsb(sh ## st); \ + WRITE_CP32(0, tlbop); \ + dsb(sh); \ + isb(); \ } /* Flush local TLBs, current VMID only */ -TLB_HELPER(flush_guest_tlb_local, TLBIALL); +TLB_HELPER(flush_guest_tlb_local, TLBIALL, nsh); /* Flush inner shareable TLBs, current VMID only */ -TLB_HELPER(flush_guest_tlb, TLBIALLIS); +TLB_HELPER(flush_guest_tlb, TLBIALLIS, ish); /* Flush local TLBs, all VMIDs, non-hypervisor mode */ -TLB_HELPER(flush_all_guests_tlb_local, TLBIALLNSNH); +TLB_HELPER(flush_all_guests_tlb_local, TLBIALLNSNH, nsh); /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ -TLB_HELPER(flush_all_guests_tlb, TLBIALLNSNHIS); +TLB_HELPER(flush_all_guests_tlb, TLBIALLNSNHIS, ish); /* Flush all hypervisor mappings from the TLB of the local processor. */ -TLB_HELPER(flush_xen_tlb_local, TLBIALLH); +TLB_HELPER(flush_xen_tlb_local, TLBIALLH, nsh); /* Flush TLB of local processor for address va. */ static inline void __flush_xen_tlb_one_local(vaddr_t va) From patchwork Mon Dec 12 09:55:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13070879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83A45C10F1E for ; Mon, 12 Dec 2022 09:55:40 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.459257.716980 (Exim 4.92) (envelope-from ) id 1p4fX2-0003vF-Tp; Mon, 12 Dec 2022 09:55:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 459257.716980; Mon, 12 Dec 2022 09:55:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX2-0003tp-Pn; Mon, 12 Dec 2022 09:55:32 +0000 Received: by outflank-mailman (input) for mailman id 459257; Mon, 12 Dec 2022 09:55:31 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX1-0003Vv-Lg for xen-devel@lists.xenproject.org; Mon, 12 Dec 2022 09:55:31 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX1-0001SF-6Z; Mon, 12 Dec 2022 09:55:31 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1p4fX0-0001lz-VP; Mon, 12 Dec 2022 09:55:31 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=sZJaNA72ZYypcX3vxZECdiF0fWUmdItqPCX8UGPLYBg=; b=lspWQG0cuIlO2qblyXvNtR/O6t njSE9CXBpnzOlJncAoErtmAk+zUIbfdCsKZpB3Fp9aziIpmpmtHb8gvwaW3pHRSCAfVrscTWEMmDK SrVtaApkPyLjbWmL/Wkui2o7MD1B6TgOnUrUkMxyFTzI2YGFtr2zcWQEzOyToKbPl7hI=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: michal.orzel@amd.com, Luca.Fancellu@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v3 04/18] xen/arm: flushtlb: Reduce scope of barrier for the TLB range flush Date: Mon, 12 Dec 2022 09:55:09 +0000 Message-Id: <20221212095523.52683-5-julien@xen.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212095523.52683-1-julien@xen.org> References: <20221212095523.52683-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall At the moment, flush_xen_tlb_range_va{,_local}() are using system wide memory barrier. This is quite expensive and unnecessary. For the local version, a non-shareable barrier is sufficient. For the SMP version, a inner-shareable barrier is sufficient. Furthermore, the initial barrier only need to a store barrier. For the full explanation of the sequence see asm/arm{32,64}/flushtlb.h. Signed-off-by: Julien Grall Reviewed-by: Michal Orzel --- Changes in v3: - Patch added --- xen/arch/arm/include/asm/flushtlb.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/include/asm/flushtlb.h b/xen/arch/arm/include/asm/flushtlb.h index 125a141975e0..e45fb6d97b02 100644 --- a/xen/arch/arm/include/asm/flushtlb.h +++ b/xen/arch/arm/include/asm/flushtlb.h @@ -37,13 +37,14 @@ static inline void flush_xen_tlb_range_va_local(vaddr_t va, { vaddr_t end = va + size; - dsb(sy); /* Ensure preceding are visible */ + /* See asm/arm{32,64}/flushtlb.h for the explanation of the sequence. */ + dsb(nshst); /* Ensure prior page-tables updates have completed */ while ( va < end ) { __flush_xen_tlb_one_local(va); va += PAGE_SIZE; } - dsb(sy); /* Ensure completion of the TLB flush */ + dsb(nsh); /* Ensure the TLB invalidation has completed */ isb(); } @@ -56,13 +57,14 @@ static inline void flush_xen_tlb_range_va(vaddr_t va, { vaddr_t end = va + size; - dsb(sy); /* Ensure preceding are visible */ + /* See asm/arm{32,64}/flushtlb.h for the explanation of the sequence. */ + dsb(ishst); /* Ensure prior page-tables updates have completed */ while ( va < end ) { __flush_xen_tlb_one(va); va += PAGE_SIZE; } - dsb(sy); /* Ensure completion of the TLB flush */ + dsb(ish); /* Ensure the TLB invalidation has completed */ isb(); } From patchwork Mon Dec 12 09:55:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13070882 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E8E8C4332F for ; Mon, 12 Dec 2022 09:55:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.459258.716993 (Exim 4.92) (envelope-from ) id 1p4fX4-0004G3-D7; Mon, 12 Dec 2022 09:55:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 459258.716993; Mon, 12 Dec 2022 09:55:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX4-0004Em-8Y; Mon, 12 Dec 2022 09:55:34 +0000 Received: by outflank-mailman (input) for mailman id 459258; Mon, 12 Dec 2022 09:55:32 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX2-0003pM-IE for xen-devel@lists.xenproject.org; Mon, 12 Dec 2022 09:55:32 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX2-0001SX-CK; Mon, 12 Dec 2022 09:55:32 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1p4fX2-0001lz-4x; Mon, 12 Dec 2022 09:55:32 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=4gf7OGmCVTPIad+5gHH9EbUJ/Y2Mpf2evxa74D/Bu6g=; b=vKmbKzPt6HLBrhHXL56pzDRdO7 02rW7Wm0ZQxyS+V8WoSvH8sylIwt/iUR2xk3jH731iLkNrjEORwfLQbKKGb52Fp0CmA1oLQd+fuo2 lyrIXPq8h7pTuB25cDL9UZJqcKZFYmCxr3N4a3K34tr1Q800MK85iP6v1EE2PnkRHfyI=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: michal.orzel@amd.com, Luca.Fancellu@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v3 05/18] xen/arm: Clean-up the memory layout Date: Mon, 12 Dec 2022 09:55:10 +0000 Message-Id: <20221212095523.52683-6-julien@xen.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212095523.52683-1-julien@xen.org> References: <20221212095523.52683-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall In a follow-up patch, the base address for the common mappings will vary between arm32 and arm64. To avoid any duplication, define every mapping in the common region from the previous one. Take the opportunity to: * add missing *_SIZE for FIXMAP_VIRT_* and XEN_VIRT_* * switch to MB()/GB() to be avoid hexadecimal (easier to read) Signed-off-by: Julien Grall Reviewed-by: Michal Orzel --- Changes in v3: - Switch more macros to use MB()/GB() - Remove duplicated sentence in the commit message Changes in v2: - Use _AT(vaddr_t, ...) to build on 32-bit. - Drop COMMON_VIRT_START --- xen/arch/arm/include/asm/config.h | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/include/asm/config.h b/xen/arch/arm/include/asm/config.h index 0fefed1b8aa9..87851e677701 100644 --- a/xen/arch/arm/include/asm/config.h +++ b/xen/arch/arm/include/asm/config.h @@ -107,14 +107,19 @@ * Unused */ -#define XEN_VIRT_START _AT(vaddr_t,0x00200000) -#define FIXMAP_ADDR(n) (_AT(vaddr_t,0x00400000) + (n) * PAGE_SIZE) +#define XEN_VIRT_START _AT(vaddr_t, MB(2)) +#define XEN_VIRT_SIZE _AT(vaddr_t, MB(2)) -#define BOOT_FDT_VIRT_START _AT(vaddr_t,0x00600000) -#define BOOT_FDT_VIRT_SIZE _AT(vaddr_t, MB(4)) +#define FIXMAP_VIRT_START (XEN_VIRT_START + XEN_VIRT_SIZE) +#define FIXMAP_VIRT_SIZE _AT(vaddr_t, MB(2)) + +#define FIXMAP_ADDR(n) (FIXMAP_VIRT_START + (n) * PAGE_SIZE) + +#define BOOT_FDT_VIRT_START (FIXMAP_VIRT_START + FIXMAP_VIRT_SIZE) +#define BOOT_FDT_VIRT_SIZE _AT(vaddr_t, MB(4)) #ifdef CONFIG_LIVEPATCH -#define LIVEPATCH_VMAP_START _AT(vaddr_t,0x00a00000) +#define LIVEPATCH_VMAP_START (BOOT_FDT_VIRT_START + BOOT_FDT_VIRT_SIZE) #define LIVEPATCH_VMAP_SIZE _AT(vaddr_t, MB(2)) #endif @@ -124,18 +129,18 @@ #define CONFIG_SEPARATE_XENHEAP 1 -#define FRAMETABLE_VIRT_START _AT(vaddr_t,0x02000000) +#define FRAMETABLE_VIRT_START _AT(vaddr_t, MB(32)) #define FRAMETABLE_SIZE MB(128-32) #define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) #define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + FRAMETABLE_SIZE - 1) -#define VMAP_VIRT_START _AT(vaddr_t,0x10000000) +#define VMAP_VIRT_START _AT(vaddr_t, MB(256)) #define VMAP_VIRT_SIZE _AT(vaddr_t, GB(1) - MB(256)) -#define XENHEAP_VIRT_START _AT(vaddr_t,0x40000000) +#define XENHEAP_VIRT_START _AT(vaddr_t, GB(1)) #define XENHEAP_VIRT_SIZE _AT(vaddr_t, GB(1)) -#define DOMHEAP_VIRT_START _AT(vaddr_t,0x80000000) +#define DOMHEAP_VIRT_START _AT(vaddr_t, GB(2)) #define DOMHEAP_VIRT_SIZE _AT(vaddr_t, GB(2)) #define DOMHEAP_ENTRIES 1024 /* 1024 2MB mapping slots */ From patchwork Mon Dec 12 09:55:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13070881 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5DFB1C4167B for ; Mon, 12 Dec 2022 09:55:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.459261.716999 (Exim 4.92) (envelope-from ) id 1p4fX5-0004OF-1K; Mon, 12 Dec 2022 09:55:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 459261.716999; Mon, 12 Dec 2022 09:55:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX4-0004ND-QV; Mon, 12 Dec 2022 09:55:34 +0000 Received: by outflank-mailman (input) for mailman id 459261; Mon, 12 Dec 2022 09:55:33 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX3-0004Ae-R9 for xen-devel@lists.xenproject.org; Mon, 12 Dec 2022 09:55:33 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1p4fX3-0001Ss-ID; Mon, 12 Dec 2022 09:55:33 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1p4fX3-0001lz-Am; Mon, 12 Dec 2022 09:55:33 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=8XTTu/Hz4Y+O0ljKPi9Gp8h5CZ8CZj743R2YHfvL9wM=; b=U367eq51tXzXTpAIBNPLuA4+7/ u9Z/Cp11p4d6pLtN1uA3J5bOk7fj/l+/xsp1tYVcYmESN7dG9A03uM//V7tQvgReTZTD8oHh3AHIL /6HhxU3CIObSbHlxTBw2PAnoF/8LWo//cGHy+vcvZj3dq1DELbq1OqPEFOwMKhpYKbvA=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: michal.orzel@amd.com, Luca.Fancellu@arm.com, Julien Grall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v3 06/18] xen/arm32: head: Replace "ldr rX, =