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Unfortunately, it looks like the SMMU integration in the NXP LS1028A has wrongly tied the cfg_cttw signal to 0, even though the SoC documentation specifies that "The SMMU supports cache coherency for page table walks and DVM transactions for page table cache maintenance operations." Device tree provides the option of overriding the ID register via the dma-coherent property since commit bae2c2d421cd ("iommu/arm-smmu: Sort out coherency"), and that's what we do here. Telling struct io_pgtable_cfg that the SMMU page table walks are coherent with the CPU caches brings performance benefits, because it avoids certain operations such as __arm_lpae_sync_pte() for PTE updates. Link: https://lore.kernel.org/linux-iommu/3f3112e4-65ff-105d-8cd7-60495ec9054a@arm.com/ Suggested-by: Robin Murphy Signed-off-by: Vladimir Oltean --- v1->v2: reword commit message, drop Fixes: tag vfio's problem with arm_smmu_capable(IOMMU_CAP_CACHE_COHERENCY) should be resolved independently, I'm not claiming that this is the only fix for that. v1 at: https://lore.kernel.org/linux-iommu/20221208151514.3840720-1-vladimir.oltean@nxp.com/ arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index ac1c3a7e5f7a..9be0b4b7babf 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -712,6 +712,7 @@ smmu: iommu@5000000 { reg = <0 0x5000000 0 0x800000>; #global-interrupts = <8>; #iommu-cells = <1>; + dma-coherent; stream-match-mask = <0x7c00>; /* global secure fault */ interrupts = , From patchwork Thu Dec 15 13:56:36 2022 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GWXNjzQBr6S+UQHQ6xlvmmFWq/uIfY+Nv4lQbICHkgQvwlLLSSWKtpd9oFg+Pb/OvMfSuB/n7OkP6Bec65VTR3iD6co26yD/q0kp5+2WNKaZrhGw/Q9sN/sZcfBktfPNAhX6BQoeW3Gw7AuupDTlD7ckpH1PgpXV7rG+trSYWwe5E0hCrfTIpZouko7UZsAyFmf0+22QGDgcSJjUZFTqS63hAPZq1J3fIW/rWp3eCQ/MinAr/olY2S+xKIeaQg5Oxml+/GaVb3qsS4vbwzogbd/6jgNcMNX/QHJwMVITNNmfJqWdv81xK2fYeSmFyKQA8DKBY7YsAECzDmMM03nCKOdezwmovlMvTz9e6Jhs2FRwUyPK978iZOIW+mPV439Gu1/c3GLicV4IiK0+Qtb2UEDiw6Vis51w9a8Fliquw99RPWQLqm8ThXw8IXB2+2j+c0Rkpwvy7dL0ChfszGnQ+7IcI1w0keydSz8+5uPcX7Z5d6B43c18IZ4gxbEPzNznwC+v93JRNWrBtY7fV/uJmZ36Yzg1G5fGUD4UMUQEQnjNr8H0geaeFpHOnzBiYLmBVBmTs/YBaRQ7hHjj0fA1uWLNNYqNpUEiyRQ9HZbRKG5htDHba7/YuBbLPJhnteSWvQx6IOZt5CNhrvbSsctVPeAvwvC7laKgeHh4GCkGaPicfkxmlsUiOyR7peQpfOMXv3igNMKEcccFxOtD9V8XHr2Jse1V3vFdtGdU1OXaZ5KyvkKYkeCEb0fdZazQ14e2bss5RtHc86AXApbMZHi4KmAgI/6DQbIndiUJtjzJbRKiHKPjPHQ/LKBfC8/NLPY2HLaF9R1J7Uuo79cQyRnpcuvwP5Jnguu7DKv0sGUWJUw4MzW58CqE4o8eK8sWiLjyBEWtx0nK32eLSGJ2NP1E3Q9HTQCgJvu+ceGH8+lt+tJKkNhwu4DRhmRLWbw56s6r23JV+XRKYIEXwxgLkcTlWSPZevwcJiEQJE1jTwBGEH4txJQk9XVQPUbjjH+HpHmQUIP+4LkbNh9MLSrtDuje0r3tVlSm/8C8U96iPLC4suA4bGEnZzSltT6GiczIgDL+u3DnJUsHyYQWrp6aMhnJL8KRQhlCVqkcsYEqoQpOk71TWnkFM96D7GiEY4W9HDHsAHyL83iPzzt6WmWVHPWpEIZz0I80rDgzvgWsvutCG+3jwiStpXMR1bROcbWMILjW8bz+l1zrp8oFnpd58WyEoZpzkLnuJJqCP+7kaBRCRst/D8FC8mwjIABXCRuRKd7jB2/Tg9EugTKKhB3f2myI4b+kWtar7dXAw/DYo8mM4JIo8BvZUmlIG0XTKlE/WOhicInG1A7ZV6R1kYz+IFM4sSK51FEeawMFBYrSPo05mYiHc9nEPUkyzfpAEzYQa0iSVdP8Uqc/LNMoETO4xYRBTsGWSAgcVJEfPQPFnKoVze+OklwhePcvUfMnEgJlH4N5rB03rpzCCsDG+7NNz6yC5tD/cpRP+yyyQ4f8KoYSuUkrgPXbsJCu7Z9/gnmoy5ia+GKgtAlQIvgiuRHtnoAwQ/D+H+ftKLXi2ZplF5FnIvSIBHjvaC8zpdFpwxInFQWD8P8B2m4NBFdZYBq7Rmk6Gg== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f22907bc-d5a4-44c5-c9a8-08dadea43783 X-MS-Exchange-CrossTenant-AuthSource: AM0PR04MB5121.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2022 13:56:51.5764 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NW9bSFLSf31QtJhkzwb4kr7b2el8EmM4kbir8I93dbu7RjcdjV/RNQUp0P3oU8do0ffhPTMudfskIMd0IZ9v3A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB8463 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221215_055657_075524_3D7C2A65 X-CRM114-Status: GOOD ( 11.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SMMUv2 driver for MMU-500 reads the ARM_SMMU_GR0_ID0 register at probe time and tries to determine based on the CTTW (Coherent Translation Table Walk) bit whether this feature is supported. Unfortunately, it looks like the SMMU integration in the NXP LS1088A has wrongly tied the cfg_cttw signal to 0, even though the SoC documentation specifies that "The SMMU supports cache coherency for page table walks and DVM transactions for page table cache maintenance operations." Device tree provides the option of overriding the ID register via the dma-coherent property since commit bae2c2d421cd ("iommu/arm-smmu: Sort out coherency"), and that's what we do here. Telling struct io_pgtable_cfg that the SMMU page table walks are coherent with the CPU caches brings performance benefits, because it avoids certain operations such as __arm_lpae_sync_pte() for PTE updates. Link: https://lore.kernel.org/linux-iommu/3f3112e4-65ff-105d-8cd7-60495ec9054a@arm.com/ Suggested-by: Robin Murphy Signed-off-by: Vladimir Oltean --- v1->v2: patch is new arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 260d045dbd9a..e5fb137ac02b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -674,6 +674,7 @@ smmu: iommu@5000000 { reg = <0 0x5000000 0 0x800000>; #iommu-cells = <1>; stream-match-mask = <0x7C00>; + dma-coherent; #global-interrupts = <12>; // global secure fault interrupts = ,