From patchwork Mon Dec 19 15:46:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 13076716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F55EC4167B for ; Mon, 19 Dec 2022 15:39:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232126AbiLSPjN (ORCPT ); Mon, 19 Dec 2022 10:39:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232268AbiLSPjM (ORCPT ); Mon, 19 Dec 2022 10:39:12 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A35AA11178 for ; Mon, 19 Dec 2022 07:39:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671464351; x=1703000351; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+upwQwze58+VXG+39ATg90l00WT7gm0SqCvuLlxgE3E=; b=fugq2C28dNIt3SjEuyhkICIyDYAEie6iDVdPdtrgG8Fxct7fCUG2T83a EDPEzZrQzsAse1dqY1XdEnsibfd599foMqAEYS+hdg3pBcQ2mO9gyOhXn oTCZUBlUuYflJLGDkw+1CgSYy+VjZhMapMsqf9M4uMdpa8Zz/PQdUeSDe bPSNYPgc+4nd9XtW8TRZyKgiv4wBY7LwkxEcwhkvDqlHbUGh7Mmcm/ExT uNybNwgcA+UCJj+Xi6rTcERVZ2oEEJ60M53TcWNAtGDm9btJhxqPvJrFn QoJ5HPLWxrr2CWtM3air16vRoL21KZuO0jhQqt4aoygbkElFxq7dHeWhH A==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="307051207" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="307051207" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 07:39:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="774960313" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="774960313" Received: from power-sh.sh.intel.com ([10.239.183.7]) by orsmga004.jf.intel.com with ESMTP; 19 Dec 2022 07:39:09 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com, rui.zhang@intel.com Subject: [PATCH V2 1/6] thermal/intel: Introduce Intel TCC library Date: Mon, 19 Dec 2022 23:46:15 +0800 Message-Id: <20221219154620.3630-2-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219154620.3630-1-rui.zhang@intel.com> References: <20221219154620.3630-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There are several different drivers that accesses the Intel TCC (thermal control circuitry) MSRs, and each of them has its own implementation for the same functionalities, e.g. getting the current temperature, getting the tj_max, and getting/setting the tj_max offset. Introduce a library to unify the code for Intel CPU TCC MSR access. At the same time, ensure the temperature is got based on the updated tjmax value because tjmax can be changed at runtime for cases like the Intel SST-PP (Intel Speed Select Technology - Performance Profile) level change. Signed-off-by: Zhang Rui --- drivers/thermal/intel/Kconfig | 4 + drivers/thermal/intel/Makefile | 1 + drivers/thermal/intel/intel_tcc.c | 139 ++++++++++++++++++++++++++++++ include/linux/intel_tcc.h | 18 ++++ 4 files changed, 162 insertions(+) create mode 100644 drivers/thermal/intel/intel_tcc.c create mode 100644 include/linux/intel_tcc.h diff --git a/drivers/thermal/intel/Kconfig b/drivers/thermal/intel/Kconfig index f0c845679250..6b938c040d6e 100644 --- a/drivers/thermal/intel/Kconfig +++ b/drivers/thermal/intel/Kconfig @@ -12,6 +12,10 @@ config X86_THERMAL_VECTOR def_bool y depends on X86 && CPU_SUP_INTEL && X86_LOCAL_APIC +config INTEL_TCC + bool + depends on X86 + config X86_PKG_TEMP_THERMAL tristate "X86 package temperature thermal driver" depends on X86_THERMAL_VECTOR diff --git a/drivers/thermal/intel/Makefile b/drivers/thermal/intel/Makefile index 9a8d8054f316..5d8833c82ab6 100644 --- a/drivers/thermal/intel/Makefile +++ b/drivers/thermal/intel/Makefile @@ -2,6 +2,7 @@ # # Makefile for various Intel thermal drivers. +obj-$(CONFIG_INTEL_TCC) += intel_tcc.o obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o obj-$(CONFIG_INTEL_SOC_DTS_IOSF_CORE) += intel_soc_dts_iosf.o diff --git a/drivers/thermal/intel/intel_tcc.c b/drivers/thermal/intel/intel_tcc.c new file mode 100644 index 000000000000..2e5c741c41ca --- /dev/null +++ b/drivers/thermal/intel/intel_tcc.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * intel_tcc.c - Library for Intel TCC (thermal control circuitry) MSR access + * Copyright (c) 2022, Intel Corporation. + */ + +#include +#include +#include + +/** + * intel_tcc_get_tjmax() - returns the default TCC activation Temperature + * @cpu: cpu that the MSR should be run on, nagative value means any cpu. + * + * Get the TjMax value, which is the default thermal throttling or TCC + * activation temperature in degrees C. + * + * Return: Tjmax value in degrees C on success, negative error code otherwise. + */ +int intel_tcc_get_tjmax(int cpu) +{ + u32 low, high; + int val, err; + + if (cpu < 0) + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + else + err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + if (err) + return err; + + val = (low >> 16) & 0xff; + + return val ? val : -ENODATA; +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_get_tjmax, INTEL_TCC); + +/** + * intel_tcc_get_offset() - returns the TCC Offset value to Tjmax + * @cpu: cpu that the MSR should be run on, nagative value means any cpu. + * + * Get the TCC offset value to Tjmax. The effective thermal throttling or TCC + * activation temperature equals "Tjmax" - "TCC Offset", in degrees C. + * + * Return: Tcc offset value in degrees C on success, negative error code otherwise. + */ +int intel_tcc_get_offset(int cpu) +{ + u32 low, high; + int err; + + if (cpu < 0) + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + else + err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + if (err) + return err; + + return (low >> 24) & 0x3f; +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_get_offset, INTEL_TCC); + +/** + * intel_tcc_set_offset() - set the TCC offset value to Tjmax + * @cpu: cpu that the MSR should be run on, nagative value means any cpu. + * @offset: TCC offset value in degree C + * + * Set the TCC Offset value to Tjmax. The effective thermal throttling or TCC + * activation temperature equals "Tjmax" - "TCC Offset", in degree C. + * + * Return: On success returns 0, negative error code otherwise. + */ + +int intel_tcc_set_offset(int cpu, int offset) +{ + u32 low, high; + int err; + + if (offset < 0 || offset > 0x3f) + return -EINVAL; + + if (cpu < 0) + err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &low, &high); + else + err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &low, &high); + if (err) + return err; + + /* MSR Locked */ + if (low & BIT(31)) + return -EPERM; + + low &= ~(0x3f << 24); + low |= offset << 24; + + if (cpu < 0) + return wrmsr_safe(MSR_IA32_TEMPERATURE_TARGET, low, high); + else + return wrmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, low, high); +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_set_offset, INTEL_TCC); + +/** + * intel_tcc_get_temp() - returns the current temperature + * @cpu: cpu that the MSR should be run on, nagative value means any cpu. + * @pkg: true: Package Thermal Sensor. false: Core Thermal Sensor. + * + * Get the current temperature returned by the CPU core/package level + * thermal sensor, in degrees C. + * + * Return: Temperature in degrees C on success, negative error code otherwise. + */ +int intel_tcc_get_temp(int cpu, bool pkg) +{ + u32 low, high; + u32 msr = pkg ? MSR_IA32_PACKAGE_THERM_STATUS : MSR_IA32_THERM_STATUS; + int tjmax, temp, err; + + tjmax = intel_tcc_get_tjmax(cpu); + if (tjmax < 0) + return tjmax; + + if (cpu < 0) + err = rdmsr_safe(msr, &low, &high); + else + err = rdmsr_safe_on_cpu(cpu, msr, &low, &high); + if (err) + return err; + + /* Temperature is beyond the valid thermal sensor range */ + if (!(low & BIT(31))) + return -ENODATA; + + temp = tjmax - ((low >> 16) & 0x7f); + + /* Do not allow negative CPU temperature */ + return temp >= 0 ? temp : -ENODATA; +} +EXPORT_SYMBOL_NS_GPL(intel_tcc_get_temp, INTEL_TCC); diff --git a/include/linux/intel_tcc.h b/include/linux/intel_tcc.h new file mode 100644 index 000000000000..f422612c28d6 --- /dev/null +++ b/include/linux/intel_tcc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * header for Intel TCC (thermal control circuitry) library + * + * Copyright (C) 2022 Intel Corporation. + */ + +#ifndef __INTEL_TCC_H__ +#define __INTEL_TCC_H__ + +#include + +int intel_tcc_get_tjmax(int cpu); +int intel_tcc_get_offset(int cpu); +int intel_tcc_set_offset(int cpu, int offset); +int intel_tcc_get_temp(int cpu, bool pkg); + +#endif /* __INTEL_TCC_H__ */ From patchwork Mon Dec 19 15:46:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 13076717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48E13C4332F for ; Mon, 19 Dec 2022 15:39:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229781AbiLSPjP (ORCPT ); Mon, 19 Dec 2022 10:39:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232268AbiLSPjO (ORCPT ); Mon, 19 Dec 2022 10:39:14 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A33691180D for ; Mon, 19 Dec 2022 07:39:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671464353; x=1703000353; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=WjLjJqVpr9ryArdMJb+Zb1klQB3M0pfezXp+V752k6c=; b=C8XbRsRtt8NCEzpkA4zSSKTrWghYkO9UqlzupPpNzFxmrdzNPMCCF1tr jNb9yEHKx2nDSW2wOYptmtF6bkYM/i4cDd4ayDowGlLGKZ/eC67dq51Nk XTndZsBkhGDMpTqjEP9WT8T2NcEyFhh2i297N4fsgrNEepT5y68TxbX7U yCOZKzig80iZ867oo4sm7LJTrz/Ay1MRzc419pYulUEkNQJSnEIatcTWS cc8As6pvzEqrcVNt870XZcp9M9jpKpyz6WRqddloLEgIlbHAjKj2uPVNI 9Yv9CDMKBQ+VPxmjhASWPnWgsc/MRS9iAimBuvdIzQcgLDa2fgOE09o8g w==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="307051223" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="307051223" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 07:39:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="774960325" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="774960325" Received: from power-sh.sh.intel.com ([10.239.183.7]) by orsmga004.jf.intel.com with ESMTP; 19 Dec 2022 07:39:11 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com, rui.zhang@intel.com Subject: [PATCH V2 2/6] thermal/int340x/processor_thermal: Use Intel TCC library Date: Mon, 19 Dec 2022 23:46:16 +0800 Message-Id: <20221219154620.3630-3-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219154620.3630-1-rui.zhang@intel.com> References: <20221219154620.3630-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cleanup the code by using Intel TCC library for TCC (Thermal Control Circuitry) MSR access. Signed-off-by: Zhang Rui --- drivers/thermal/intel/int340x_thermal/Kconfig | 1 + .../processor_thermal_device.c | 119 ++++-------------- 2 files changed, 22 insertions(+), 98 deletions(-) diff --git a/drivers/thermal/intel/int340x_thermal/Kconfig b/drivers/thermal/intel/int340x_thermal/Kconfig index 5d046de96a5d..0f511917e0e1 100644 --- a/drivers/thermal/intel/int340x_thermal/Kconfig +++ b/drivers/thermal/intel/int340x_thermal/Kconfig @@ -10,6 +10,7 @@ config INT340X_THERMAL select ACPI_THERMAL_REL select ACPI_FAN select INTEL_SOC_DTS_IOSF_CORE + select INTEL_TCC select PROC_THERMAL_MMIO_RAPL if POWERCAP help Newer laptops and tablets that use ACPI may have thermal sensors and diff --git a/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c b/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c index a8d98f1bd6c6..a2ea22f2bffd 100644 --- a/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c +++ b/drivers/thermal/intel/int340x_thermal/processor_thermal_device.c @@ -4,6 +4,7 @@ * Copyright (c) 2014, Intel Corporation. */ #include +#include #include #include #include @@ -68,54 +69,17 @@ static const struct attribute_group power_limit_attribute_group = { .name = "power_limits" }; -static int tcc_get_offset(void) -{ - u64 val; - int err; - - err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); - if (err) - return err; - - return (val >> 24) & 0x3f; -} - static ssize_t tcc_offset_degree_celsius_show(struct device *dev, struct device_attribute *attr, char *buf) { - int tcc; - - tcc = tcc_get_offset(); - if (tcc < 0) - return tcc; + int offset; - return sprintf(buf, "%d\n", tcc); -} - -static int tcc_offset_update(unsigned int tcc) -{ - u64 val; - int err; - - if (tcc > 63) - return -EINVAL; - - err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); - if (err) - return err; - - if (val & BIT(31)) - return -EPERM; - - val &= ~GENMASK_ULL(29, 24); - val |= (tcc & 0x3f) << 24; - - err = wrmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, val); - if (err) - return err; + offset = intel_tcc_get_offset(-1); + if (offset < 0) + return offset; - return 0; + return sprintf(buf, "%d\n", offset); } static ssize_t tcc_offset_degree_celsius_store(struct device *dev, @@ -136,7 +100,7 @@ static ssize_t tcc_offset_degree_celsius_store(struct device *dev, if (kstrtouint(buf, 0, &tcc)) return -EINVAL; - err = tcc_offset_update(tcc); + err = intel_tcc_set_offset(-1, tcc); if (err) return err; @@ -145,66 +109,25 @@ static ssize_t tcc_offset_degree_celsius_store(struct device *dev, static DEVICE_ATTR_RW(tcc_offset_degree_celsius); -static int stored_tjmax; /* since it is fixed, we can have local storage */ - -static int get_tjmax(void) -{ - u32 eax, edx; - u32 val; - int err; - - err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); - if (err) - return err; - - val = (eax >> 16) & 0xff; - if (val) - return val; - - return -EINVAL; -} - -static int read_temp_msr(int *temp) +static int proc_thermal_get_zone_temp(struct thermal_zone_device *zone, + int *temp) { int cpu; - u32 eax, edx; - int err; - unsigned long curr_temp_off = 0; + int curr_temp; *temp = 0; for_each_online_cpu(cpu) { - err = rdmsr_safe_on_cpu(cpu, MSR_IA32_THERM_STATUS, &eax, - &edx); - if (err) - goto err_ret; - else { - if (eax & 0x80000000) { - curr_temp_off = (eax >> 16) & 0x7f; - if (!*temp || curr_temp_off < *temp) - *temp = curr_temp_off; - } else { - err = -EINVAL; - goto err_ret; - } - } + curr_temp = intel_tcc_get_temp(cpu, false); + if (curr_temp < 0) + return curr_temp; + if (!*temp || curr_temp > *temp) + *temp = curr_temp; } - return 0; -err_ret: - return err; -} - -static int proc_thermal_get_zone_temp(struct thermal_zone_device *zone, - int *temp) -{ - int ret; - - ret = read_temp_msr(temp); - if (!ret) - *temp = (stored_tjmax - *temp) * 1000; + *temp *= 1000; - return ret; + return 0; } static struct thermal_zone_device_ops proc_thermal_local_ops = { @@ -302,8 +225,7 @@ int proc_thermal_add(struct device *dev, struct proc_thermal_device *proc_priv) status = acpi_evaluate_integer(adev->handle, "_TMP", NULL, &tmp); if (ACPI_FAILURE(status)) { /* there is no _TMP method, add local method */ - stored_tjmax = get_tjmax(); - if (stored_tjmax > 0) + if (intel_tcc_get_tjmax(-1) > 0) ops = &proc_thermal_local_ops; } @@ -356,7 +278,7 @@ static int tcc_offset_save = -1; int proc_thermal_suspend(struct device *dev) { - tcc_offset_save = tcc_get_offset(); + tcc_offset_save = intel_tcc_get_offset(-1); if (tcc_offset_save < 0) dev_warn(dev, "failed to save offset (%d)\n", tcc_offset_save); @@ -373,7 +295,7 @@ int proc_thermal_resume(struct device *dev) /* Do not update if saving failed */ if (tcc_offset_save >= 0) - tcc_offset_update(tcc_offset_save); + intel_tcc_set_offset(-1, tcc_offset_save); return 0; } @@ -460,6 +382,7 @@ void proc_thermal_mmio_remove(struct pci_dev *pdev, struct proc_thermal_device * } EXPORT_SYMBOL_GPL(proc_thermal_mmio_remove); +MODULE_IMPORT_NS(INTEL_TCC); MODULE_AUTHOR("Srinivas Pandruvada "); MODULE_DESCRIPTION("Processor Thermal Reporting Device Driver"); MODULE_LICENSE("GPL v2"); From patchwork Mon Dec 19 15:46:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 13076718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CC60C4167B for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="307051236" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="307051236" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 07:39:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="774960332" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="774960332" Received: from power-sh.sh.intel.com ([10.239.183.7]) by orsmga004.jf.intel.com with ESMTP; 19 Dec 2022 07:39:13 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com, rui.zhang@intel.com Subject: [PATCH V2 3/6] thermal/intel/intel_soc_dts_iosf: Use Intel TCC library Date: Mon, 19 Dec 2022 23:46:17 +0800 Message-Id: <20221219154620.3630-4-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219154620.3630-1-rui.zhang@intel.com> References: <20221219154620.3630-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cleanup the code by using Intel TCC library for TCC (Thermal Control Circuitry) MSR access. Signed-off-by: Zhang Rui --- drivers/thermal/intel/Kconfig | 1 + drivers/thermal/intel/intel_soc_dts_iosf.c | 33 ++++------------------ 2 files changed, 6 insertions(+), 28 deletions(-) diff --git a/drivers/thermal/intel/Kconfig b/drivers/thermal/intel/Kconfig index 6b938c040d6e..329c0ee934c4 100644 --- a/drivers/thermal/intel/Kconfig +++ b/drivers/thermal/intel/Kconfig @@ -32,6 +32,7 @@ config INTEL_SOC_DTS_IOSF_CORE tristate depends on X86 && PCI select IOSF_MBI + select INTEL_TCC help This is becoming a common feature for Intel SoCs to expose the additional digital temperature sensors (DTSs) using side band interface (IOSF). This diff --git a/drivers/thermal/intel/intel_soc_dts_iosf.c b/drivers/thermal/intel/intel_soc_dts_iosf.c index 342b0bb5a56d..2138693d8afd 100644 --- a/drivers/thermal/intel/intel_soc_dts_iosf.c +++ b/drivers/thermal/intel/intel_soc_dts_iosf.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include @@ -45,32 +46,6 @@ /* DTS0 and DTS 1 */ #define SOC_MAX_DTS_SENSORS 2 -static int get_tj_max(u32 *tj_max) -{ - u32 eax, edx; - u32 val; - int err; - - err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); - if (err) - goto err_ret; - else { - val = (eax >> 16) & 0xff; - if (val) - *tj_max = val * 1000; - else { - err = -EINVAL; - goto err_ret; - } - } - - return 0; -err_ret: - *tj_max = 0; - - return err; -} - static int sys_get_trip_temp(struct thermal_zone_device *tzd, int trip, int *temp) { @@ -415,8 +390,9 @@ struct intel_soc_dts_sensors *intel_soc_dts_iosf_init( if (!trip_count || read_only_trip_count > trip_count) return ERR_PTR(-EINVAL); - if (get_tj_max(&tj_max)) - return ERR_PTR(-EINVAL); + tj_max = intel_tcc_get_tjmax(-1); + if (tj_max < 0) + return ERR_PTR(tj_max); sensors = kzalloc(sizeof(*sensors), GFP_KERNEL); if (!sensors) @@ -475,4 +451,5 @@ void intel_soc_dts_iosf_exit(struct intel_soc_dts_sensors *sensors) } EXPORT_SYMBOL_GPL(intel_soc_dts_iosf_exit); +MODULE_IMPORT_NS(INTEL_TCC); MODULE_LICENSE("GPL v2"); From patchwork Mon Dec 19 15:46:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 13076719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F9F2C4332F for ; Mon, 19 Dec 2022 15:39:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232326AbiLSPjU (ORCPT ); Mon, 19 Dec 2022 10:39:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232292AbiLSPjR (ORCPT ); Mon, 19 Dec 2022 10:39:17 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 228BA11807 for ; Mon, 19 Dec 2022 07:39:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671464357; x=1703000357; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=cP0pwvMyQvIEbCrwUdFXadweBwuCrJ7kDmYMN+bfngU=; b=RuZnQxJXvoXFAS5LA0+4MMhUf0N3j5YjavHl/7hsz0okCFXaB2pLbC+o BH64btiyMiv9puyy8BXxhx7qgPV2YL8HMcS/JOVwNkH0XWuDO4CO9/yzh kmDHpEg9HcQtmxRY3M8nlUowrCg+0CevsdqiVh5yCqfbQVYWNbd6QM0A7 Ph3jT9jimQK+8KkFD65l0Bw6mBmTDWSDKRmF4EsGSFrRo4V1Rf0dK7vZW 6TPHICcdIXSLBCH+UEsoYC0TcUSWRLmn8gq9RwSplThGM27l6wdiVMH6f 78lMpsqAa3uNb2cOQuyetsMTZMPI4wLkWsDPegCTB4xzMf02YaJTaqjtd A==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="307051247" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="307051247" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 07:39:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="774960338" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="774960338" Received: from power-sh.sh.intel.com ([10.239.183.7]) by orsmga004.jf.intel.com with ESMTP; 19 Dec 2022 07:39:15 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com, rui.zhang@intel.com Subject: [PATCH V2 4/6] thermal/intel/intel_tcc_cooling: Use Intel TCC library Date: Mon, 19 Dec 2022 23:46:18 +0800 Message-Id: <20221219154620.3630-5-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219154620.3630-1-rui.zhang@intel.com> References: <20221219154620.3630-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cleanup the code by using Intel TCC library for TCC (Thermal Control Circuitry) MSR access. Signed-off-by: Zhang Rui --- drivers/thermal/intel/Kconfig | 1 + drivers/thermal/intel/intel_tcc_cooling.c | 37 +++++------------------ 2 files changed, 9 insertions(+), 29 deletions(-) diff --git a/drivers/thermal/intel/Kconfig b/drivers/thermal/intel/Kconfig index 329c0ee934c4..dafdb3dd3fc7 100644 --- a/drivers/thermal/intel/Kconfig +++ b/drivers/thermal/intel/Kconfig @@ -88,6 +88,7 @@ config INTEL_PCH_THERMAL config INTEL_TCC_COOLING tristate "Intel TCC offset cooling Driver" depends on X86 + select INTEL_TCC help Enable this to support system cooling by adjusting the effective TCC activation temperature via the TCC Offset register, which is widely diff --git a/drivers/thermal/intel/intel_tcc_cooling.c b/drivers/thermal/intel/intel_tcc_cooling.c index 95adac427b6f..c5b559a123fd 100644 --- a/drivers/thermal/intel/intel_tcc_cooling.c +++ b/drivers/thermal/intel/intel_tcc_cooling.c @@ -7,12 +7,11 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include -#define TCC_SHIFT 24 -#define TCC_MASK (0x3fULL<<24) #define TCC_PROGRAMMABLE BIT(30) static struct thermal_cooling_device *tcc_cdev; @@ -20,47 +19,26 @@ static struct thermal_cooling_device *tcc_cdev; static int tcc_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state) { - *state = TCC_MASK >> TCC_SHIFT; - return 0; -} - -static int tcc_offset_update(int tcc) -{ - u64 val; - int err; - - err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); - if (err) - return err; - - val &= ~TCC_MASK; - val |= tcc << TCC_SHIFT; - - err = wrmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, val); - if (err) - return err; - + *state = 0x3f; return 0; } static int tcc_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state) { - u64 val; - int err; + int offset = intel_tcc_get_offset(-1); - err = rdmsrl_safe(MSR_IA32_TEMPERATURE_TARGET, &val); - if (err) - return err; + if (offset < 0) + return offset; - *state = (val & TCC_MASK) >> TCC_SHIFT; + *state = offset; return 0; } static int tcc_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state) { - return tcc_offset_update(state); + return intel_tcc_set_offset(-1, (int)state); } static const struct thermal_cooling_device_ops tcc_cooling_ops = { @@ -129,6 +107,7 @@ static void __exit tcc_cooling_exit(void) module_exit(tcc_cooling_exit) +MODULE_IMPORT_NS(INTEL_TCC); MODULE_DESCRIPTION("TCC offset cooling device Driver"); MODULE_AUTHOR("Zhang Rui "); MODULE_LICENSE("GPL v2"); From patchwork Mon Dec 19 15:46:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 13076720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F882C10F1B for ; Mon, 19 Dec 2022 15:39:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231370AbiLSPjX (ORCPT ); Mon, 19 Dec 2022 10:39:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232299AbiLSPjU (ORCPT ); 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19 Dec 2022 07:39:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="774960348" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="774960348" Received: from power-sh.sh.intel.com ([10.239.183.7]) by orsmga004.jf.intel.com with ESMTP; 19 Dec 2022 07:39:17 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com, rui.zhang@intel.com Subject: [PATCH V2 5/6] thermal/x86_pkg_temp_thermal: Use Intel TCC library Date: Mon, 19 Dec 2022 23:46:19 +0800 Message-Id: <20221219154620.3630-6-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219154620.3630-1-rui.zhang@intel.com> References: <20221219154620.3630-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Cleanup the code by using Intel TCC library for TCC (Thermal Control Circuitry) MSR access. Signed-off-by: Zhang Rui --- drivers/thermal/intel/Kconfig | 1 + drivers/thermal/intel/x86_pkg_temp_thermal.c | 44 ++++++-------------- 2 files changed, 14 insertions(+), 31 deletions(-) diff --git a/drivers/thermal/intel/Kconfig b/drivers/thermal/intel/Kconfig index dafdb3dd3fc7..fd41c810629b 100644 --- a/drivers/thermal/intel/Kconfig +++ b/drivers/thermal/intel/Kconfig @@ -21,6 +21,7 @@ config X86_PKG_TEMP_THERMAL depends on X86_THERMAL_VECTOR select THERMAL_GOV_USER_SPACE select THERMAL_WRITABLE_TRIPS + select INTEL_TCC default m help Enable this to register CPU digital sensor for package temperature as diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c index a0e234fce71a..416ff23da4de 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -104,38 +105,18 @@ static struct zone_device *pkg_temp_thermal_get_dev(unsigned int cpu) return NULL; } -/* -* tj-max is interesting because threshold is set relative to this -* temperature. -*/ -static int get_tj_max(int cpu, u32 *tj_max) -{ - u32 eax, edx, val; - int err; - - err = rdmsr_safe_on_cpu(cpu, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx); - if (err) - return err; - - val = (eax >> 16) & 0xff; - *tj_max = val * 1000; - - return val ? 0 : -EINVAL; -} - static int sys_get_curr_temp(struct thermal_zone_device *tzd, int *temp) { struct zone_device *zonedev = tzd->devdata; - u32 eax, edx; + int val; - rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_STATUS, - &eax, &edx); - if (eax & 0x80000000) { - *temp = zonedev->tj_max - ((eax >> 16) & 0x7f) * 1000; - pr_debug("sys_get_curr_temp %d\n", *temp); - return 0; - } - return -EINVAL; + val = intel_tcc_get_temp(zonedev->cpu, true); + if (val < 0) + return val; + + *temp = val * 1000; + pr_debug("sys_get_curr_temp %d\n", *temp); + return 0; } static int sys_get_trip_temp(struct thermal_zone_device *tzd, @@ -345,9 +326,9 @@ static int pkg_temp_thermal_device_add(unsigned int cpu) thres_count = clamp_val(thres_count, 0, MAX_NUMBER_OF_TRIPS); - err = get_tj_max(cpu, &tj_max); - if (err) - return err; + tj_max = intel_tcc_get_tjmax(cpu); + if (tj_max < 0) + return tj_max; zonedev = kzalloc(sizeof(*zonedev), GFP_KERNEL); if (!zonedev) @@ -536,6 +517,7 @@ static void __exit pkg_temp_thermal_exit(void) } module_exit(pkg_temp_thermal_exit) +MODULE_IMPORT_NS(INTEL_TCC); MODULE_DESCRIPTION("X86 PKG TEMP Thermal Driver"); MODULE_AUTHOR("Srinivas Pandruvada "); MODULE_LICENSE("GPL v2"); From patchwork Mon Dec 19 15:46:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 13076721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7833C4332F for ; Mon, 19 Dec 2022 15:39:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231739AbiLSPjZ (ORCPT ); Mon, 19 Dec 2022 10:39:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232341AbiLSPjW (ORCPT ); Mon, 19 Dec 2022 10:39:22 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4028411838 for ; Mon, 19 Dec 2022 07:39:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671464361; x=1703000361; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=z54DaDYRtkOEulF9x0NJLtJ7Ea+wxw4HXszOh07R6Qg=; b=iUks4BU1LFRz2ER2JQ9rsk2O6/qmHOU+zBmtCXbuEwKLXy+M8pjRs4AM n5OrcQwtClM4Yhkd1LwprQMwWUOnqAPLCRA9pDgADZQs3cGCSGExfiSHv 11aJZKmRSdr2gYe/9xtyNcKOyyTnBJ8MZbhv+yFvtCnhGesDihQhuJqFH czkGFmU4cd7pxvy/90MkchA8UEZa/wDi6NEKh3RIdRL1ZAsCDIv1HZrTS Mam8WgP4js0G1VlPBIaFtF+EWOQmhTGYu8diyXboEJ09YAmAHVCwtD29z DCNNQNWVrGrSM+hJm2IEhZXo0txO9+G/NhhV9lJ2Xzu3MHfFX/J25dtTt A==; X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="307051276" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="307051276" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 07:39:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10566"; a="774960355" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="774960355" Received: from power-sh.sh.intel.com ([10.239.183.7]) by orsmga004.jf.intel.com with ESMTP; 19 Dec 2022 07:39:19 -0800 From: Zhang Rui To: rjw@rjwysocki.net, daniel.lezcano@linaro.org Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@linux.intel.com, rui.zhang@intel.com Subject: [PATCH V2 6/6] thermal/x86_pkg_temp_thermal: Add support for handling dynamic tjmax Date: Mon, 19 Dec 2022 23:46:20 +0800 Message-Id: <20221219154620.3630-7-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221219154620.3630-1-rui.zhang@intel.com> References: <20221219154620.3630-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Tjmax value retrieved from MSR_IA32_TEMPERATURE_TARGET can be changed at runtime when the Intel SST-PP (Intel Speed Select Technology - Performance Profile) level is changed. Enhance the code to use updated tjmax when programming the thermal interrupt thresholds. Signed-off-by: Zhang Rui --- drivers/thermal/intel/x86_pkg_temp_thermal.c | 30 +++++++++++++------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal/intel/x86_pkg_temp_thermal.c index 416ff23da4de..954cbceaf786 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -49,7 +49,6 @@ MODULE_PARM_DESC(notify_delay_ms, struct zone_device { int cpu; bool work_scheduled; - u32 tj_max; u32 msr_pkg_therm_low; u32 msr_pkg_therm_high; struct delayed_work work; @@ -125,7 +124,7 @@ static int sys_get_trip_temp(struct thermal_zone_device *tzd, struct zone_device *zonedev = tzd->devdata; unsigned long thres_reg_value; u32 mask, shift, eax, edx; - int ret; + int tj_max, ret; if (trip >= MAX_NUMBER_OF_TRIPS) return -EINVAL; @@ -138,6 +137,11 @@ static int sys_get_trip_temp(struct thermal_zone_device *tzd, shift = THERM_SHIFT_THRESHOLD0; } + tj_max = intel_tcc_get_tjmax(zonedev->cpu); + if (tj_max < 0) + return tj_max; + tj_max *= 1000; + ret = rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &eax, &edx); if (ret < 0) @@ -145,7 +149,7 @@ static int sys_get_trip_temp(struct thermal_zone_device *tzd, thres_reg_value = (eax & mask) >> shift; if (thres_reg_value) - *temp = zonedev->tj_max - thres_reg_value * 1000; + *temp = tj_max - thres_reg_value * 1000; else *temp = THERMAL_TEMP_INVALID; pr_debug("sys_get_trip_temp %d\n", *temp); @@ -158,9 +162,14 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, int trip, int temp) { struct zone_device *zonedev = tzd->devdata; u32 l, h, mask, shift, intr; - int ret; + int tj_max, ret; - if (trip >= MAX_NUMBER_OF_TRIPS || temp >= zonedev->tj_max) + tj_max = intel_tcc_get_tjmax(zonedev->cpu); + if (tj_max < 0) + return tj_max; + tj_max *= 1000; + + if (trip >= MAX_NUMBER_OF_TRIPS || temp >= tj_max) return -EINVAL; ret = rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, @@ -185,7 +194,7 @@ sys_set_trip_temp(struct thermal_zone_device *tzd, int trip, int temp) if (!temp) { l &= ~intr; } else { - l |= (zonedev->tj_max - temp)/1000 << shift; + l |= (tj_max - temp)/1000 << shift; l |= intr; } @@ -312,7 +321,7 @@ static int pkg_thermal_notify(u64 msr_val) static int pkg_temp_thermal_device_add(unsigned int cpu) { int id = topology_logical_die_id(cpu); - u32 tj_max, eax, ebx, ecx, edx; + u32 eax, ebx, ecx, edx; struct zone_device *zonedev; int thres_count, err; @@ -326,9 +335,9 @@ static int pkg_temp_thermal_device_add(unsigned int cpu) thres_count = clamp_val(thres_count, 0, MAX_NUMBER_OF_TRIPS); - tj_max = intel_tcc_get_tjmax(cpu); - if (tj_max < 0) - return tj_max; + err = intel_tcc_get_tjmax(cpu); + if (err < 0) + return err; zonedev = kzalloc(sizeof(*zonedev), GFP_KERNEL); if (!zonedev) @@ -336,7 +345,6 @@ static int pkg_temp_thermal_device_add(unsigned int cpu) INIT_DELAYED_WORK(&zonedev->work, pkg_temp_thermal_threshold_work_fn); zonedev->cpu = cpu; - zonedev->tj_max = tj_max; zonedev->tzone = thermal_zone_device_register("x86_pkg_temp", thres_count, (thres_count == MAX_NUMBER_OF_TRIPS) ? 0x03 : 0x01,