From patchwork Fri Dec 23 01:50:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 13080594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4906C4332F for ; Fri, 23 Dec 2022 02:32:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fuW3uA+/Mh3KGoQ4XFvk6315f0WjUGGeFv7c7bwDHi8=; b=HU0vl1yd8dGcww CNsU1yKboMocDD0wc3R0t86rLwvgIHN6BH1rH2elo8QwEzyXzUVXJftTenxx34tkByWinHlOWIgdY eQqnTS5AA2OanO5pPmw/5dF7+9NyY/onQRTHojBHpku7V46UdknUDzEJgEKnD2rRsjW3slbUI5ciU 3kFmElJPGUdjPHws8eW0gafhVIDbjKBxVSsaK5ErMEUIUgR8D3P92xf3UsU8SaUNFo8I4OJMyUn6O 6Ioqt07ssJzCoSQwH/+r6wtX3NkWp+ndA9p2KnarEEGdKgC6IT7LLfDMBISJ+HxYKBF7XxXXl7xEo IST2VA5A88e5q/3kPlRw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p8XqW-0024x0-Oa; Fri, 23 Dec 2022 02:31:40 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p8XqF-0024mn-Ss; Fri, 23 Dec 2022 02:31:25 +0000 X-UUID: 9f84268e670c49b38a6edfcb03929381-20221222 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BseEKJDeDeZ7+Gz+rMrpO4HRXtkR+aAiH33ITZwHI4k=; b=dY5fXjC/KHfMz9V+Z2TNxVKKDOWtSaLbz07FHlHKeQ53qEyow+7HR8Ee2Yj3En7NtVzx1tohuF5LDD6cYtYVdyHh1Qcl7gZqVoiajn7/sORJGX6qeOn2Y96SZLOFopXe2PzeO10PnozdEk7/iiFbO7LBSZbi/K2UxJYCVxBaa2s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:667a7e1d-c173-4938-b12e-5c2373c0bf2c,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:dcaaed0,CLOUDID:91752a8a-8530-4eff-9f77-222cf6e2895b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 9f84268e670c49b38a6edfcb03929381-20221222 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 257220090; Thu, 22 Dec 2022 19:31:19 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Fri, 23 Dec 2022 09:50:41 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 23 Dec 2022 09:50:40 +0800 From: Biao Huang To: Andrew Lunn , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Maxime Coquelin , Richard Cochran , , , , , "Biao Huang" , Subject: [PATCH v5 1/2] stmmac: dwmac-mediatek: enable 2ns delay only for special cases Date: Fri, 23 Dec 2022 09:50:28 +0800 Message-ID: <20221223015029.24978-2-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221223015029.24978-1-biao.huang@mediatek.com> References: <20221223015029.24978-1-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221222_183123_988466_0181CF73 X-CRM114-Status: GOOD ( 12.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In current driver, MAC will always enable 2ns delay in RGMII mode, but that will lead to transmission failures for "rgmii-id"/"rgmii-txid" cases. Modify the implementation of fix_mac_speed() to ensure the 2ns delay will only take effect for "rgmii-rxid"/"rgmii" cases, then user can choose phy-mode freely. Fixes: f2d356a6ab71 ("stmmac: dwmac-mediatek: add support for mt8195") Signed-off-by: Biao Huang Reviewed-by: AngeloGioacchino Del Regno --- drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c index d42e1afb6521..cde4fb81d596 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c @@ -447,7 +447,9 @@ static void mt8195_fix_mac_speed(void *priv, unsigned int speed) { struct mediatek_dwmac_plat_data *priv_plat = priv; - if ((phy_interface_mode_is_rgmii(priv_plat->phy_mode))) { + switch (priv_plat->phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: /* prefer 2ns fixed delay which is controlled by TXC_PHASE_CTRL, * when link speed is 1Gbps with RGMII interface, * Fall back to delay macro circuit for 10/100Mbps link speed. @@ -462,6 +464,9 @@ static void mt8195_fix_mac_speed(void *priv, unsigned int speed) MT8195_RGMII_TXC_PHASE_CTRL); else mt8195_set_delay(priv_plat); + break; + default: + break; } } From patchwork Fri Dec 23 01:50:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QmlhbyBIdWFuZyAo6buE5b2qKQ==?= X-Patchwork-Id: 13080599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B668C4332F for ; Fri, 23 Dec 2022 02:45:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KG7eySzf53ENJX9dxI3LXNRDqHd8GBW/xD/ZzGTybfc=; b=06xH4BXBAVfLqh pjsvDEiFQkb5MLInifmVkh+M7tm9E+qIjmUvyzwLuyhkm9rVBX/EWMIDhyftjNN7MRRoiXEhMD12A geDSs6pRn2VXFdGYOnnln9VZZ9z79i5alauwcj+STbBhsqPDRwQWUCSJrqpmXavricux+ms/OZqyJ S8TJ+vScmni/UMOpSTQrLOSnCiEyjP2KP8znZseBDtwwK2Qv+anuFWzhl3gzeBGioeE7nSB0PByOg 05cc4Xp1NgpM/T4EU6Ng/WRMs1nc40w0yHxHkpx4RK2IgWVR8sZBS4PiddccwNf+zfPXvn3yjQi2P 5UMt6PyXc40hOoF44UEw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1p8Y2V-002COS-QO; Fri, 23 Dec 2022 02:44:04 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1p8Xzw-002AjN-Nq; Fri, 23 Dec 2022 02:41:27 +0000 X-UUID: ce1531a3f83b48c4b0a5f5e76d1276d7-20221222 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=RetU9plkC6PlzdhyrPl9diuDAf2ccELX3EGs8VyzYRM=; b=D52o/J04XB4Ir6uyEs8pwAOiVUOoPttG3PIaMQsuDLasJOaIq23NA1NQj570Qd5Dbt5dexrzI0BLHcGvJ/XP0EvAy6ZdCIpM5fp96R/esMgvIhtBHIaHw9L2Dbt8xwGggsMAnyi5ncz86CLpK7yb6E4HQne5no45xOJrKqlbWcY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.14,REQID:48d7197d-c56d-40fd-b290-402f4804b981,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:dcaaed0,CLOUDID:06c42a8a-8530-4eff-9f77-222cf6e2895b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: ce1531a3f83b48c4b0a5f5e76d1276d7-20221222 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2114717160; Thu, 22 Dec 2022 19:41:17 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 23 Dec 2022 09:50:43 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 23 Dec 2022 09:50:41 +0800 From: Biao Huang To: Andrew Lunn , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Richard Cochran , , , , , Biao Huang , Subject: [PATCH v5 2/2] arm64: dts: mt8195: Add Ethernet controller Date: Fri, 23 Dec 2022 09:50:29 +0800 Message-ID: <20221223015029.24978-3-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221223015029.24978-1-biao.huang@mediatek.com> References: <20221223015029.24978-1-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221222_184124_889385_B259AE4A X-CRM114-Status: UNSURE ( 9.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add Ethernet controller node for mt8195. Signed-off-by: Biao Huang Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 81 ++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 86 ++++++++++++++++++++ 2 files changed, 167 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index 4fbd99eb496a..2e6979c47aa6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -258,6 +258,66 @@ &mt6359_vsram_others_ldo_reg { }; &pio { + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = , + , + , + ; + drive-strength = ; + }; + pins-cc { + pinmux = , + , + , + ; + drive-strength = ; + }; + pins-rxd { + pinmux = , + , + , + ; + }; + pins-mdio { + pinmux = , + ; + input-enable; + }; + pins-power { + pinmux = , + ; + output-high; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = , + , + , + ; + }; + pins-cc { + pinmux = , + , + , + ; + }; + pins-rxd { + pinmux = , + , + , + ; + }; + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + }; + gpio_keys_pins: gpio-keys-pins { pins { pinmux = ; @@ -434,6 +494,27 @@ &xhci0 { status = "okay"; }; +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 10000 10000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + }; + }; +}; + &xhci1 { vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d31536f4c48..b90d38d87aa4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1046,6 +1046,92 @@ spis1: spi@1101e000 { status = "disabled"; }; + eth: ethernet@11021000 { + compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; + reg = <0 0x11021000 0 0x4000>; + interrupts = ; + interrupt-names = "macirq"; + clock-names = "axi", + "apb", + "mac_main", + "ptp_ref", + "rmii_internal", + "mac_cg"; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; + mediatek,pericfg = <&infracfg_ao>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + queue3 { + snps,weight = <0x13>; + snps,dcb-algorithm; + snps,priority = <0x3>; + }; + }; + }; + xhci0: usb@11200000 { compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";