From patchwork Sat Dec 31 10:47:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F96DC3DA7A for ; Sat, 31 Dec 2022 10:49:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ds2qalRtQ0cYyJ9PleRLy0AIPfOhNEMwCwU/bV0wslQ=; b=JUMFz3cmMxcAZ2 6ZzytjOos+NoZQS/kaULn5csF4IqAFNoOEAlrxGtiEGnW9x5P2K/HEW5qKs1+cjDVgWY3TF8gWbJb +uk3v2Yf+v4P2+Qhp0YlJKQ/AQXy2G8mEUnz/gHUkHQaxPFuPdPDTKovkcYWa7+gzSHr/oYRgq1st fPsfy0iuZ7dXhdf5CXOQN1h/yXnCAi6m4tCbPctXoFGIVfB0iOXuOqlt6wOmqRPApIfBx8vZgcq4z YvczU2jp4W4AvhK2c5B4/87+Xl+2TOGgRFAsqY+3j9Y7r3mqAq7mVqhKglLhsBOUbVeRkulmrl8CO uITQfsH/MEpexLdBTVSQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZPW-0042n0-Pk; Sat, 31 Dec 2022 10:48:18 +0000 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZP6-0042QR-VD for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 10:47:54 +0000 Received: by mail-ej1-x635.google.com with SMTP id fc4so56329928ejc.12 for ; Sat, 31 Dec 2022 02:47:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MlxmeaIHk8OrzWPfE3cm09UY7yzoRBn0Uu2mQgPXmdk=; b=S+QfZYeGZv2u4Pj/RfMQHserifc6sZuTu+rOAN4eYOI89qwvHyEgnRIrVh8oBeeSgA y6kkfDGh4WOtOTFA4pXjUoEcJFaOLt48FlzmHzdxoHzDAbdtt+mGZ/NHSEtfJZWqC05o +Zr/ZptCwfmVuNOMQ4buPQs8qDjUQyV4k+GGU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MlxmeaIHk8OrzWPfE3cm09UY7yzoRBn0Uu2mQgPXmdk=; b=rXCn9G+4rfkpALjqsNBH6qJWcp4jzIROCdKRHL2xzTzsc/55B1SVWb0pHF88QvLCY0 /+rLmzGwPPrYeHGje0zp98IVuMWmxOSj5TR9wcd/NUDPuaor2B1myeXYHpWe3yiheDFa BBr68I2JOSaSdBcs3J9IdgMKyIatqjPw9cZ2WwtPJGbyMvJB+be1lC3CTRRsVkmWrVpB PTCTwSfb+SPcDayoBN9gcSFgDYVSwAgjJqxubCBndl/GO/I/OtdV/IlP3k7B7M9/7cmj tDGMKVa61f+s1oeOphQbo/jja1jXIyH1dU5ZiReot4NGZpwyLEpE74ge+iwHAQ6nS+lv vG5w== X-Gm-Message-State: AFqh2kooLRj9njMUr2Kbfx0vzkMIYri22f5Rv6/uxbFRE1Uzp6Q8zso4 296zD37TItp2ELkWofROVf4t8Q== X-Google-Smtp-Source: AMrXdXssd4th2tQ+K3pikob5HvmOdLstBIM/Xz4rVcfK8ulWOXsUv0KvoKsIAwFQcCOjQNqi6CJzBw== X-Received: by 2002:a17:907:c296:b0:820:4046:1586 with SMTP id tk22-20020a170907c29600b0082040461586mr27687273ejc.12.1672483671115; Sat, 31 Dec 2022 02:47:51 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:50 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 01/11] clk: imx: add structure to extend register accesses Date: Sat, 31 Dec 2022 11:47:26 +0100 Message-Id: <20221231104736.12635-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_024753_037047_A9444729 X-CRM114-Status: GOOD ( 12.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The imx_clk_reg structure allows accessing both registers that belong to specific modules and those that are registered in syscon through the use of the regmap API. This is a preparation patch for the upcoming support to setup clocks directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 689b3ad927c0..86538c990a0d 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -89,6 +89,18 @@ struct imx_fracn_gppll_clk { int flags; }; +/** + * struct imx_clk_reg - imx register declaration + * @base: the register base address + * @regmap: the register map + * @offset: the offset within @base or @regmap + */ +struct imx_clk_reg { + void __iomem *base; + struct regmap *regmap; + u16 offset; +}; + struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk); From patchwork Sat Dec 31 10:47:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C69EC3DA7D for ; Sat, 31 Dec 2022 10:49:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=A1jcDxQXt2fbxp0V5iijat10Frdx9NleawtjhlY5Pho=; b=SSABSMS+eiq/mB hejd2g260/1oWAO765Jtkh/DOjsBxim0oi+gp3V8/kGqISxeTjm3C7FjnvsjD511PzhR+r3w/+95r D12/ufgI/dbI+C2MeAejaJJhKeViuNkMdR7VV8JxyWIJxH3kuz1RtH9znBSxI+PGuR/y7oeCuGfgC 9oLQAZHS8s5YW5OzMi5UfiTJX1bvd7/xkRUBo/Yuoirvo6kvMNBJN03VXYCNj1KcY8UeIqYTGDcRx TWv++oAHZ4OYH3ghZElMXDA8mNaf1xpBB0lieJBEBWjNFuSX6/XZvrqzDMwhJfCPy5/332poBFrSS WUidwjetwDEAEXTzcd/w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZPl-0042vc-KU; Sat, 31 Dec 2022 10:48:33 +0000 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZP8-0042Ri-PY for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 10:47:56 +0000 Received: by mail-ed1-x535.google.com with SMTP id s5so33552548edc.12 for ; Sat, 31 Dec 2022 02:47:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9LiLmCOA0Z19dwC3ajYydNnRTh+WZFHl0GJOC3Tfb7Q=; b=dpGsl32H+NNVcVtEIx85ju9cr7IPOJOUIB3kqId8lldf1S2UdBpejzWuX5tcYFMVkC SphizhvcFMKwotnjfF3ENAJyHrLnQOw1+cZsYrMbqnDe+d8tEmLIyZILWJetG6yFygEE pMEWbfKZYxwJNhExR13BT9opcQBihG3SXXY2k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9LiLmCOA0Z19dwC3ajYydNnRTh+WZFHl0GJOC3Tfb7Q=; b=oJLvo9xMnHsrlecfRCMDvHns8mRNIb9wmirJ1Ekq8j9XgpYNqwU8YYUlyJAaIUnAJu JOIMrbVhIUDTUEHBYElbm+0aI8jXOiNR7BgGjZUGo1ACLyHU0a1OB64x2NE0MdJ/L46j ahjJP74735a3lr+2rsnNShmrixwvN1fv/D7/eRFbce36GoOZ2ZnSxF4k+dFa0lgHGK+X g6BuNJXD9Ktsziokz2WiKRtonvrKttHc0dyLSIJ1o8zncU8LwvwEbrU3fs4p8QGWZHCY ff8UjKcP6nc0KLmsOECRycNSV1qMehfjLTYrVYMw1LWHSZGXH7z0VDooziYs8wTDjajC 7NAg== X-Gm-Message-State: AFqh2kralD1TlDLXDplp7E2SC5f+4Df2XUOrnClV04l2wwroaRuJ20nV lTJbEJkm9s0milBY5FrotCYDzw== X-Google-Smtp-Source: AMrXdXuh52WUWq6kR8l8ZywR9zEG9r0GqDzyIKcqeFwzq4G9eJcKVr/9ag8SH66WV0CFa3iTrqZ9Kg== X-Received: by 2002:a05:6402:f05:b0:45c:834b:f28c with SMTP id i5-20020a0564020f0500b0045c834bf28cmr31100958eda.9.1672483672554; Sat, 31 Dec 2022 02:47:52 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:52 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 02/11] clk: imx: add clk_hw based API imx_get_clk_hw_from_dt() Date: Sat, 31 Dec 2022 11:47:27 +0100 Message-Id: <20221231104736.12635-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_024754_866669_C48CA11E X-CRM114-Status: GOOD ( 13.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Clock providers are recommended to use the struct clk_hw based API, so add an IMX provider helper to get clk_hw from device tree node name. This is a preparation patch for the upcoming support to setup clocks directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk.c | 21 +++++++++++++++++++++ drivers/clk/imx/clk.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index b636cc099d96..6ae122ccd83e 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -68,6 +68,27 @@ void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count) } EXPORT_SYMBOL_GPL(imx_check_clk_hws); +struct clk_hw *imx_get_clk_hw_from_dt(struct device_node *np, + const char *name) +{ + struct of_phandle_args clkspec; + struct clk *clk; + + clkspec.np = of_find_node_by_name(np, name); + if (clkspec.np) { + clk = of_clk_get_from_provider(&clkspec); + if (!IS_ERR(clk)) { + pr_debug("%s: got %s clock\n", __func__, name); + of_node_put(clkspec.np); + return __clk_get_hw(clk); + } + } + + pr_err("%s: failed to %s clock\n", __func__, name); + return ERR_PTR(-ENODEV); +} +EXPORT_SYMBOL_GPL(imx_get_clk_hw_from_dt); + static struct clk *imx_obtain_fixed_clock_from_dt(const char *name) { struct of_phandle_args phandle; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 86538c990a0d..a0e6b8357eb7 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -294,6 +294,9 @@ struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, u8 clk_gate_flags, spinlock_t *lock, unsigned int *share_count); +struct clk_hw *imx_get_clk_hw_from_dt(struct device_node *np, + const char *name); + struct clk * imx_obtain_fixed_clock( const char *name, unsigned long rate); From patchwork Sat Dec 31 10:47:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47EEDC3DA7D for ; Sat, 31 Dec 2022 10:50:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=liXeVI1uyOCf3VyxLw/OVKQGv3JePs82QRNr0rBcVN0=; b=TKTRkK/++4wwbw VeiPW6dqN0yMWSnFUIAE7We/YogVG3Fd0V9KV521hBptzcsCtSjOi8MtAjAAMki2UOZFC2RpF1Jbc hLXDX5VAgzvDyqh8YN99n5j5sH7Tkx8u1Lej5+WU5b3P7q5qjXvJ7BEJhFhJx3pNdVtQ93ztQ6gLo U69BMOYFxeS/oYYej2IEvwYZVBC9bS8zx47jjjfprs0VghD8U6YHOr9GnBK8Rs2S8Ucc9g6Nf61Qf ep9a/FLo231DbhM6ZD28Hlv7LVKS0Tkq/JSVz2KiRUtpPL/mywNOm+sXGzGheDBYIEJ8e9Z36QXMg giP3jxGAXil2OMKrsAow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZQ2-00433U-Iu; Sat, 31 Dec 2022 10:48:50 +0000 Received: from mail-ej1-x642.google.com ([2a00:1450:4864:20::642]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZPA-0042T4-2t for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 10:47:58 +0000 Received: by mail-ej1-x642.google.com with SMTP id u19so56336437ejm.8 for ; Sat, 31 Dec 2022 02:47:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IcEaICywm+0WRzTCyxMBWQ3K+HlDrikikPFrWzM/DaQ=; b=I8RIy1OktpVsbRpdmWg43bz4+D803jKtzwDbMPvBKSHl6gv9lqEPzvf83PEGNiR4ip BOL6wHstTxnQmvCBlZpt5d5k+RrlgFN8yHeZkUMOBhKX2gjyzxCF6CZx/CwMLwTqE7lX BYVEZc7LX2SORaTEAUwaSZsrJLkmVp3Bfm2qw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IcEaICywm+0WRzTCyxMBWQ3K+HlDrikikPFrWzM/DaQ=; b=o2iX8wyeTfTAg1A4LriabNDISAyKILbRkU44JBas/2moU/l7JGZqGaq4t9DBzKlGSY SpIuiie6LO73Codq/PhC8D2+mWWm0DslWkksnQ05CoK8HLLSeHeykPs8+9pfp1ifUi0g sCaemgYRsTnSASp3fWOnh+XQZ6KY6yRHCAenet2AFEb53ks+TEdvnD7vtu/fgbpSpWF1 Rq3GN3vnlqHhkTrirP+RTSqc6MCpSW/3n/smLK/RzlpLNJwmoRx0wSXC2W/JT8rZooTA omAhKHHeD9B1Uwn3Tyrk6cnciXhjbszXAEiv/iU9tlojI6Pqme7r5ltGPPnoOdeeZhtt kB3w== X-Gm-Message-State: AFqh2kq6DBkjTmiueeQn8ulL+qPggczGZjJaHca/3E3bm1rhVN/RxV5x klvBQb9jOLsfBTV8zXgHu8df0A== X-Google-Smtp-Source: AMrXdXsZ1DnWXF3cwjmhe5cQIwc3pa88nJl+BqujUnRqk6Vxg2ufSDQ/pcYcfQVMlsRYJnlHQfgIOg== X-Received: by 2002:a17:907:8312:b0:7c1:bb4:ea20 with SMTP id mq18-20020a170907831200b007c10bb4ea20mr28492064ejc.71.1672483674014; Sat, 31 Dec 2022 02:47:54 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:53 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 03/11] clk: imx8mn: add gate driver Date: Sat, 31 Dec 2022 11:47:28 +0100 Message-Id: <20221231104736.12635-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_024756_173131_4AB71F17 X-CRM114-Status: GOOD ( 20.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The patch adds support for imx8mn gate clocks to be initialized directly from the device tree. Currently all i.MX gate clocks are initialized by legacy code with hardwired parameters. This approach has generated a proliferation of setup functions with unclear names: git grep "#define imx_clk_hw_gate" drivers/clk/imx/clk.h drivers/clk/imx/clk.h:#define imx_clk_hw_gate(name, parent, reg, shift) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate2(name, parent, reg, shift) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate_dis(name, parent, reg, shift) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate3(name, parent, reg, shift) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate4(name, parent, reg, shift) \ drivers/clk/imx/clk.h:#define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \ So, let's start with this specific clock driver and hope that other variants can be handled in the future, causing the legacy code to be removed. Signed-off-by: Dario Binacchi --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-gate.c | 156 +++++++++++++++++++++++++++++++++++++ 2 files changed, 157 insertions(+) create mode 100644 drivers/clk/imx/clk-gate.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index e8aacb0ee6ac..72e1f08d49dc 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -11,6 +11,7 @@ mxc-clk-objs += clk-divider-gate.o mxc-clk-objs += clk-fixup-div.o mxc-clk-objs += clk-fixup-mux.o mxc-clk-objs += clk-frac-pll.o +mxc-clk-objs += clk-gate.o mxc-clk-objs += clk-gate2.o mxc-clk-objs += clk-gate-93.o mxc-clk-objs += clk-gate-exclusive.o diff --git a/drivers/clk/imx/clk-gate.c b/drivers/clk/imx/clk-gate.c new file mode 100644 index 000000000000..841ff9a37f30 --- /dev/null +++ b/drivers/clk/imx/clk-gate.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Amarula Solutions + * + * Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define to_clk_imx_gate(_hw) container_of(_hw, struct clk_imx_gate, hw) + +struct clk_imx_gate { + struct clk_hw hw; + struct imx_clk_reg reg; + u32 enable_mask; +}; + +static int imx_clk_gate_enable(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + struct imx_clk_reg *reg = &gate->reg; + + return regmap_update_bits(reg->regmap, reg->offset, gate->enable_mask, + gate->enable_mask); +} + +static void imx_clk_gate_disable(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + struct imx_clk_reg *reg = &gate->reg; + + regmap_update_bits(reg->regmap, reg->offset, gate->enable_mask, 0); +} + +static int imx_clk_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + struct imx_clk_reg *reg = &gate->reg; + unsigned int val; + + if (regmap_read(reg->regmap, reg->offset, &val)) + return -EIO; + + return !!(val & gate->enable_mask); +} + +const struct clk_ops imx_clk_gate_ops = { + .enable = &imx_clk_gate_enable, + .disable = &imx_clk_gate_disable, + .is_enabled = &imx_clk_gate_is_enabled, +}; + +static void imx_clk_hw_unregister_gate(struct clk_hw *hw) +{ + struct clk_imx_gate *gate = to_clk_imx_gate(hw); + + clk_hw_unregister(hw); + kfree(gate); +} + +static struct clk_hw *imx_clk_hw_register_gate(struct device_node *node, + const char *name, + unsigned long flags, + struct imx_clk_reg *reg, + u8 enable_bit) +{ + struct clk_parent_data pdata = { .index = 0 }; + struct clk_init_data init = { NULL }; + struct clk_imx_gate *gate; + struct clk_hw *hw; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.ops = &imx_clk_gate_ops; + init.parent_data = &pdata; + init.num_parents = 1; + + memcpy(&gate->reg, reg, sizeof(*reg)); + gate->enable_mask = BIT(enable_bit); + gate->hw.init = &init; + + hw = &gate->hw; + ret = of_clk_hw_register(node, hw); + if (ret) { + kfree(gate); + return ERR_PTR(ret); + } + + return hw; +} + +/** + * of_imx_gate_clk_setup() - Setup function for imx gate clock + * @node: device node for the clock + */ +static void __init of_imx_gate_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct imx_clk_reg reg; + const char *name = node->name; + u8 enable_bit = 0; + u32 val; + + reg.regmap = syscon_regmap_lookup_by_phandle(node, "fsl,anatop"); + if (IS_ERR(reg.regmap)) { + pr_err("missing regmap for %pOFn\n", node); + return; + } + + if (of_property_read_u32_index(node, "fsl,anatop", 1, &val)) { + pr_err("missing register offset for %pOFn\n", node); + return; + } + + reg.offset = val; + + if (!of_property_read_u32(node, "fsl,bit-shift", &val)) + enable_bit = val; + + if (of_clk_get_parent_count(node) != 1) { + pr_err("%pOFn must have 1 parent clock\n", node); + return; + } + + of_property_read_string(node, "clock-output-names", &name); + + hw = imx_clk_hw_register_gate(node, name, 0, ®, enable_bit); + if (IS_ERR(hw)) + return; + + if (of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw)) { + imx_clk_hw_unregister_gate(hw); + return; + } + + pr_debug("name: %s, offset: 0x%x, enable-bit: %d\n", name, reg.offset, + enable_bit); +} +CLK_OF_DECLARE(fsl_imx8mn_gate_clk, "fsl,imx8mn-gate-clock", + of_imx_gate_clk_setup); From patchwork Sat Dec 31 10:47:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB48DC3DA7D for ; Sat, 31 Dec 2022 10:50:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gp2IlhhADLThe4+slAXFUTdiv+d2psi27ee0FrxkYSg=; b=mtFIGvtO5pi1By 52v6rI5OcGechY/ZCOyCq2fAMTpbtpoynvbbRJNQTrPn1PjRg7uka/f0FDGRO/Tu6l5aLgtqp7f6q jY6EJNFet95sXUAwVM1HJnClEnnbakmQ+XPv2LWBRrI6Ehh40FW+6LLjL0lhx8N6R6wATrQmhfDdL NpGh8ZGfAcQBnFPovrdtSP4+xXPQQEQclyeJKAHSFviZKnO1tDgPNdFvdpdmMYbGR5Od6GLuonGqi Xy9fI8P2j4HIXYWJth1qVkAVgjUT+9JO0HuhjrCBo1iZ5SXocRhsUOYUN3XKBcpDdKj8ljGXMkEXb KjExs129Pw+kWz2dgMig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZQm-0043YJ-B0; Sat, 31 Dec 2022 10:49:36 +0000 Received: from mail-ej1-x641.google.com ([2a00:1450:4864:20::641]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZPB-0042Uf-M5 for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 10:48:00 +0000 Received: by mail-ej1-x641.google.com with SMTP id fc4so56330187ejc.12 for ; Sat, 31 Dec 2022 02:47:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hDUNpRYxOH0Qfmue9rixWxBdtGSeAjE61Y6tD2lDkOk=; b=QoTb9Sofi2PodIImz2XhZ7x1F4SpdiPV1LNAYJm6+mKofJETH/cHb7X4bx9pqo+YF7 +h/SU5kc2NKX0+LclRiGQWvZD7zVOa4zJnrY4ylQNtQS/Gu7MFqk5Di3F0ShLZGWe1N7 vIqNErcxKdun0dPyh0En8q9wBsXDhS5bTGki4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hDUNpRYxOH0Qfmue9rixWxBdtGSeAjE61Y6tD2lDkOk=; b=Msgs2WpjgWmxaURhHnpRn/NgCRg+FfzlnB7qFqcorrdAiRogPl5QJUwKjXbfmVrDHr IFFeGqg0t53R2B1U2xs5qgiQsZ0zLrCVJIn0qPK9qA/2X+49gmiBoru28MN1dI3HWX0+ zC5ZNVSM98EQqCdy6U/ZRLSkXB26I+PMI051vjYfrZGpeuP28d4oA8qno9ujK5yzenKd Pch/7VeaPXVR8Yx2wHyU8MLEnU6x0kVU1p7pVuaKuREMYd93Oosn9TDiAxun4Y0tjBzt 2W0Mkp4lmCdy+AauCbLHq6No/nLR7/VeyLMDgV6I9wk0XYefnWAoMNpSfatXMOYEcI1I iYZQ== X-Gm-Message-State: AFqh2kp0T2Mtv/T0YJWEn9vNGaoKmWqYR4Ty6VJCnxG77kGXcniuGef7 rWnQyJc3zZrJBIaq6mKVGJ5AIw== X-Google-Smtp-Source: AMrXdXvV6aev/NHHV6d9ff+t2egnOElgbWjU0DVnAheA4kZcaiUJaWWsvx5Xj5NXU9XW1JUDVZZ5EA== X-Received: by 2002:a17:907:8e93:b0:7bf:3627:df32 with SMTP id tx19-20020a1709078e9300b007bf3627df32mr30498842ejc.75.1672483675879; Sat, 31 Dec 2022 02:47:55 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:55 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 04/11] clk: imx8mn: add mux driver Date: Sat, 31 Dec 2022 11:47:29 +0100 Message-Id: <20221231104736.12635-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_024757_881721_387ADA14 X-CRM114-Status: GOOD ( 23.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The patch adds support for imx8mn mux clocks to be initialized directly from the device tree. Currently all i.MX mux clocks are initialized by legacy code with hardwired parameters. This approach has generated setup functions with unclear names: git grep "#define imx_clk_hw_mux" drivers/clk/imx/clk.h drivers/clk/imx/clk.h:#define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \ drivers/clk/imx/clk.h:#define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \ drivers/clk/imx/clk.h:#define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ drivers/clk/imx/clk.h:#define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \ drivers/clk/imx/clk.h:#define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ So, let's start with this specific clock driver and hope that other variants can be handled in the future, causing the legacy code to be removed. Signed-off-by: Dario Binacchi --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-mux.c | 258 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 259 insertions(+) create mode 100644 drivers/clk/imx/clk-mux.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 72e1f08d49dc..1cffc5bebbe1 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -15,6 +15,7 @@ mxc-clk-objs += clk-gate.o mxc-clk-objs += clk-gate2.o mxc-clk-objs += clk-gate-93.o mxc-clk-objs += clk-gate-exclusive.o +mxc-clk-objs += clk-mux.o mxc-clk-objs += clk-pfd.o mxc-clk-objs += clk-pfdv2.o mxc-clk-objs += clk-pllv1.o diff --git a/drivers/clk/imx/clk-mux.c b/drivers/clk/imx/clk-mux.c new file mode 100644 index 000000000000..426738d25582 --- /dev/null +++ b/drivers/clk/imx/clk-mux.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Amarula Solutions + * + * Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define to_clk_imx_mux(_hw) container_of(_hw, struct clk_imx_mux, hw) + +struct clk_imx_mux { + struct clk_hw hw; + struct imx_clk_reg reg; + u32 mask; + u8 shift; + u8 saved_parent; +}; + +static int imx_clk_mux_write(const struct imx_clk_reg *reg, u32 val) +{ + int ret = 0; + + if (reg->base) { + writel(val, reg->base + reg->offset); + } else if (reg->regmap) { + ret = regmap_write(reg->regmap, reg->offset, val); + } else { + pr_err("memory address not set\n"); + ret = -EIO; + } + + return ret; +} + +static int imx_clk_mux_read(const struct imx_clk_reg *reg, u32 *val) +{ + int ret = 0; + + if (reg->base) { + *val = readl(reg->base + reg->offset); + } else if (reg->regmap) { + ret = regmap_read(reg->regmap, reg->offset, val); + } else { + pr_err("memory address not set\n"); + ret = -EIO; + } + + return ret; +} + +static u8 imx_clk_mux_get_parent(struct clk_hw *hw) +{ + + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + int num_parents = clk_hw_get_num_parents(hw); + unsigned int val; + int ret; + + ret = imx_clk_mux_read(&mux->reg, &val); + if (ret) + return ret; + + val = (val >> mux->shift) && mux->mask; + + if (val >= num_parents) + return -EINVAL; + + return val; +} + +static int imx_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + unsigned int val; + int ret; + + ret = imx_clk_mux_read(&mux->reg, &val); + if (ret) + return ret; + + val &= ~(mux->mask << mux->shift); + val |= index << mux->shift; + return imx_clk_mux_write(&mux->reg, val); +} + +/** + * imx_clk_mux_save_context - Save the parent selcted in the mux + * @hw: pointer struct clk_hw + * + * Save the parent mux value. + */ +static int imx_clk_mux_save_context(struct clk_hw *hw) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + + mux->saved_parent = imx_clk_mux_get_parent(hw); + return 0; +} + +/** + * imx_clk_mux_restore_context - Restore the parent in the mux + * @hw: pointer struct clk_hw + * + * Restore the saved parent mux value. + */ +static void imx_clk_mux_restore_context(struct clk_hw *hw) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + + imx_clk_mux_set_parent(hw, mux->saved_parent); +} + +const struct clk_ops imx_clk_mux_ops = { + .get_parent = imx_clk_mux_get_parent, + .set_parent = imx_clk_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, + .save_context = imx_clk_mux_save_context, + .restore_context = imx_clk_mux_restore_context, +}; + +static void imx_clk_hw_unregister_mux(struct clk_hw *hw) +{ + struct clk_imx_mux *mux = to_clk_imx_mux(hw); + + clk_hw_unregister(hw); + kfree(mux); +} + +static struct clk_hw *imx_clk_hw_register_mux(struct device_node *node, + const char *name, + const char * const *parent_names, + u8 num_parents, + unsigned long flags, + struct imx_clk_reg *reg, u8 shift, + u32 mask) +{ + struct clk_init_data init = { NULL }; + struct clk_imx_mux *mux; + struct clk_hw *hw; + + int ret; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.ops = &imx_clk_mux_ops; + init.parent_names = parent_names; + init.num_parents = num_parents; + + /* struct clk_mux assignments */ + memcpy(&mux->reg, reg, sizeof(*reg)); + mux->hw.init = &init; + + hw = &mux->hw; + ret = of_clk_hw_register(node, hw); + if (ret) { + kfree(mux); + return ERR_PTR(ret); + } + + return hw; +} + +/** + * of_imx_mux_clk_setup() - Setup function for imx mux clock + * @node: device node for the clock + */ +static void __init of_imx_mux_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + unsigned int num_parents; + const char **parent_names; + const char *name = node->name; + struct imx_clk_reg reg = {}; + u32 shift = 0; + u32 flags = CLK_SET_RATE_NO_REPARENT; + u32 val; + u32 mask; + + reg.regmap = syscon_regmap_lookup_by_phandle(node, "fsl,anatop"); + if (!IS_ERR(reg.regmap)) { + if (of_property_read_u32_index(node, "fsl,anatop", 1, &val)) { + pr_err("missing register offset for %pOFn\n", node); + return; + } + + reg.offset = val; + } else { + reg.base = of_iomap(node, 0); + if (IS_ERR(reg.base)) { + pr_err("failed to get register address for %pOFn\n", + node); + return; + } + } + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + pr_err("%pOFn must have parents\n", node); + return; + } + + parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); + if (!parent_names) + return; + + of_clk_parent_fill(node, parent_names, num_parents); + + of_property_read_u32(node, "fsl,bit-shift", &shift); + + if (of_property_read_bool(node, "fsl,is-critical")) + flags |= CLK_IS_CRITICAL; + + if (of_property_read_bool(node, "fsl,ops-parent-enable")) + flags |= CLK_OPS_PARENT_ENABLE; + + if (of_property_read_bool(node, "fsl,set-rate-parent")) + flags |= CLK_SET_RATE_PARENT; + + /* Generate bit-mask based on parent info */ + mask = num_parents - 1; + mask = (1 << fls(mask)) - 1; + + of_property_read_string(node, "clock-output-names", &name); + + hw = imx_clk_hw_register_mux(node, name, parent_names, num_parents, + flags, ®, shift, mask); + if (IS_ERR(hw)) + goto free_parent_names; + + if (of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw)) { + imx_clk_hw_unregister_mux(hw); + goto free_parent_names; + } + + pr_debug("name: %s, offset: 0x%x, shift: %d, mask: 0x%x\n", name, + reg.offset, shift, mask); + +free_parent_names: + kfree(parent_names); +} +CLK_OF_DECLARE(fsl_imx8mn_mux_clk, "fsl,imx8mn-mux-clock", + of_imx_mux_clk_setup); From patchwork Sat Dec 31 10:47:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27331C3DA7A for ; Sat, 31 Dec 2022 10:51:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kFqzAb/jPEM4hrg1ccVb1Tn+1Q/DWMMtqi7ZYA/wS+A=; b=PUoSGM7k89MLyR pR/lxBDIdxd3IJFP9IuS7W6PKRprm4rrOEk2XlmOcIT/CDm/59lQk12lqw0Yh6LilhtRwfTQcQlPZ dUFl+1c6F9fSDcXll4K+v1YjdfZlJYsNp3RBTJpS91+tIJmtrc8nQXs+Z1bZPT9LzRQgC70+Ryc1Y oVJgX1acV5wp1sdH37kyzUwjrYcOjR1GzDuvTcDqk3Gq8XAom0qBAWrxSCTJ3PxSIuPmTcOlikh8I bqHv17PDF+5YVTVf9QjOfcT7Cg51/WHSItHcW3LrJb6jH7tUmBiHs+epaZ6Qo4KTUac3QAAr1frC3 D67pR4Gc6qJa9Di5W2KQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZRS-00442h-HG; Sat, 31 Dec 2022 10:50:19 +0000 Received: from mail-ej1-x641.google.com ([2a00:1450:4864:20::641]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZPC-0042WW-I8 for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 10:48:00 +0000 Received: by mail-ej1-x641.google.com with SMTP id fc4so56330267ejc.12 for ; Sat, 31 Dec 2022 02:47:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d8WEj9/C0OhSqYwiG2nnUMjHUoH+KTqQswi/Eb48WWY=; b=faGsjlnuCzfCPHiRcZ1qw4oPmkoFMcCH2iMe8ETxugAl0liXMqMz8abSOkdc6/49Nv gEDEsi4REBwJBqOHMJx3vaV8ZZhwvU6/yv5aUqtSi3SE7p41uRui3q6yJeWVcq1TTzxs c3E86ljyETMwKYcAqklaVs17D/ctAHEzimSEA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d8WEj9/C0OhSqYwiG2nnUMjHUoH+KTqQswi/Eb48WWY=; b=SuX8MpZ6R2adjfua0qeAGazLJWdDpFALzBiWacrwYEdeOHRpTHTfte3x1cHKQ1bKyN gzYWN7o1EpwaOlosvIizMsGriCPagLKDcSb7CqaJVSIgtcQTlHodhDOWk8mcvq8VmI14 sD4uHqb9bKVesYYD2vpL7Q+SHccy45RsjcIhZQC2F85lZ8z2/6FNJCoTu3aearc9smwt MU8MqfYikHqUstYlX6d4m+PdDkuZPBi/jD51vWNAjLqoVlo7lHCIh/KFZl71847/8+NR O68aNM3rkf4aOadSh2Y0h6E3QiVPSaCNX27Wrn5OtbmsNebZbRU+yio8yOYwjAddVAPi tsWw== X-Gm-Message-State: AFqh2krXXpnQupf/EDZaCptpEkp3eQWjDLT/HsIjjR8Ex/co9e9RXrmd QxyTR8TQ3ergxvFMH1X/bx7jTw== X-Google-Smtp-Source: AMrXdXtQZ5PYyji1oGUrR72dCgZDGXss/dvqbdGt9E4S2rg3dCbMe5ImjH9I9Rna7/6Ly7y+KyLLLA== X-Received: by 2002:a17:907:80cb:b0:7c0:deb1:bb8a with SMTP id io11-20020a17090780cb00b007c0deb1bb8amr35195077ejc.28.1672483677349; Sat, 31 Dec 2022 02:47:57 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:57 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 05/11] clk: imx8mn: add divider driver Date: Sat, 31 Dec 2022 11:47:30 +0100 Message-Id: <20221231104736.12635-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_024758_666833_1C86F2BD X-CRM114-Status: GOOD ( 22.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The patch adds support for imx8mn divider clocks to be initialized directly from the device tree. Currently all i.MX divider clocks are initialized by legacy code with hardwired parameters. So, let's start with this specific clock driver and hope that other variants can be handled in the future, causing the legacy code to be removed. Signed-off-by: Dario Binacchi --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-divider.c | 235 ++++++++++++++++++++++++++++++++++ 2 files changed, 236 insertions(+) create mode 100644 drivers/clk/imx/clk-divider.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 1cffc5bebbe1..0e4337f0a020 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -7,6 +7,7 @@ mxc-clk-objs += clk-composite-8m.o mxc-clk-objs += clk-composite-93.o mxc-clk-objs += clk-fracn-gppll.o mxc-clk-objs += clk-cpu.o +mxc-clk-objs += clk-divider.o mxc-clk-objs += clk-divider-gate.o mxc-clk-objs += clk-fixup-div.o mxc-clk-objs += clk-fixup-mux.o diff --git a/drivers/clk/imx/clk-divider.c b/drivers/clk/imx/clk-divider.c new file mode 100644 index 000000000000..4617aa906de4 --- /dev/null +++ b/drivers/clk/imx/clk-divider.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Amarula Solutions + * + * Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#define to_clk_imx_divider(_hw) container_of(_hw, struct clk_imx_divider, hw) + +struct clk_imx_divider { + struct clk_hw hw; + struct imx_clk_reg reg; + u8 shift; + u8 width; +}; + +static int imx_clk_divider_write(const struct imx_clk_reg *reg, u32 val) +{ + int ret = 0; + + if (reg->base) { + writel(val, reg->base + reg->offset); + } else if (reg->regmap) { + ret = regmap_write(reg->regmap, reg->offset, val); + } else { + pr_err("memory address not set\n"); + ret = -EIO; + } + + return ret; +} + +static int imx_clk_divider_read(const struct imx_clk_reg *reg, u32 *val) +{ + int ret = 0; + + if (reg->base) { + *val = readl(reg->base + reg->offset); + } else if (reg->regmap) { + ret = regmap_read(reg->regmap, reg->offset, val); + } else { + pr_err("memory address not set\n"); + ret = -EIO; + } + + return ret; +} + +static unsigned long imx_clk_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + unsigned int val; + int ret; + + ret = imx_clk_divider_read(÷r->reg, &val); + if (ret) + return 0; + + val >>= divider->shift; + val &= clk_div_mask(divider->width); + + return divider_recalc_rate(hw, parent_rate, val, NULL, 0, + divider->width); +} + +static long imx_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + + return divider_round_rate(hw, rate, prate, NULL, divider->width, 0); +} + +static int imx_clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + + return divider_determine_rate(hw, req, NULL, divider->width, 0); +} + +static int imx_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + unsigned int val; + int div, ret; + + div = divider_get_val(rate, parent_rate, NULL, divider->width, 0); + if (div < 0) + return div; + + ret = imx_clk_divider_read(÷r->reg, &val); + if (ret) + return ret; + + val &= ~(clk_div_mask(divider->width) << divider->shift); + val |= div << divider->shift; + return imx_clk_divider_write(÷r->reg, val); +} + +const struct clk_ops imx_clk_divider_ops = { + .recalc_rate = imx_clk_divider_recalc_rate, + .round_rate = imx_clk_divider_round_rate, + .determine_rate = imx_clk_divider_determine_rate, + .set_rate = imx_clk_divider_set_rate, +}; + +static void imx_clk_hw_unregister_divider(struct clk_hw *hw) +{ + struct clk_imx_divider *divider = to_clk_imx_divider(hw); + + clk_hw_unregister(hw); + kfree(divider); +} + +static struct clk_hw *imx_clk_hw_register_divider(struct device_node *node, + const char *name, + unsigned long flags, + struct imx_clk_reg *reg, + u8 shift, u8 width) +{ + struct clk_parent_data pdata = { .index = 0 }; + struct clk_init_data init = { NULL }; + struct clk_imx_divider *divider; + struct clk_hw *hw; + int ret; + + divider = kzalloc(sizeof(*divider), GFP_KERNEL); + if (!divider) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.flags = flags; + init.ops = &imx_clk_divider_ops; + init.parent_data = &pdata; + init.num_parents = 1; + + memcpy(÷r->reg, reg, sizeof(*reg)); + divider->shift = shift; + divider->width = width; + divider->hw.init = &init; + + hw = ÷r->hw; + ret = of_clk_hw_register(node, hw); + if (ret) { + kfree(divider); + return ERR_PTR(ret); + } + + return hw; +} + +/** + * of_imx_divider_clk_setup() - Setup function for imx gate clock + * @node: device node for the clock + */ +static void __init of_imx_divider_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct imx_clk_reg reg = {}; + const char *name = node->name; + u8 shift = 0; + u8 width; + u32 flags = 0; + u32 val; + + reg.regmap = syscon_regmap_lookup_by_phandle(node, "fsl,anatop"); + if (!IS_ERR(reg.regmap)) { + if (of_property_read_u32_index(node, "fsl,anatop", 1, &val)) { + pr_err("missing register offset for %pOFn\n", node); + return; + } + + reg.offset = val; + } else { + reg.base = of_iomap(node, 0); + if (IS_ERR(reg.base)) { + pr_err("failed to get register address for %pOFn\n", + node); + return; + } + } + + if (!of_property_read_u32(node, "fsl,bit-shift", &val)) + shift = val; + + if (of_property_read_u32(node, "fsl,width", &val)) { + pr_err("missing width for %pOFn\n", node); + return; + + } + + width = val; + + if (of_property_read_bool(node, "fsl,ops-parent-enable")) + flags |= CLK_OPS_PARENT_ENABLE; + + if (of_property_read_bool(node, "fsl,set-rate-parent")) + flags |= CLK_SET_RATE_PARENT; + + if (of_clk_get_parent_count(node) != 1) { + pr_err("%pOFn must have 1 parent clock\n", node); + return; + } + + of_property_read_string(node, "clock-output-names", &name); + + hw = imx_clk_hw_register_divider(node, name, flags, ®, shift, width); + if (IS_ERR(hw)) + return; + + if (of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw)) { + imx_clk_hw_unregister_divider(hw); + return; + } + + pr_debug("name: %s, offset: 0x%x, shift: %d, width: %d\n", name, + reg.offset, shift, width); +} +CLK_OF_DECLARE(fsl_imx8mn_divider_clk, "fsl,imx8mn-divider-clock", + of_imx_divider_clk_setup); From patchwork Sat Dec 31 10:47:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE6E2C3DA7D for ; Sat, 31 Dec 2022 10:52:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Vkci5gZibvlo4MC3IIcpGW2pvJF/kQ/kqX8FetxSaAA=; b=PNKbvLYdt549pC cct6oTXNuWJi3/IvXsEtsPlbdCkeM383OL8OPSfhb6MB8WXRYqFxVr/1fDn+psmlObBFQ76rD2OYd GGoz574eN/qa+j5/KgKjrcbf8OOUPYY+eolVvuHODLO0kcDoc4Rv8Mf0AL0ihOHX1CDrJKmYmQRZG eV5eKXi1vYe/bvO9YmJzm8LTAnvxIy8Lw1DCEiEn1vr2NFVeHYvpoMYHopI8fZ09AfD1aB8uZII92 mXDaYz6FheJ7qaKj6giEkvtQSSG+Py57ZmnV57VOYCVBPjLKIKxBtGiAHjOR28pSScAfFZrfkX4fM XmvMo8epbTkk/K6FHhBA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZSE-0044cD-Ds; Sat, 31 Dec 2022 10:51:07 +0000 Received: from mail-ej1-x642.google.com ([2a00:1450:4864:20::642]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZPD-0042T4-Dg for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 10:48:02 +0000 Received: by mail-ej1-x642.google.com with SMTP id u19so56336656ejm.8 for ; Sat, 31 Dec 2022 02:47:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1iy2WsPMUIoNX6u9WQ/l0SQoi0Lk5nxPuSrhDYO0lTs=; b=emsOw7kgepZGvr7cmVhAuUy1pxmvNgy5JGtwO2lVuU9cFSxhuic4+z6gUFM2dHW0F5 AUUCTjPEeCS8DPLlzCRsYQwt+FNIpWjUxAO6LHkIhnJ8OtmlV5xAn0tGZLY7nX2GHzim 5twlC9SftCNRcJP/3B55gTQp6QITxA8NgNov0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1iy2WsPMUIoNX6u9WQ/l0SQoi0Lk5nxPuSrhDYO0lTs=; b=PDlPUsbU+AqloS4tCDTbqiIr1wF5y+dpbzfSA+VmtiFQcft59DIK1Xx9S1lVBt1YkU D6bGIKVj1SW1gJ3+QsCDYkveYMjjsvHwq4cCXkGpFHfSAbjmAn2d/SCvX+U4Y5jbUPL/ Mg7QIn86lkYR+Glc412K2kdROnJU7yuz3r622E+6iXDF7miRkBG57dS3GMMQlTzdbx03 fZqlQcyUxAyU5Uwbz+pflKQbxwFFQ4GNILbzFjf1uK2xvDXouip1MYuQkEV4+CONpP85 4rQCLOK7QPJwAOqA0bkKGHC5uAKeZBIxk8p1KDEyFY0lQ8xggaUN2GidsNdumXBwVBaC LPTw== X-Gm-Message-State: AFqh2kqAKXq8yzx0cV5TE3mJJDcN3+xcuaCm1AUhQ2r4siJ/NDXqpVpi paU8VeXDDnXxhb5gl5XdeDVBUg== X-Google-Smtp-Source: AMrXdXv8ZevdJwLLV7gy7GY2QLqAScmfeBn3M6bAsFEbIKip0Zwmr9t4Hv/sdHYZcVT4R3xh8pMl1g== X-Received: by 2002:a17:906:85d9:b0:842:1627:77b4 with SMTP id i25-20020a17090685d900b00842162777b4mr29133602ejy.3.1672483678925; Sat, 31 Dec 2022 02:47:58 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:47:58 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 06/11] clk: imx: pll14xx: add device tree support Date: Sat, 31 Dec 2022 11:47:31 +0100 Message-Id: <20221231104736.12635-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_024759_568281_9EC765BB X-CRM114-Status: GOOD ( 24.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-pll14xx.c | 220 +++++++++++++++++++++++++++------- 1 file changed, 176 insertions(+), 44 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 828336873a98..6503005b885a 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -12,6 +12,10 @@ #include #include #include +#include +#include +#include +#include #include #include @@ -36,7 +40,9 @@ struct clk_pll14xx { struct clk_hw hw; - void __iomem *base; + struct imx_clk_reg gnrl_ctl; + struct imx_clk_reg div_ctl0; + struct imx_clk_reg div_ctl1; enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; @@ -90,6 +96,30 @@ struct imx_pll14xx_clk imx_1416x_pll = { }; EXPORT_SYMBOL_GPL(imx_1416x_pll); +static void imx_pll14xx_writel(u32 val, const struct imx_clk_reg *reg) +{ + if (reg->base) + writel_relaxed(val, reg->base + reg->offset); + else if (reg->regmap) + regmap_write(reg->regmap, reg->offset, val); + else + pr_err("%s: memory address not set\n", __func__); +} + +static u32 imx_pll14xx_readl(const struct imx_clk_reg *reg) +{ + u32 val = 0; + + if (reg->base) + val = readl_relaxed(reg->base + reg->offset); + else if (reg->regmap) + regmap_read(reg->regmap, reg->offset, &val); + else + pr_err("%s: memory address not set\n", __func__); + + return val; +} + static const struct imx_pll14xx_rate_table *imx_get_pll_settings( struct clk_pll14xx *pll, unsigned long rate) { @@ -161,11 +191,11 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat return; } - pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + pll_div_ctl0 = imx_pll14xx_readl(&pll->div_ctl0); mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); - pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + pll_div_ctl1 = imx_pll14xx_readl(&pll->div_ctl1); /* Then see if we can get the desired rate by only adjusting kdiv (glitch free) */ rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate); @@ -249,13 +279,13 @@ static unsigned long clk_pll14xx_recalc_rate(struct clk_hw *hw, struct clk_pll14xx *pll = to_clk_pll14xx(hw); u32 mdiv, pdiv, sdiv, kdiv, pll_div_ctl0, pll_div_ctl1; - pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + pll_div_ctl0 = imx_pll14xx_readl(&pll->div_ctl0); mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); if (pll->type == PLL_1443X) { - pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); + pll_div_ctl1 = imx_pll14xx_readl(&pll->div_ctl1); kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1); } else { kdiv = 0; @@ -277,10 +307,22 @@ static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *ra static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll) { + struct imx_clk_reg *reg = &pll->gnrl_ctl; u32 val; - return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0, - LOCK_TIMEOUT_US); + if (reg->base) + return readl_poll_timeout(reg->base + reg->offset, val, + val & LOCK_STATUS, 0, + LOCK_TIMEOUT_US); + + if (reg->regmap) + return regmap_read_poll_timeout(reg->regmap, reg->offset, val, + val & LOCK_STATUS, 0, + LOCK_TIMEOUT_US); + + pr_err("%s: memory address not set\n", __func__); + + return -EIO; } static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, @@ -298,32 +340,32 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - tmp = readl_relaxed(pll->base + DIV_CTL0); + tmp = imx_pll14xx_readl(&pll->div_ctl0); if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~SDIV_MASK; tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(tmp, pll->base + DIV_CTL0); + imx_pll14xx_writel(tmp, &pll->div_ctl0); return 0; } /* Bypass clock and set lock to pll output lock */ - tmp = readl_relaxed(pll->base + GNRL_CTL); + tmp = imx_pll14xx_readl(&pll->gnrl_ctl); tmp |= LOCK_SEL_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); /* Enable RST */ tmp &= ~RST_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); /* Enable BYPASS */ tmp |= BYPASS_MASK; - writel(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) | FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(div_val, pll->base + DIV_CTL0); + imx_pll14xx_writel(div_val, &pll->div_ctl0); /* * According to SPEC, t3 - t2 need to be greater than @@ -335,7 +377,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ tmp |= RST_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); /* Wait Lock */ ret = clk_pll14xx_wait_lock(pll); @@ -344,7 +386,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ tmp &= ~BYPASS_MASK; - writel_relaxed(tmp, pll->base + GNRL_CTL); + imx_pll14xx_writel(tmp, &pll->gnrl_ctl); return 0; } @@ -359,35 +401,35 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, imx_pll14xx_calc_settings(pll, drate, prate, &rate); - div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + div_ctl0 = imx_pll14xx_readl(&pll->div_ctl0); if (!clk_pll14xx_mp_change(&rate, div_ctl0)) { /* only sdiv and/or kdiv changed - no need to RESET PLL */ div_ctl0 &= ~SDIV_MASK; div_ctl0 |= FIELD_PREP(SDIV_MASK, rate.sdiv); - writel_relaxed(div_ctl0, pll->base + DIV_CTL0); + imx_pll14xx_writel(div_ctl0, &pll->div_ctl0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), - pll->base + DIV_CTL1); + imx_pll14xx_writel(FIELD_PREP(KDIV_MASK, rate.kdiv), + &pll->div_ctl1); return 0; } /* Enable RST */ - gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL); + gnrl_ctl = imx_pll14xx_readl(&pll->gnrl_ctl); gnrl_ctl &= ~RST_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); /* Enable BYPASS */ gnrl_ctl |= BYPASS_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); div_ctl0 = FIELD_PREP(MDIV_MASK, rate.mdiv) | FIELD_PREP(PDIV_MASK, rate.pdiv) | FIELD_PREP(SDIV_MASK, rate.sdiv); - writel_relaxed(div_ctl0, pll->base + DIV_CTL0); + imx_pll14xx_writel(div_ctl0, &pll->div_ctl0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + imx_pll14xx_writel(FIELD_PREP(KDIV_MASK, rate.kdiv), &pll->div_ctl1); /* * According to SPEC, t3 - t2 need to be greater than @@ -399,7 +441,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Disable RST */ gnrl_ctl |= RST_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); /* Wait Lock*/ ret = clk_pll14xx_wait_lock(pll); @@ -408,7 +450,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, /* Bypass */ gnrl_ctl &= ~BYPASS_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + imx_pll14xx_writel(gnrl_ctl, &pll->gnrl_ctl); return 0; } @@ -423,20 +465,20 @@ static int clk_pll14xx_prepare(struct clk_hw *hw) * RESETB = 1 from 0, PLL starts its normal * operation after lock time */ - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); if (val & RST_MASK) return 0; val |= BYPASS_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); val |= RST_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); ret = clk_pll14xx_wait_lock(pll); if (ret) return ret; val &= ~BYPASS_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); return 0; } @@ -446,7 +488,7 @@ static int clk_pll14xx_is_prepared(struct clk_hw *hw) struct clk_pll14xx *pll = to_clk_pll14xx(hw); u32 val; - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); return (val & RST_MASK) ? 1 : 0; } @@ -460,9 +502,9 @@ static void clk_pll14xx_unprepare(struct clk_hw *hw) * Set RST to 0, power down mode is enabled and * every digital block is reset */ - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); val &= ~RST_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); } static const struct clk_ops clk_pll1416x_ops = { @@ -487,13 +529,24 @@ static const struct clk_ops clk_pll1443x_ops = { .set_rate = clk_pll1443x_set_rate, }; -struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, - const char *parent_name, void __iomem *base, - const struct imx_pll14xx_clk *pll_clk) +static void imx_clk_hw_unregister_pll14xx(struct clk_hw *hw) { + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + + clk_hw_unregister(hw); + kfree(pll); +} + +static struct clk_hw * +imx_clk_hw_register_pll14xx(struct device_node *node, const char *name, + const char *parent_name, + struct imx_clk_reg *iomap, + const struct imx_pll14xx_clk *pll_clk) +{ + struct clk_parent_data pdata = { .index = 0 }; + struct clk_init_data init = { NULL }; struct clk_pll14xx *pll; struct clk_hw *hw; - struct clk_init_data init; int ret; u32 val; @@ -503,7 +556,8 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, init.name = name; init.flags = pll_clk->flags; - init.parent_names = &parent_name; + init.parent_names = parent_name ? &parent_name : NULL; + init.parent_data = &pdata; init.num_parents = 1; switch (pll_clk->type) { @@ -522,19 +576,24 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, return ERR_PTR(-EINVAL); } - pll->base = base; + memcpy(&pll->gnrl_ctl, iomap, sizeof(*iomap)); + pll->gnrl_ctl.offset += GNRL_CTL; + memcpy(&pll->div_ctl0, iomap, sizeof(*iomap)); + pll->div_ctl0.offset += DIV_CTL0; + memcpy(&pll->div_ctl1, iomap, sizeof(*iomap)); + pll->div_ctl1.offset += DIV_CTL1; + pll->hw.init = &init; pll->type = pll_clk->type; pll->rate_table = pll_clk->rate_table; pll->rate_count = pll_clk->rate_count; - val = readl_relaxed(pll->base + GNRL_CTL); + val = imx_pll14xx_readl(&pll->gnrl_ctl); val &= ~BYPASS_MASK; - writel_relaxed(val, pll->base + GNRL_CTL); + imx_pll14xx_writel(val, &pll->gnrl_ctl); hw = &pll->hw; - - ret = clk_hw_register(dev, hw); + ret = of_clk_hw_register(node, hw); if (ret) { pr_err("failed to register pll %s %d\n", name, ret); kfree(pll); @@ -543,4 +602,77 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, return hw; } + +struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, + const char *parent_name, void __iomem *base, + const struct imx_pll14xx_clk *pll_clk) +{ + struct imx_clk_reg iomap = {}; + + iomap.base = base; + return imx_clk_hw_register_pll14xx(dev_of_node(dev), name, parent_name, + &iomap, pll_clk); +} EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +/** + * of_imx_pll14xx_clk_setup() - Setup function for imx pll14xx clock + * @node: device node for the clock + */ +static void __init of_imx_pll14xx_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct imx_clk_reg iomap = {}; + const char *name = node->name; + const struct imx_pll14xx_clk *pll_clk; + const char *pll_type; + u32 val; + + iomap.regmap = syscon_regmap_lookup_by_phandle(node, "fsl,anatop"); + if (IS_ERR(iomap.regmap)) { + pr_err("missing regmap for %pOFn\n", node); + return; + } + + if (of_property_read_u32_index(node, "fsl,anatop", 1, &val)) { + pr_err("missing register offset for %pOFn\n", node); + return; + } + + iomap.offset = val; + if (of_clk_get_parent_count(node) != 1) { + pr_err("%pOFn must have 1 parent clock\n", node); + return; + } + + of_property_read_string(node, "clock-output-names", &name); + if (of_property_read_string(node, "fsl,type", &pll_type)) { + pr_err("missing 'fsl,type' for %pOFn\n", node); + return; + } + + if (!strcmp(pll_type, "1443x")) { + if (of_property_read_bool(node, "fsl,get-rate-nocache")) + pll_clk = &imx_1443x_dram_pll; + else + pll_clk = &imx_1443x_pll; + } else if (!strcmp(pll_type, "1416x")) { + pll_clk = &imx_1416x_pll; + } else { + pr_err("failed to get pll clock for %pOFn\n", node); + return; + } + + hw = imx_clk_hw_register_pll14xx(node, name, NULL, &iomap, pll_clk); + if (IS_ERR(hw)) + return; + + if (of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw)) { + imx_clk_hw_unregister_pll14xx(hw); + return; + } + + pr_debug("name: %s, offset: 0x%x, pll_type: %s\n", name, iomap.offset, + pll_type); +} +CLK_OF_DECLARE(fsl_pll14xx_clk, "fsl,pll14xx-clock", of_imx_pll14xx_clk_setup); From patchwork Sat Dec 31 10:47:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECF19C3DA7D for ; Sat, 31 Dec 2022 10:53:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6cBbGxNEsm8iZGnJJbWdbK7HDJ5MGQy5dmmYstuaq1A=; b=y2/y6mul7KmYBi kn6mwGcX4bJZofqGxeVVXCHX9vBMJbeAkd90Akty1yCJD72eC+eWkYs2NIeMVCWRHkuIqCqfSJwSG stPZy68shGvntwsghaK3OJpbtkMNN2WoDFpst3JLasE6Ool8mNCH8CIJioI7CGL+k6Um+hEZuBqZ2 kgQNGjnJ7djd2ZKYpxhyfQbvlEyLuxKcexOfyvDwjp+uo3EC+mCqg5wAEAkYVspO7DxlXPAjkBmVn sl5U10/WhUwvt10ObqA9Q7L6URSVHhrnZYdaD0Coy+U030/JKbDSJsT80GIRkScr/d66ZKKHuHCkS yNVySmzTxJBWriN9fKxg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZTE-0045Ld-AW; Sat, 31 Dec 2022 10:52:09 +0000 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZPG-0042ZO-Rp for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 10:48:04 +0000 Received: by mail-ed1-x533.google.com with SMTP id m21so33549673edc.3 for ; Sat, 31 Dec 2022 02:48:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lNTG6siRVvvtXsy+GAwDHHb+RGsPbfwrQN+hKdCck/s=; b=h6suuaQS77Q7uXcGE0tPIOZR6gBZPftHQtxsZiWvYKzvoFpBLYY0mo7cbC6csHNPoF 3NaUYsD6S+p2Q+FZCE0OaBn+CWnPrJ7vDGapfHiNJKYuCUAnvARnT+N8olSAMNF1QW7K O20zyLdNpY08v8qurYDkKtekosozQzLZuBqX0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lNTG6siRVvvtXsy+GAwDHHb+RGsPbfwrQN+hKdCck/s=; b=Agr5gTRikfkoYk2fhSzNHz50EQzyhqUgywCNrIASzAx1QNOC7GI5N6wJjja1jhjZXW YErlYupY/6K1mZfST63hjDueE6DhRi4qMGxgzya5Cyt0xk65xoDczZlmKTwMH6dY6vD1 JqjVpTkgBpEVTdVWZL1wJGtBLhH67qHeaAo+87Ov9BrfzTw7GmWaXbLzxt/rHZG2xhd+ QRbU2uP+YCHSB+s0MNxibFpv2Jksdx70E/SIJbfrzFqaUJCt9+xj2+DWXjvQmOK10bUS D36oPfXo9PZEGAGrfK4yx/UHIJ/unVMswMKEW6sXt7nrFULDjIm0bQT866R17PjWu/Gr GApQ== X-Gm-Message-State: AFqh2kqDQCeJ9s8O46J3N4a0cFtz6blg3umuW+o4J1MjvMfg3w3hU1DR uG9M03xX3TQUXMVAWClQ+SI+rg== X-Google-Smtp-Source: AMrXdXuM12mBzocEhuMcUaHxAAUx1SH1UDETPNtrsDAD8zfD6TsTHXBUEAZtLnOMm8WCM7+fJN+OCQ== X-Received: by 2002:a05:6402:1854:b0:483:6039:9801 with SMTP id v20-20020a056402185400b0048360399801mr22324086edy.22.1672483680664; Sat, 31 Dec 2022 02:48:00 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:00 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 07/11] clk: imx: composite-8m: add device tree support Date: Sat, 31 Dec 2022 11:47:32 +0100 Message-Id: <20221231104736.12635-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_024803_092848_6B4153FB X-CRM114-Status: GOOD ( 14.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-composite-8m.c | 83 ++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index cbf0d7955a00..8c945d180318 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include "clk.h" @@ -25,6 +27,9 @@ #define PCG_CGC_SHIFT 28 +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt, __func__ + static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -250,3 +255,81 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, return ERR_CAST(hw); } EXPORT_SYMBOL_GPL(__imx8m_clk_hw_composite); + +static void __init _of_imx_composite_clk_setup(struct device_node *node, + u32 type) +{ + void __iomem *reg; + struct clk_hw *hw; + const char *name = node->name; + unsigned int num_parents; + const char **parent_names; + unsigned long flags = IMX_COMPOSITE_CLK_FLAGS_DEFAULT; + + reg = of_iomap(node, 0); + if (IS_ERR(reg)) { + pr_err("failed to get reg address for %pOFn\n", node); + return; + } + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + pr_err("%pOFn must have parents\n", node); + return; + } + + parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); + if (!parent_names) + return; + + of_clk_parent_fill(node, parent_names, num_parents); + of_property_read_string(node, "clock-output-names", &name); + + if (of_property_read_bool(node, "fsl,get-rate-nocache")) + flags |= CLK_GET_RATE_NOCACHE; + + if (of_property_read_bool(node, "fsl,is-critical")) + flags |= CLK_IS_CRITICAL; + + hw = __imx8m_clk_hw_composite(name, parent_names, num_parents, reg, + type, flags); + if (!IS_ERR(hw)) + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + kfree(parent_names); +} + +/** + * of_imx_composite_clk_setup() - Setup function for imx composite clock + * @node: device node for the clock + */ +void __init of_imx_composite_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_CORE); +} +CLK_OF_DECLARE(fsl_composite_8m_clk, "fsl,imx8m-composite-clock", + of_imx_composite_clk_setup); + +/** + * of_imx_composite_bus_clk_setup() - Setup function for imx composite clock + * @node: device node for the clock + */ +void __init of_imx_composite_bus_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_BUS); +} +CLK_OF_DECLARE(fsl_composite_bus_8m_clk, "fsl,imx8m-composite-bus-clock", + of_imx_composite_bus_clk_setup); + +/** + * of_imx_composite_fw_managed_clk_setup() - Setup function for imx + * composite fw managed clock + * @node: device node for the clock + */ +void __init of_imx_composite_fw_managed_clk_setup(struct device_node *node) +{ + _of_imx_composite_clk_setup(node, IMX_COMPOSITE_FW_MANAGED); +} +CLK_OF_DECLARE(fsl_composite_fw_managed_8m_clk, + "fsl,imx8m-composite-fw-managed-clock", + of_imx_composite_fw_managed_clk_setup); From patchwork Sat Dec 31 10:47:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B831C3DA7A for ; Sat, 31 Dec 2022 10:54:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mZCi/GlCIKbjxBIKg2UWWj6V2xr1wNGbMOSh90oFY3c=; b=XUhvUgZUTgz4H9 Pn60kDMNYiad7T7cDzfEdoyvHJ5OVrBkuRaJvyzVGPyt2kitC7XnmyOUi2/TSgNQ1F/cv7B1nE/Dj iIgo+kTcgZrTH9NL69lZAAGkDftIIpKGWsk9x1jgIEM9dNIxLf/DNSDEpw32vSyrqb/7DYMybxNEo +J7QGqZigtyzezqe2TE7izT4tWTQFAyI+L6cgVHlEj3mpBfmxHgDA3EawD8mAEAHsWic/JYxoqdRh I4eF++qaLCg+uQxvo4cF0zlcI11pGOTq+nsdgOzd5AE4j+X+pfzj43SiiANumyvKpsS722TOzrag8 wZ2Vv/Gl5kagqoK3pn3Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZUD-0045vR-4k; Sat, 31 Dec 2022 10:53:09 +0000 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZPH-0042au-Ue for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 10:48:07 +0000 Received: by mail-ej1-x631.google.com with SMTP id tz12so56380748ejc.9 for ; Sat, 31 Dec 2022 02:48:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2nmJF3bEeRxJYrFQdgL7c1Fy/VFwyyC/ez/jfHGKmTk=; b=EIHtuJl7Px5jzWvOr0qcRutxwgf6dnRNYLj1qy6cx/ApezQRL7YwyNkTmofDy153pm WUyMaeEYCyXqFkvC13Jq7KilR7OTFSYZqtQCj+EEoZUdG6tHVy8Gn/pzaZUiKv9CihUW tEAOczd8T+FnFe18k9Ndsdg31yarDkD8InlzQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2nmJF3bEeRxJYrFQdgL7c1Fy/VFwyyC/ez/jfHGKmTk=; b=keAXRihKXMLmDDFvvecoR2gWtMJTMO8jbG54mU4QuhUXSgGCuLavNiu7KtY/Y3t6m5 +mBqke7kHM1cejnYmO4xNgpVl1980fV7WnXyQcmhTzkv+JxWNZ1MA4ihi6/QzDWEj0lG YXM0+D1qZeqhTtJOvuBUSOOcRVt0yQji3hSNABnC1gHBGMxSmMSlCjjcnQ/kjXJzsQFJ 58SsVHy8gC2/xXHgK72GrPXzrEvSyzsTLHt3Gcq3fREadt3ZATpJyIetrr1QUiNUAUNF D/5Ng8kCLj/MNP+vdlt2FzIpjdwS9izrVP6E6I0GA21dMAUqqGxhuBp6qf8Cg78A0s3x xYZg== X-Gm-Message-State: AFqh2kpa5CuGh30ZaJaMda7us8nZ5JKgMSlVIIJ93KSRZVfj9meVkfeY WW6ipZrg3ZR2czBBAglO10eMYA== X-Google-Smtp-Source: AMrXdXt6n3gAYNVwmlTeUuEyNQjyNuRze77+SuBFtaIQ4NFBo1ogkhxz0e9wcjVJCxQcH9XfPsY5nA== X-Received: by 2002:a17:907:8c08:b0:7c1:65d1:c4ca with SMTP id ta8-20020a1709078c0800b007c165d1c4camr10045321ejc.33.1672483682160; Sat, 31 Dec 2022 02:48:02 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:01 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 08/11] clk: imx: gate2: add device tree support Date: Sat, 31 Dec 2022 11:47:33 +0100 Message-Id: <20221231104736.12635-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_024805_434131_3F973C61 X-CRM114-Status: GOOD ( 16.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-gate2.c | 86 +++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index f16c4019f402..b28150bf1ff6 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -12,9 +12,26 @@ #include #include #include +#include +#include #include #include "clk.h" +#define CLK_GATE2_CGR_DISABLED 0 +#define CLK_GATE2_CGR_RUN 1 +#define CLK_GATE2_CGR_RUN_WAIT 2 +#define CLK_GATE2_CGR_RUN_WAIT_STOP 3 +#define CLK_GATE2_CGR_MASK 3 + +#define CLK_GATE2_MAX_GROUPS 16 + +struct clk_gate2_group { + const char *name; + unsigned int share_count; +}; + +static struct clk_gate2_group clk_gate2_groups[CLK_GATE2_MAX_GROUPS]; + /** * DOC: basic gateable clock which can gate and ungate its output * @@ -175,3 +192,72 @@ struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, return hw; } EXPORT_SYMBOL_GPL(clk_hw_register_gate2); + +/** + * of_imx_gate2_clk_setup() - Setup function for imx low power gate + * clock + * @node: device node for the clock + */ +static void __init of_imx_gate2_clk_setup(struct device_node *node) +{ + void __iomem *reg; + u8 i, bit_idx = 0; + u8 cgr_val = CLK_GATE2_CGR_RUN_WAIT_STOP; + u8 cgr_mask = CLK_GATE2_CGR_MASK; + unsigned long flags = CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT; + u8 gate2_flags = 0; + unsigned int *share_count = NULL; + const char *name = node->name, *parent_name; + const char *str; + struct clk_hw *hw; + u32 val; + + reg = of_iomap(node, 0); + if (IS_ERR(reg)) { + pr_err("failed to get reg address for %pOFn\n", node); + return; + } + + if (!of_property_read_u32(node, "fsl,bit-shift", &val)) + bit_idx = val; + + if (of_clk_get_parent_count(node) != 1) { + pr_err("%pOFn must have 1 parent clock\n", node); + return; + } + + if (!of_property_read_string(node, "sharing-group", &str)) { + for (i = 0; clk_gate2_groups[i].name && + i < ARRAY_SIZE(clk_gate2_groups); i++) { + if (!strcmp(clk_gate2_groups[i].name, str)) { + share_count = &clk_gate2_groups[i].share_count; + break; + } + } + + if (i == ARRAY_SIZE(clk_gate2_groups)) { + pr_err("failed to get shared count for %pOFn\n", node); + return; + } + + if (!share_count) { + clk_gate2_groups[i].name = + kstrdup_const(str, GFP_KERNEL); + share_count = &clk_gate2_groups[i].share_count; + } + } + + parent_name = of_clk_get_parent_name(node, 0); + of_property_read_string(node, "clock-output-names", &name); + + hw = clk_hw_register_gate2(NULL, name, parent_name, flags, reg, bit_idx, + cgr_val, cgr_mask, gate2_flags, + &imx_ccm_lock, share_count); + if (!IS_ERR(hw)) + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + pr_debug("name: %s, parent: %s, enable-bit: %d, flags: 0x%lx, gate2_flags: 0x%x\n", + name, parent_name, bit_idx, flags, gate2_flags); +} +CLK_OF_DECLARE(fsl_imx8mn_gate2_clk, "fsl,imx8mn-low-power-gate-clock", + of_imx_gate2_clk_setup); From patchwork Sat Dec 31 10:47:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D55DC3DA7A for ; Sat, 31 Dec 2022 10:55:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nHGQdEmZRLZNPl4PMFBwib31UA5XCL72PkizqlEilZ4=; b=o+FcibRBgmkjuH WSXbvlClSY2W3+rOXcPWW9VnzM+cIChyGk6iEJoMNMMmphXbA2UdsMfw7ZrKcxhOnSDgx/3ezXN19 RrWnEoSkIC+ScdXM4joK8JsdeGeX6h3ejgnoPM32iQSyJGR/BWEIt9uc4JzqrakxjR5Tsbk7ZBK9k RQTSuzKjQa5IkOWItEUk24tIXIIeSuk2jae12fqnX1jMoiRh1elcXDaigDP0yDi2+BoQSE5lc3ynC FYNgtTg8ggJK2V6YDQnmk0N/qDORieYkx+V7iRhmbUirbyALiHoJvOpiC7pDQB3azGuEoTVsjxhiD tso8LHmZiE/sgxJRJQuw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZVC-0046Qe-6m; Sat, 31 Dec 2022 10:54:11 +0000 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZPK-0042bX-FO for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 10:48:08 +0000 Received: by mail-ej1-x62e.google.com with SMTP id jo4so56397024ejb.7 for ; Sat, 31 Dec 2022 02:48:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UYCjumJKIVpNgaprHBc6yiaBNx3uDiRwwnz6NjNAOKQ=; b=d5Oo3F4xNBaZibu3GdHQEpk4dkNY4Pe366qqIdofJdaLCS+j6pM2KVNUMIuD5drl9r K8X2cHKHQQ+AiqT3GelAdpGQuM+r19m0Sjwswemw88PZ1BvN/N5IqaS2xTE9ynUfvZXZ c2joIXIGAeXGqiD24N+PjjWBoTshwF/8Q85Q8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UYCjumJKIVpNgaprHBc6yiaBNx3uDiRwwnz6NjNAOKQ=; b=WQSrPh4U5XHWOo6x8hUcCQWihw4qB71URc2jn/sxpk3BGbONGTDwIZext9pdoraqOU 7wvoc0CRAAxA/86WbK9unLS6HRdVeHFa8ia7xZCueBTGkiy/KxdH7+xYtRSxBVdcudsQ jsZvnkBQwDqC81ElHh+uiJxisJiOpc85mC68od99a97ObXZzz8ZKg//YK+458P1ggh/B TWsIAGz6MCMNwftNpUowSu14TI9DWX2rR5MB2YXLHtSREVRbkZC2gKMm6qC06ztEfSQc +i2vynifmmzkDQWIgQzXVzhertK3e2yiPbosQW1AAj4G8uC2X9w/FMno+QLE/nZX7DkA 6ADQ== X-Gm-Message-State: AFqh2kroWgvrGycPpOhtrFEVZqnGriNnVr6syqymj7rqRSNjWtTk6iyB tqEr8mwaOUkXSi74ewrTckxElw== X-Google-Smtp-Source: AMrXdXtFkf58R6L2JoTSx+H966u4VmYCHQHiNSic8sWnTUPLX+LR1HTP5V2dYJh1wIFNGVun0uh00g== X-Received: by 2002:a17:907:6f19:b0:818:3ef8:f2fc with SMTP id sy25-20020a1709076f1900b008183ef8f2fcmr28135996ejc.5.1672483684723; Sat, 31 Dec 2022 02:48:04 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:04 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 09/11] clk: imx: cpu: add device tree support Date: Sat, 31 Dec 2022 11:47:34 +0100 Message-Id: <20221231104736.12635-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_024807_498623_37FAA2B8 X-CRM114-Status: GOOD ( 12.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The patch, backwards compatible, extends the driver to initialize the clock directly from the device tree. Signed-off-by: Dario Binacchi --- drivers/clk/imx/clk-cpu.c | 54 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/clk/imx/clk-cpu.c b/drivers/clk/imx/clk-cpu.c index cb6ca4cf0535..28fb75c6ecea 100644 --- a/drivers/clk/imx/clk-cpu.c +++ b/drivers/clk/imx/clk-cpu.c @@ -106,3 +106,57 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, return hw; } EXPORT_SYMBOL_GPL(imx_clk_hw_cpu); + +/** + * of_imx_cpu_clk_setup - Setup function for imx low power gate + * clock + * @node: device node for the clock + */ +static void __init of_imx_cpu_clk_setup(struct device_node *node) +{ + struct clk_hw *hw; + struct clk *parent_clk, *div, *mux, *pll, *step; + const char *name = node->name, *parent_name; + + parent_clk = of_clk_get_by_name(node, "fck"); + if (IS_ERR(parent_clk)) { + pr_err("failed to get parent clock for %pOFn\n", node); + return; + } + + div = of_clk_get_by_name(node, "div-clk"); + if (IS_ERR(div)) { + pr_err("failed to get div clock for %pOFn\n", node); + return; + } + + mux = of_clk_get_by_name(node, "mux-clk"); + if (IS_ERR(div)) { + pr_err("failed to get mux clock for %pOFn\n", node); + return; + } + + pll = of_clk_get_by_name(node, "pll-clk"); + if (IS_ERR(div)) { + pr_err("failed to get pll clock for %pOFn\n", node); + return; + } + + step = of_clk_get_by_name(node, "step-clk"); + if (IS_ERR(div)) { + pr_err("failed to get step clock for %pOFn\n", node); + return; + } + + parent_name = __clk_get_name(parent_clk); + of_property_read_string(node, "clock-output-names", &name); + + hw = imx_clk_hw_cpu(name, parent_name, div, mux, pll, step); + if (!IS_ERR(hw)) + of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw); + + pr_debug("name: %s, parent: %s, div: %s, mux: %s, pll: %s, step: %s\n", + name, parent_name, __clk_get_name(div), __clk_get_name(mux), + __clk_get_name(pll), __clk_get_name(step)); +} +CLK_OF_DECLARE(fsl_cpu_clk, "fsl,cpu-clock", of_imx_cpu_clk_setup); From patchwork Sat Dec 31 10:47:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 13086025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7CEC3C3DA7D for ; Sat, 31 Dec 2022 10:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=chXPUWh+ou1uc07uWui+QmnXtqLuxwa+T19oIa3yKwo=; b=KpNgMGU9YwAf5y fw+MaJTGg9wsMfJsXk0fnU4wb5V/+W//xXwdZKJ/eP7KBqeOfuoMQPK+4IIwbzEIKQW+aJLQaQcm4 dR6E9ALHF1Li6yj4l0wjcoqqVn/TO3si5kWnIddoFck5dk+RKjNjy9ONeMr8hFCyydsgEhtZTJjj+ Hi8B+4fazNgqE6G7UDBtcICyFRBG0xBKwQwUM5qelrKthpzbMRRrJahXBH4WGd6YT6u/6XFOjp0+6 yy0gQQKxklcxFKciKL10QKp0cXAhyV1HGrsMCzw/+NutgJZ9UYHPBKdKkinQ/8dLssyUulOdatTXR e40rbRO3jBx023PIkPWg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZWa-0047Hc-Dd; Sat, 31 Dec 2022 10:55:37 +0000 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pBZPM-0042dT-9y for linux-arm-kernel@lists.infradead.org; Sat, 31 Dec 2022 10:48:10 +0000 Received: by mail-ed1-x52e.google.com with SMTP id b88so26295092edf.6 for ; Sat, 31 Dec 2022 02:48:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i4BAr3YDTtam7xHcR497eo7kHS6EX5vNVSsGQ3XZdVg=; b=ROLV5VC2YJKbZIZ4NSupPBjokbyz8XDtxDKZEsyZDegv7Y+nQwgg0Q77od8riAm9pN p43uc2oajTE0nu4DFsjAsTSe9BrclZmI8xi7O8Dl+xMukDXIX+mkHEGyIauIsItG+zUG LxA7cy/5n+BRZ4JdiD2454avSuVEdlMlUP+Js= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i4BAr3YDTtam7xHcR497eo7kHS6EX5vNVSsGQ3XZdVg=; b=Uf7KNes+uAhWnaD45yUYmIG2NuRccncPnyOFKcy0ntGO9cHR4UCsL1Vd0ngfn+m9Vp PoacxripV1sQHSGT6ZAFBNQ01JU3i/O10mu6tGTnH3pE+v7uhIf0oAXqVyuoJ8g/Xdqp uh4tpziMGSmcLtM9agV5zv3XlnfRNOnmEWEm3PjCWSjqiXsQWpfIcaGCJZJkdAS8rmY2 AgM0qI1qUqTMg2RsAu+Sur+BfY4TH2ytFS3KTVFNxBr5hgJhMfd9gb6Pi2g3ZeBl0X97 /8Csdp7gxnpTv13w5VHYaK0IFviOS1lSCo/NuwrktbaaxqnuvbTAdvw97jGNv2xvXUh7 no6Q== X-Gm-Message-State: AFqh2kptAhXPUY0V1o6wxvCMuTG2h2LbcvK+BE3O1gAwngjncsBKjRg2 3zDWhKY5JDhd22ThrqVED0GKNQ== X-Google-Smtp-Source: AMrXdXu1wnYLFYK3qlYdujbtgm9DCm5pkd5o4YS26KynkC7DDnX2QN12NN+FZg2mjdguJa8CIhfhog== X-Received: by 2002:a05:6402:f05:b0:45c:834b:f28c with SMTP id i5-20020a0564020f0500b0045c834bf28cmr31101282eda.9.1672483686562; Sat, 31 Dec 2022 02:48:06 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-80-180-23-57.retail.telecomitalia.it. [80.180.23.57]) by smtp.gmail.com with ESMTPSA id z4-20020a17090655c400b0083ffb81f01esm10765438ejp.136.2022.12.31.02.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Dec 2022 02:48:06 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: tommaso.merciai@amarulasolutions.com, linux-amarula@amarulasolutions.com, Chen-Yu Tsai , jagan@amarulasolutions.com, angelo@amarulasolutions.com, anthony@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Abel Vesa , Adam Ford , Fabio Estevam , Krzysztof Kozlowski , Li Jun , Lucas Stach , Marek Vasut , Markus Niebel , Michael Turquette , NXP Linux Team , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 10/11] arm64: dts: imx8mn: add dumy clock Date: Sat, 31 Dec 2022 11:47:35 +0100 Message-Id: <20221231104736.12635-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> References: <20221231104736.12635-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221231_024808_543260_F3B6FCCF X-CRM114-Status: GOOD ( 14.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The dummy clock was the only fixed rate clock not initialized from the device tree. So let's add it to the device tree like we did for the others fixed rate clocks. This is a preparation patch for the upcoming support to setup all the clocks directly from the device tree. Signed-off-by: Dario Binacchi --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 11 +++++++++-- drivers/clk/imx/clk-imx8mn.c | 2 +- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index b7d91df71cc2..1949db3e08f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -217,6 +217,13 @@ clk_ext4: clock-ext4 { clock-output-names = "clk_ext4"; }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "dummy"; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, <&clk_dummy>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "dummy"; assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, <&clk IMX8MN_CLK_A53_CORE>, <&clk IMX8MN_CLK_NOC>, diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index af256ade554f..e1f059dc5afa 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -331,7 +331,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) clk_hw_data->num = IMX8MN_CLK_END; hws = clk_hw_data->hws; - hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); + hws[IMX8MN_CLK_DUMMY] = imx_get_clk_hw_by_name(np, "dummy"); hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m"); hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k"); hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");