From patchwork Mon Jan 2 06:20:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 13086544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 884C9C4167B for ; Mon, 2 Jan 2023 06:20:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 426FE10E18A; Mon, 2 Jan 2023 06:20:17 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id CBA4010E0CC for ; Mon, 2 Jan 2023 06:20:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672640413; x=1704176413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z+ofmlmt/BsCW8VCe6+BRYbH5eHuR/1UMtdZJnGjrwo=; b=VQaPRZeV2KAUa+eAQjQnltuAX3dIcY5hzRLkiMWByPx3ZiK1eigkXLRd MDiVV1ph1Iw1gINFqjGXJpyMe1PlEeopEC+wO+y2rx46CaJf5N5ZagfNz vfGFEa2CIT5CDls6h6lvI/NGeLb6d7DG4Qr5/TDcRjXIdwTlmni7MWKS7 CAbO6v/rj/2RVW880TEC+nOe3ZDeWhW//1qdCr1iA41/7tzo7wxapBtNm 2SyTyIaeG/vlONOhpBIShUaFMc9Jwe/oIiNCQPVdcv6VoCq9MuWS6nrCw GDrK1lQWH16r89tzZeKHnbEQykI0zUpHLguE65U2e2G6CokMbX95GS9KM A==; X-IronPort-AV: E=McAfee;i="6500,9779,10577"; a="348657600" X-IronPort-AV: E=Sophos;i="5.96,293,1665471600"; d="scan'208";a="348657600" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jan 2023 22:20:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10577"; a="647840548" X-IronPort-AV: E=Sophos;i="5.96,293,1665471600"; d="scan'208";a="647840548" Received: from chaitanya.iind.intel.com ([10.190.239.113]) by orsmga007.jf.intel.com with ESMTP; 01 Jan 2023 22:20:11 -0800 From: Chaitanya Kumar Borah To: intel-gfx@lists.freedesktop.org Date: Mon, 2 Jan 2023 11:50:02 +0530 Message-Id: <20230102062005.720964-2-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com> References: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 1/4] drm/i915/quirks: Add quirk for 480MHz CDCLK step X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" A new CDCLK step of 480MHz has been added on SKUs that has a RPL-U device id. This is done to support 120Hz displays with more efficiency. RPL-U device ids are currently added within the RPL-P sub platform. It seems to be an overkill to add a separate sub platform just to support this change. Therefore, quirks are a good way to achieve the same. BSpec: 55409 Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_quirks.c | 14 ++++++++++++++ drivers/gpu/drm/i915/display/intel_quirks.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c index 6e48d3bcdfec..0a30499835b3 100644 --- a/drivers/gpu/drm/i915/display/intel_quirks.c +++ b/drivers/gpu/drm/i915/display/intel_quirks.c @@ -65,6 +65,16 @@ static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915) drm_info(&i915->drm, "Applying no pps backlight power quirk\n"); } +/* + * A new step of 480MHz has been added on SKUs that have a RPL-U device id. + * This particular step is to better support 120Hz panels. + */ +static void quirk_480mhz_cdclk_step_hook(struct drm_i915_private *i915) +{ + intel_set_quirk(i915, QUIRK_480MHZ_CDCLK_STEP); + drm_info(&i915->drm, "Applying 480MHz CDCLK step quirk\n"); +} + struct intel_quirk { int device; int subsystem_vendor; @@ -199,6 +209,10 @@ static struct intel_quirk intel_quirks[] = { /* ECS Liva Q2 */ { 0x3185, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time }, { 0x3184, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time }, + /* RPL-U */ + { 0xA7A1, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook }, + { 0xA721, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook }, + { 0xA7A9, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook }, }; void intel_init_quirks(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h b/drivers/gpu/drm/i915/display/intel_quirks.h index 10a4d163149f..71e05684f5f4 100644 --- a/drivers/gpu/drm/i915/display/intel_quirks.h +++ b/drivers/gpu/drm/i915/display/intel_quirks.h @@ -17,6 +17,7 @@ enum intel_quirk_id { QUIRK_INVERT_BRIGHTNESS, QUIRK_LVDS_SSC_DISABLE, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK, + QUIRK_480MHZ_CDCLK_STEP, }; void intel_init_quirks(struct drm_i915_private *i915); From patchwork Mon Jan 2 06:20:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 13086545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8659C4167B for ; Mon, 2 Jan 2023 06:20:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D0E6710E189; Mon, 2 Jan 2023 06:20:18 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id B8EB210E18A for ; Mon, 2 Jan 2023 06:20:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672640416; x=1704176416; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=W5+ctQ3tDOqnZCDqpB97AV1hp7iuSH53nHrmhhP2B50=; b=TNfpFYU41dyQ5ISpbZ0e3vb2tv/otub4wxnjZBBN6U7hVE7R15tDFrst nfgvTv2xQUdHwyQIjHNUsIXvogaSFj45wuE2lW0mHOGNXHnt8jGfpjWan B4X0QDZVD7D42nUj3wq2ok/WEp5N0Xe+PNI+WwFwyc4Aar/0MXjEjW+dX SwsM2zYlyD2ceHbw0VC1ftsa3fqIyCf79Bi7Y2Q5j9tCrH729Uw9aACSF ktA1HgTY4riib6OfP4jVWj3b5l1XlXt3W9CNPwSK3iV1HZ7v6kqO5LkM7 LVRNd90GTtK0DBZG+Q2A/dPS90IHv6k9PaFWSwfZcOQwxxv3Toqqo05xt g==; X-IronPort-AV: E=McAfee;i="6500,9779,10577"; a="348657602" X-IronPort-AV: E=Sophos;i="5.96,293,1665471600"; d="scan'208";a="348657602" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jan 2023 22:20:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10577"; a="647840562" X-IronPort-AV: E=Sophos;i="5.96,293,1665471600"; d="scan'208";a="647840562" Received: from chaitanya.iind.intel.com ([10.190.239.113]) by orsmga007.jf.intel.com with ESMTP; 01 Jan 2023 22:20:13 -0800 From: Chaitanya Kumar Borah To: intel-gfx@lists.freedesktop.org Date: Mon, 2 Jan 2023 11:50:03 +0530 Message-Id: <20230102062005.720964-3-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com> References: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 2/4] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" A new step of 480MHz has been added on SKUs that have a RPL-U device id to support 120Hz displays more efficiently. Use a new quirk to identify the machine for which this change needs to be applied. BSpec: 55409 Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_cdclk.c | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 0c107a38f9d0..f5df0a806765 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -38,6 +38,7 @@ #include "intel_pcode.h" #include "intel_psr.h" #include "vlv_sideband.h" +#include "intel_quirks.h" /** * DOC: CDCLK / RAWCLK @@ -1329,6 +1330,27 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = { {} }; +static const struct intel_cdclk_vals rplu_cdclk_table[] = { + { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 }, + { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, + { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 }, + { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, + { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, + + { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 }, + { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, + { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 }, + { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, + { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 }, + + { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 }, + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 }, + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, + {} +}; + static const struct intel_cdclk_vals dg2_cdclk_table[] = { { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 }, { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 }, @@ -3353,6 +3375,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) /* Wa_22011320316:adl-p[a0] */ if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; + /* BSpec: 55409 */ + else if (intel_has_quirk(dev_priv, QUIRK_480MHZ_CDCLK_STEP)) + dev_priv->display.cdclk.table = rplu_cdclk_table; else dev_priv->display.cdclk.table = adlp_cdclk_table; } else if (IS_ROCKETLAKE(dev_priv)) { From patchwork Mon Jan 2 06:20:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 13086546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2BDE0C3DA7C for ; Mon, 2 Jan 2023 06:20:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 705EF10E190; Mon, 2 Jan 2023 06:20:22 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F39010E18D for ; Mon, 2 Jan 2023 06:20:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672640419; x=1704176419; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9kkWV7Wcd0Q9lV4EIaxACG1ZlZHCtLOhBBRWCrRzcwI=; b=MIwhLzigw4xiCKXgCDCGhQWPb9PBm/JGexpTiL6Xzuz5IoBr1QbEHEDr IvqiKpA7VmcN10vsUboP8OnFG6WARRv3bTB8fo6IMxHYp4p9pDep4UU8a PgpcxFoqS6Z1V0Xd05PQOGpO5yHzn/tVCEhLO6ejPOym88iBstDgB0oyG Jh2E0UAfppFfO7a5pJX710PcWQZNpQWYnR3wD91XjuCw8pJ+42483h0nG 21lZyrf3RnUbMHe2VLf1wjbyH8KWbo/nag/absSOW5oPaxSo1xj9PEfEz L6NQSrkft2OZue/qzaZrDDbt/mQfVcuzPrrt3dmgb5kWjJoBXNjdLgvW4 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10577"; a="348657606" X-IronPort-AV: E=Sophos;i="5.96,293,1665471600"; d="scan'208";a="348657606" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jan 2023 22:20:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10577"; a="647840569" X-IronPort-AV: E=Sophos;i="5.96,293,1665471600"; d="scan'208";a="647840569" Received: from chaitanya.iind.intel.com ([10.190.239.113]) by orsmga007.jf.intel.com with ESMTP; 01 Jan 2023 22:20:16 -0800 From: Chaitanya Kumar Borah To: intel-gfx@lists.freedesktop.org Date: Mon, 2 Jan 2023 11:50:04 +0530 Message-Id: <20230102062005.720964-4-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com> References: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 3/4] drm/i915: Initialize intel quirks before CDCLK initialization X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With addition of new quirk QUIRK_480MHZ_CDCLK_STEP, it is imperative that quirks should be initialized before CDCLK initialization. Refactor the code accordingly. Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_display.c | 2 -- drivers/gpu/drm/i915/i915_driver.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e75b9b2a0e01..5c71fd83c25b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8666,8 +8666,6 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915) INIT_WORK(&i915->display.atomic_helper.free_work, intel_atomic_helper_free_state_worker); - intel_init_quirks(i915); - intel_fbc_init(i915); return 0; diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index c1e427ba57ae..4d1cb46f9863 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -104,6 +104,7 @@ #include "intel_pm.h" #include "intel_region_ttm.h" #include "vlv_suspend.h" +#include "display/intel_quirks.h" static const struct drm_driver i915_drm_driver; @@ -388,6 +389,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) if (ret < 0) goto err_gem; intel_irq_init(dev_priv); + intel_init_quirks(dev_priv); intel_init_display_hooks(dev_priv); intel_init_clock_gating_hooks(dev_priv); From patchwork Mon Jan 2 06:20:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 13086547 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE5B2C4167B for ; Mon, 2 Jan 2023 06:20:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E57E10E0CC; Mon, 2 Jan 2023 06:20:25 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 508F110E18D for ; Mon, 2 Jan 2023 06:20:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672640422; x=1704176422; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qwa7GQTqwXH5Z26MRfY0XyxEtLA+LftZtvj0NExvn94=; b=Ge6INMa0DY990RPr+Nh1QpePzajW59IkrlzPLjQuwkaqw6M/jtUsNlbm osAVGK+9RzCkW2nUpgjAtXrLeeYDNE/oIYHkLdDKPv9t6+otF3zO1irIR LtJnYrAOiKw5IgnOvWbJ5f48lnudeJ37tkld/beDL4aEplvG7BSfUj7oK bzvKBDwsvS834adCreoTCDKR1IDZ/5FYriF1NO5cNHYd8S+IviC8XRnNa R9/FC9O5vFmNufS9WfRW5RyeTkpTFUsMRTB/n/8PB0P60eXzu/xfOF5eI MtlUOsMPUyrxUgk6HkF9cKbv3TsO+26BvZakgMULRsdYg9ykBGVapajor g==; X-IronPort-AV: E=McAfee;i="6500,9779,10577"; a="348657608" X-IronPort-AV: E=Sophos;i="5.96,293,1665471600"; d="scan'208";a="348657608" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jan 2023 22:20:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10577"; a="647840579" X-IronPort-AV: E=Sophos;i="5.96,293,1665471600"; d="scan'208";a="647840579" Received: from chaitanya.iind.intel.com ([10.190.239.113]) by orsmga007.jf.intel.com with ESMTP; 01 Jan 2023 22:20:19 -0800 From: Chaitanya Kumar Borah To: intel-gfx@lists.freedesktop.org Date: Mon, 2 Jan 2023 11:50:05 +0530 Message-Id: <20230102062005.720964-5-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com> References: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 4/4] drm/i915: Apply CDCLK quirk only on QS parts X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" RPL-U boards with ES silicon does not support the 480Mhz step of CDCLK. To differentiate between QS and ES part CPU brand string is the only feasible way as of now. ES parts have "Genuine Intel" in their brand string while QS parts have a more specific brand string, for ex. "13th Gen Intel(R) Core(TM) i5-1345U" BSpec: 55409 Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_quirks.c | 32 +++++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c index 0a30499835b3..a6d7a2430626 100644 --- a/drivers/gpu/drm/i915/display/intel_quirks.c +++ b/drivers/gpu/drm/i915/display/intel_quirks.c @@ -14,6 +14,25 @@ static void intel_set_quirk(struct drm_i915_private *i915, enum intel_quirk_id q i915->display.quirks.mask |= BIT(quirk); } +/* + * To differentiate between QS and ES part CPU brand string is the only feasible way + * as of now. ES parts have "Genuine Intel" in their brand string while QS parts have a more + * specific brand string, for ex. "13th Gen Intel(R) Core(TM) i5-1345U" + */ +static bool is_QS_part(void) +{ + struct cpuinfo_x86 *c; + unsigned int cpu = get_cpu(); + + c = &cpu_data(cpu); + put_cpu(); + + if (c->x86_model_id[0] && !strstr(c->x86_model_id, "Genuine Intel")) + return true; + + return false; +} + /* * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason */ @@ -67,12 +86,19 @@ static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915) /* * A new step of 480MHz has been added on SKUs that have a RPL-U device id. - * This particular step is to better support 120Hz panels. + * This particular step is to better support 120Hz panels. In addition to + * identifying RPL-U device id, we need to make a distinction between ES and + * QS parts as this change comes only to QS parts. For this CPUID Brand + * string is used. 480Mhz step is only supported in SKUs which does not + * contain the string "Genuine Intel" in the Brand string. */ + static void quirk_480mhz_cdclk_step_hook(struct drm_i915_private *i915) { - intel_set_quirk(i915, QUIRK_480MHZ_CDCLK_STEP); - drm_info(&i915->drm, "Applying 480MHz CDCLK step quirk\n"); + if (is_QS_part()) { + intel_set_quirk(i915, QUIRK_480MHZ_CDCLK_STEP); + drm_info(&i915->drm, "Applying 480MHz CDCLK step quirk\n"); + } } struct intel_quirk {