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Sun, 1 Jan 2023 22:49:12 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sun, 1 Jan 2023 22:49:11 -0800 Received: from mkumard.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Sun, 1 Jan 2023 22:49:09 -0800 From: Mohan Kumar To: , , , CC: , , , Mohan Kumar , Subject: [PATCH v2] dmaengine: tegra210-adma: fix global intr clear Date: Mon, 2 Jan 2023 12:18:44 +0530 Message-ID: <20230102064844.31306-1-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT026:EE_|DM6PR12MB4076:EE_ X-MS-Office365-Filtering-Correlation-Id: a1718b25-5088-4257-117d-08daec8d799f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nkABbZDJplXy6oCnkUlPXKvQluLTntCNVs1L9iUJzQ1NwVQ+I1hTS8WEwJTQEU7AHbc0rCkI3w4Q78vKPHGEeFWx4xJg9SfiunssOJkE0OvmwGVtXfBF4WQPkJtCKD0mNqLuUR0M7uVmQ7lQjeRupzILqIZzIkO+jGEupS/gegmbLSTiO/0J1wZfpshZ7Y0PDo2Smxf/FYkN3j4AS09Abo5mS4egLxwK84ym74RA7zbIUhKrCCinOyZgTrbIdj4ud28eNd6pfhD/PyK5/nx7F/OULyVYzE7OwkHYzJHI5kSqPxoAqI5KeTuqOIF/tz7QGadcRo4vybn0CVYImtFiB6pq5shIRaC53QITDCQasrKfJ4hwCYBS6ADfEcCTqFCuH8EE9mDmJILysgJWVfI/M/DwEdr2TkXar/7fsJ3/x3TuHhFIYhVtBLm/ob7rBCPtkmUe6cOk7jKSSpGvXFRbEFCdsJavTThwxdxNnTJqKx9k6HGem3Iyy6m1sZAPpeEgQsLUPW/SNPItlZUElRoYd+vMEQui9fmFy5Dc2rS/OlX/DuHLjC+V77bKkHJAv40c5gHThQ2gSZGEs/9jUBuSXgCXuxkoDSL8R7+TtMBjC5Ikn/p6xLaj6EJ60rI+LygaEQIcww8ycTXVqcN9M4M7Qg95KZJuEH0ymUpFRIPGxC29cbKTdCbvV1rz9mYv7QjNgoTg7mZ/YW7aTOCcq6MfaO5JeV1Nj3HVGO4/YdJsfwY= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(346002)(39860400002)(136003)(376002)(451199015)(36840700001)(40470700004)(46966006)(82740400003)(110136005)(36860700001)(478600001)(40460700003)(5660300002)(36756003)(2616005)(1076003)(40480700001)(8936002)(4744005)(41300700001)(7696005)(70206006)(70586007)(4326008)(356005)(8676002)(47076005)(426003)(82310400005)(336012)(7636003)(83380400001)(6666004)(316002)(54906003)(186003)(2906002)(26005)(86362001)(22166006);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2023 06:49:20.0420 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1718b25-5088-4257-117d-08daec8d799f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4076 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The current global interrupt clear programming register offset was not correct. Fix the programming with right offset Fixes: ded1f3db4cd6 ("dmaengine: tegra210-adma: prepare for supporting newer Tegra chips") Cc: stable@vger.kernel.org Signed-off-by: Mohan Kumar --- drivers/dma/tegra210-adma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index ae39b52012b2..79da93cc77b6 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -221,7 +221,7 @@ static int tegra_adma_init(struct tegra_adma *tdma) int ret; /* Clear any interrupts */ - tdma_write(tdma, tdma->cdata->global_int_clear, 0x1); + tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1); /* Assert soft reset */ tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1);