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Tue, 3 Jan 2023 17:22:16 -0800 From: Shanker Donthineni To: Catalin Marinas , Marc Zyngier , Will Deacon , James Morse CC: , , Shanker Donthineni Subject: [PATCH] arm64: gic: increase the number of IRQ descriptors Date: Tue, 3 Jan 2023 19:22:15 -0600 Message-ID: <20230104012215.1222263-1-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT064:EE_|LV2PR12MB5869:EE_ X-MS-Office365-Filtering-Correlation-Id: 9b33e5cb-2091-46a0-d5ca-08daedf2268e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8K0umbqjJgjCcGEh7at+m746uZ7IK7XQq4JoUBjr/oWjcIDH/Q5IUm3utyQmKBplWltUeFBBkzUc7qOuyCGo6NldjH4W6sBrjYRW3cGGvjvcdlsDmsEI566ZMFwkcH1QU8XaTdG6SlNNiJ8HorUWSuy3QB0rXQlRSuQkfmleaNvJku0Db8lUpRChE4lD6JRSUszg9vquEBSw2EWsuiHIwM22sGXX319IlsH4it56/zamsm3Oi7J92h5nHgDUohCUtfwJJ9TGI4y5CHcaARCcidPFllQ+vVeHQ70CxKA7zIRTtdJ8qRwu6v9/GgF0h8AmFUt1BLW8v8pauU+2jMFyXQ3XCm6eyToyyv1+8TUJdv32NuIZ3z4aqGScQ8aSU2bq+591AUpZ34+i5PwH5GTe7W6QISwGmuf3qkojwrQIgl+lHUZTFuMWefIdgfdYPXoiJGq9g+oF6+8jstMaoWdtKITBXRc6bLejB9HcycA63nAR6ZERF8KysxnPbEpGgPXoUeF1DyzixS19dLDepxtVD4q/DIwKRH7wAC4mkjQxq68VuaWcsyBG1frqLzcQVyQa2Vf3ESkpHuhxmNr3LViYmItF/FgTbgQruw4Qw9PS0ov0A43J3qTOjCa4NPkidj9MI69f/Dbxf0XQBA843ozKN4fOdFjoqs7WIpz/LHWAihTrah7X67wH2UBJ8OPhMjCdwJD92cGnPWMTzYO/GT+TXQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(346002)(376002)(136003)(451199015)(36840700001)(46966006)(40470700004)(41300700001)(5660300002)(8676002)(8936002)(4326008)(70206006)(70586007)(4744005)(316002)(110136005)(54906003)(2906002)(7696005)(478600001)(107886003)(426003)(47076005)(2616005)(86362001)(336012)(40480700001)(186003)(26005)(1076003)(36756003)(356005)(36860700001)(7636003)(82740400003)(40460700003)(82310400005);DIR:OUT;SFP:1101; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The default value of NR_IRQS is not sufficient to support GICv4.1 features and ~64K LPIs. This parameter would be too small for certain server platforms where it has many IO devices and is capable of direct injection of vSGI and vLPI features. Currently, maximum of 64 + 8192 (IRQ_BITMAP_BITS) IRQ descriptors are allowed. The vCPU creation fails after reaching count ~400 with kvm-arm.vgic_v4_enable=1. This patch increases NR_IRQS to 1^19 to cover 64K LPIs and 262144 vSGIs (16K vPEs x 16). Signed-off-by: Shanker Donthineni --- arch/arm64/include/asm/irq.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index 168d710a7b70..741e0e9148ed 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -4,6 +4,10 @@ #ifndef __ASSEMBLER__ +#if defined(CONFIG_ARM_GIC_V3_ITS) +#define NR_IRQS (1 << 19) +#endif + #include #include