From patchwork Tue Jan 10 14:57:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13095245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6867FC54EBE for ; Tue, 10 Jan 2023 14:58:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234513AbjAJO6P (ORCPT ); Tue, 10 Jan 2023 09:58:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238660AbjAJO6M (ORCPT ); Tue, 10 Jan 2023 09:58:12 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E840710E0; Tue, 10 Jan 2023 06:58:10 -0800 (PST) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30A9Oglo026320; Tue, 10 Jan 2023 14:57:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=XVHq0Kz67cOqQ4FRlvygznzhRdnEVSLJ75V4v+tRpzc=; b=HHJerQFPulj+qGdEO+rKMBily3x2iJcybogCDtO40pHqzNOx/o7Hkui+SF5jiMX/flds avjEe/Y1Q1hpc+Jq/V4in42cC6+KzEaqPYZBpaX6EboYOd7MeYo585pcrNFKkAvvL4nN Dmk8H1JlcQSvfWMnCGJJ26uyn5YNtsnD0mk2joWu7vPRXtfDib4joqVhoZ7V5w6+Hal7 kVx5citMRBn1yDKSKTuCJAFqm7vlKn9GB69+TAvUUWoOrJDceFSHSVqgrdUO5I2mAkZM AjaYejo754HfDeWouqQJSMjoZM7EGmRNQ2EAvLZAaZbkccvbjC8B8cCxYCrec1e+0t4/ ig== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3n156x0p0c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 10 Jan 2023 14:57:58 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30AEvv8b030222 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 10 Jan 2023 14:57:57 GMT Received: from hu-bjorande-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 10 Jan 2023 06:57:57 -0800 From: Bjorn Andersson To: Bjorn Andersson , Konrad Dybcio , Johan Hovold CC: Dmitry Baryshkov , , , , Subject: [PATCH v6 1/4] arm64: dts: qcom: sc8280xp: Define some of the display blocks Date: Tue, 10 Jan 2023 06:57:48 -0800 Message-ID: <20230110145751.2654795-2-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230110145751.2654795-1-quic_bjorande@quicinc.com> References: <20230110145751.2654795-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: xQQ_l7-p4Tsm359qKPA3EDjjONXMnUjK X-Proofpoint-GUID: xQQ_l7-p4Tsm359qKPA3EDjjONXMnUjK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-10_06,2023-01-10_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 phishscore=0 clxscore=1011 mlxscore=0 priorityscore=1501 suspectscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301100093 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bjorn Andersson Define the display clock controllers, the MDSS instances, the DP phys and connect these together. Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson --- Changes since v5: - Moved displayport controllers to MMCX - Dropped required-opps = leftover in dispcc nodes - Moved status property last arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 836 +++++++++++++++++++++++++ 1 file changed, 836 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0ea2f19d471b..2f42814f23ab 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2022, Linaro Limited */ +#include #include #include #include @@ -2097,6 +2098,44 @@ usb_1_qmpphy: phy@8903000 { status = "disabled"; }; + mdss1_dp0_phy: phy@8909a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x08909a00 0 0x19c>, + <0 0x08909200 0 0xec>, + <0 0x08909600 0 0xec>, + <0 0x08909000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp1_phy: phy@890ca00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x0890ca00 0 0x19c>, + <0 0x0890c200 0 0xec>, + <0 0x0890c600 0 0xec>, + <0 0x0890c000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + pmu@9091000 { compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x9091000 0 0x1000>; @@ -2303,6 +2342,325 @@ usb_1_dwc3: usb@a800000 { }; }; + mdss0: display-subsystem@ae00000 { + compatible = "qcom,sc8280xp-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc0 MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x1000 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss0_mdp: display-controller@ae01000 { + compatible = "qcom,sc8280xp-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdss0_mdp_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + interrupt-parent = <&mdss0>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + mdss0_intf5_out: endpoint { + remote-endpoint = <&mdss0_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + mdss0_intf6_out: endpoint { + remote-endpoint = <&mdss0_dp2_in>; + }; + }; + }; + + mdss0_mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss0_dp2: displayport-controller@ae9a000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0xae9a000 0 0x200>, + <0 0xae9a200 0 0x200>, + <0 0xae9a400 0 0x600>, + <0 0xae9b000 0 0x400>; + interrupt-parent = <&mdss0>; + interrupts = <14>; + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; + + phys = <&mdss0_dp2_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&mdss0_dp2_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dp2_in: endpoint { + remote-endpoint = <&mdss0_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss0_dp2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss0_dp3: displayport-controller@aea0000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0xaea0000 0 0x200>, + <0 0xaea0200 0 0x200>, + <0 0xaea0400 0 0x600>, + <0 0xaea1000 0 0x400>; + interrupt-parent = <&mdss0>; + interrupts = <15>; + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; + + phys = <&mdss0_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&mdss0_dp3_opp_table>; + power-domains = <&dispcc0 MDSS_GDSC>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dp3_in: endpoint { + remote-endpoint = <&mdss0_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss0_dp3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + + mdss0_dp2_phy: phy@aec2a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x0aec2a00 0 0x19c>, + <0 0x0aec2200 0 0xec>, + <0 0x0aec2600 0 0xec>, + <0 0x0aec2000 0 0x1c8>; + + clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss0_dp3_phy: phy@aec5a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x0aec5a00 0 0x19c>, + <0 0x0aec5200 0 0xec>, + <0 0x0aec5600 0 0xec>, + <0 0x0aec5000 0 0x1c8>; + + clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + dispcc0: clock-controller@af00000 { + compatible = "qcom,sc8280xp-dispcc0"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <&mdss0_dp2_phy 0>, + <&mdss0_dp2_phy 1>, + <&mdss0_dp3_phy 0>, + <&mdss0_dp3_phy 1>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; @@ -2925,6 +3283,484 @@ IPCC_MPROC_SIGNAL_GLINK_QMP qcom,remote-pid = <12>; }; }; + + mdss1: display-subsystem@22000000 { + compatible = "qcom,sc8280xp-mdss"; + reg = <0 0x22000000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc1 MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x1800 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss1_mdp: display-controller@22001000 { + compatible = "qcom,sc8280xp-dpu"; + reg = <0 0x22001000 0 0x8f000>, + <0 0x220b0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc1 DISP_CC_MDSS_MDP_CLK>, + <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_MDP_CLK>, + <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <460000000>, + <19200000>; + + operating-points-v2 = <&mdss1_mdp_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + interrupt-parent = <&mdss1>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_intf0_out: endpoint { + remote-endpoint = <&mdss1_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + mdss1_intf4_out: endpoint { + remote-endpoint = <&mdss1_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + mdss1_intf5_out: endpoint { + remote-endpoint = <&mdss1_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + mdss1_intf6_out: endpoint { + remote-endpoint = <&mdss1_dp2_in>; + }; + }; + }; + + mdss1_mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss1_dp0: displayport-controller@22090000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x22090000 0 0x200>, + <0 0x22090200 0 0x200>, + <0 0x22090400 0 0x600>, + <0 0x22091000 0 0x400>; + interrupt-parent = <&mdss1>; + interrupts = <12>; + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; + + phys = <&mdss1_dp0_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&mdss1_dp0_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp0_in: endpoint { + remote-endpoint = <&mdss1_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + }; + + mdss1_dp1: displayport-controller@22098000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x22098000 0 0x200>, + <0 0x22098200 0 0x200>, + <0 0x22098400 0 0x600>, + <0 0x22099000 0 0x400>; + interrupt-parent = <&mdss1>; + interrupts = <13>; + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; + + phys = <&mdss1_dp1_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&mdss1_dp1_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp1_in: endpoint { + remote-endpoint = <&mdss1_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss1_dp2: displayport-controller@2209a000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x2209a000 0 0x200>, + <0 0x2209a200 0 0x200>, + <0 0x2209a400 0 0x600>, + <0 0x2209b000 0 0x400>; + interrupt-parent = <&mdss1>; + interrupts = <14>; + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; + + phys = <&mdss1_dp2_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&mdss1_dp2_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp2_in: endpoint { + remote-endpoint = <&mdss1_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss1_dp3: displayport-controller@220a0000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x220a0000 0 0x200>, + <0 0x220a0200 0 0x200>, + <0 0x220a0400 0 0x600>, + <0 0x220a1000 0 0x400>; + interrupt-parent = <&mdss1>; + interrupts = <15>; + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; + + phys = <&mdss1_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&mdss1_dp3_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp3_in: endpoint { + remote-endpoint = <&mdss1_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + + mdss1_dp2_phy: phy@220c2a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x220c2a00 0 0x19c>, + <0 0x220c2200 0 0xec>, + <0 0x220c2600 0 0xec>, + <0 0x220c2000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp3_phy: phy@220c5a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x220c5a00 0 0x19c>, + <0 0x220c5200 0 0xec>, + <0 0x220c5600 0 0xec>, + <0 0x220c5000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + dispcc1: clock-controller@22100000 { + compatible = "qcom,sc8280xp-dispcc1"; + reg = <0 0x22100000 0 0x20000>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <0>, + <&mdss1_dp0_phy 0>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp1_phy 0>, + <&mdss1_dp1_phy 1>, + <&mdss1_dp2_phy 0>, + <&mdss1_dp2_phy 1>, + <&mdss1_dp3_phy 0>, + <&mdss1_dp3_phy 1>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + status = "disabled"; + }; }; sound: sound { From patchwork Tue Jan 10 14:57:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13095242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E27B1C54EBE for ; Tue, 10 Jan 2023 14:58:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238617AbjAJO6L (ORCPT ); Tue, 10 Jan 2023 09:58:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233973AbjAJO6J (ORCPT ); Tue, 10 Jan 2023 09:58:09 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A801358D15; 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Tue, 10 Jan 2023 14:57:58 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30AEvvYl000518 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 10 Jan 2023 14:57:57 GMT Received: from hu-bjorande-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 10 Jan 2023 06:57:57 -0800 From: Bjorn Andersson To: Bjorn Andersson , Konrad Dybcio , Johan Hovold CC: Dmitry Baryshkov , , , , Subject: [PATCH v6 2/4] arm64: dts: qcom: sc8280xp-crd: Enable EDP Date: Tue, 10 Jan 2023 06:57:49 -0800 Message-ID: <20230110145751.2654795-3-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230110145751.2654795-1-quic_bjorande@quicinc.com> References: <20230110145751.2654795-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: PnfVI3rrsUL8GAajoak--hBrZntCzAsQ X-Proofpoint-ORIG-GUID: PnfVI3rrsUL8GAajoak--hBrZntCzAsQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-10_06,2023-01-10_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 spamscore=0 clxscore=1015 suspectscore=0 adultscore=0 impostorscore=0 bulkscore=0 malwarescore=0 mlxlogscore=904 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301100093 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bjorn Andersson The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes and link it together with the backlight control. Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson --- Changes since v5: - Moved status property last in nodes arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 73 ++++++++++++++++++++++- 1 file changed, 72 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 6a619d07cdea..a836c3200d52 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -20,7 +20,7 @@ aliases { serial0 = &qup2_uart17; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pmc8280c_lpg 3 1000000>; enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; @@ -34,6 +34,22 @@ chosen { stdout-path = "serial0:115200n8"; }; + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_reg_en>; + + regulator-boot-on; + }; + vreg_edp_bl: regulator-edp-bl { compatible = "regulator-fixed"; @@ -228,6 +244,55 @@ vreg_l9d: ldo9 { }; }; +&dispcc0 { + status = "okay"; +}; + +&mdss0 { + status = "okay"; +}; + +&mdss0_dp3 { + compatible = "qcom,sc8280xp-edp"; + + data-lanes = <0 1 2 3>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + backlight = <&backlight>; + + ports { + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss0_dp3_out>; + }; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss0_dp3_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss0_dp3_phy { + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l3b>; + + status = "okay"; +}; + &pcie2a { perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; @@ -496,6 +561,12 @@ hastings_reg_en: hastings-reg-en-state { &tlmm { gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + edp_reg_en: edp-reg-en-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <16>; + }; + kybd_default: kybd-default-state { disable-pins { pins = "gpio102"; From patchwork Tue Jan 10 14:57:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13095244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1D28C678D8 for ; Tue, 10 Jan 2023 14:58:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233353AbjAJO6N (ORCPT ); Tue, 10 Jan 2023 09:58:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238460AbjAJO6K (ORCPT ); Tue, 10 Jan 2023 09:58:10 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D667959313; 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Tue, 10 Jan 2023 14:57:58 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30AEvwOo007676 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 10 Jan 2023 14:57:58 GMT Received: from hu-bjorande-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 10 Jan 2023 06:57:57 -0800 From: Bjorn Andersson To: Bjorn Andersson , Konrad Dybcio , Johan Hovold CC: Dmitry Baryshkov , , , , Subject: [PATCH v6 3/4] arm64: dts: qcom: sa8295-adp: Enable DP instances Date: Tue, 10 Jan 2023 06:57:50 -0800 Message-ID: <20230110145751.2654795-4-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230110145751.2654795-1-quic_bjorande@quicinc.com> References: <20230110145751.2654795-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ie3B2pE4-yHS8PmiFVmmyBNimc3jeoRU X-Proofpoint-ORIG-GUID: ie3B2pE4-yHS8PmiFVmmyBNimc3jeoRU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-10_06,2023-01-10_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 clxscore=1015 mlxscore=0 mlxlogscore=811 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301100093 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bjorn Andersson The SA8295P ADP has, among other interfaces, six MiniDP connectors which are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3. Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers, DP PHYs and link them all together. Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson --- Changes since v5: - Moved status property last in nodes arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 243 ++++++++++++++++++++++- 1 file changed, 241 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 84cb6f3eeb56..c35e16b087b8 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -23,6 +23,90 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + dp2-connector { + compatible = "dp-connector"; + label = "DP2"; + type = "mini"; + + hpd-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + + port { + dp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp0_phy_out>; + }; + }; + }; + + dp3-connector { + compatible = "dp-connector"; + label = "DP3"; + type = "mini"; + + hpd-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + + port { + dp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp1_phy_out>; + }; + }; + }; + + edp0-connector { + compatible = "dp-connector"; + label = "EDP0"; + type = "mini"; + + hpd-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; + + port { + edp0_connector_in: endpoint { + remote-endpoint = <&mdss0_dp2_phy_out>; + }; + }; + }; + + edp1-connector { + compatible = "dp-connector"; + label = "EDP1"; + type = "mini"; + + hpd-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + + port { + edp1_connector_in: endpoint { + remote-endpoint = <&mdss0_dp3_phy_out>; + }; + }; + }; + + edp2-connector { + compatible = "dp-connector"; + label = "EDP2"; + type = "mini"; + + hpd-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + + port { + edp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp2_phy_out>; + }; + }; + }; + + edp3-connector { + compatible = "dp-connector"; + label = "EDP3"; + type = "mini"; + + hpd-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + port { + edp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp3_phy_out>; + }; + }; + }; }; &apps_rsc { @@ -159,13 +243,168 @@ vreg_l7g: ldo7 { vreg_l8g: ldo8 { regulator-name = "vreg_l8g"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l11g: ldo11 { + regulator-name = "vreg_l11g"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; regulator-initial-mode = ; }; }; }; +&dispcc0 { + status = "okay"; +}; + +&dispcc1 { + status = "okay"; +}; + +&mdss0 { + status = "okay"; +}; + +&mdss0_dp2 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss0_dp2_phy_out: endpoint { + remote-endpoint = <&edp0_connector_in>; + }; + }; + }; +}; + +&mdss0_dp2_phy { + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss0_dp3 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss0_dp3_phy_out: endpoint { + remote-endpoint = <&edp1_connector_in>; + }; + }; + }; +}; + +&mdss0_dp3_phy { + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1 { + status = "okay"; +}; + +&mdss1_dp0 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp0_phy_out: endpoint { + remote-endpoint = <&dp2_connector_in>; + }; + }; + }; +}; + +&mdss1_dp0_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1_dp1 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp1_phy_out: endpoint { + remote-endpoint = <&dp3_connector_in>; + }; + }; + }; +}; + +&mdss1_dp1_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1_dp2 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp2_phy_out: endpoint { + remote-endpoint = <&edp2_connector_in>; + }; + }; + }; +}; + +&mdss1_dp2_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1_dp3 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp3_phy_out: endpoint { + remote-endpoint = <&edp3_connector_in>; + }; + }; + }; +}; + +&mdss1_dp3_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + &pcie2a { perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; From patchwork Tue Jan 10 14:57:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 13095243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7244C46467 for ; Tue, 10 Jan 2023 14:58:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238716AbjAJO6N (ORCPT ); Tue, 10 Jan 2023 09:58:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233114AbjAJO6K (ORCPT ); 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Tue, 10 Jan 2023 14:57:59 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30AEvwaR007679 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 10 Jan 2023 14:57:58 GMT Received: from hu-bjorande-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 10 Jan 2023 06:57:58 -0800 From: Bjorn Andersson To: Bjorn Andersson , Konrad Dybcio , Johan Hovold CC: Dmitry Baryshkov , , , , Subject: [PATCH v6 4/4] arm64: defconfig: Enable SC8280XP Display Clock Controller Date: Tue, 10 Jan 2023 06:57:51 -0800 Message-ID: <20230110145751.2654795-5-quic_bjorande@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230110145751.2654795-1-quic_bjorande@quicinc.com> References: <20230110145751.2654795-1-quic_bjorande@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: SpktMfXcCR_d_iuWbNdylVyiEp-hzRk6 X-Proofpoint-GUID: SpktMfXcCR_d_iuWbNdylVyiEp-hzRk6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-10_06,2023-01-10_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 adultscore=0 spamscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301100093 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Display Clock Controller provides clocks and power-domains for the display subsystem, enable this to enable display on the SC8280XP. Now that power-domains can probe defer past late_initcall() this should be possible to leave as module. Signed-off-by: Bjorn Andersson Acked-by: Konrad Dybcio --- Changes since v5: - New patch arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 340199714874..43df50a044ce 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1100,6 +1100,7 @@ CONFIG_MSM_GCC_8994=y CONFIG_MSM_MMCC_8996=y CONFIG_MSM_GCC_8998=y CONFIG_QCS_GCC_404=y +CONFIG_SC_DISPCC_8280XP=m CONFIG_SC_GCC_7180=y CONFIG_SC_GCC_7280=y CONFIG_SC_GCC_8180X=y