From patchwork Wed Jan 11 08:21:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naman Jain X-Patchwork-Id: 13096247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E1EEC46467 for ; Wed, 11 Jan 2023 08:22:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231861AbjAKIWc (ORCPT ); Wed, 11 Jan 2023 03:22:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231997AbjAKIW2 (ORCPT ); Wed, 11 Jan 2023 03:22:28 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9845364ED; Wed, 11 Jan 2023 00:22:26 -0800 (PST) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30B7Wn9j006570; Wed, 11 Jan 2023 08:22:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=X4kMJ7lGqg4ERoxmcSf1cIw1DJKzOZ4Ph7v10sowEmc=; b=MRBrzyIa6WEeC0OsKqeHRfeXiJ7oVa3QKsZWFNiAS1aJc2pJ+Rq0T3nEjtvnqECelmr8 0+WeR/ZsT+5zSZUWIGR1eYJUjJgEs4xABxFGV+5smD/7UoAUZ+u54Ejhd3oRlRht8pcg 24k1KoihIvtfYAngNhDzK3uQQGbusGNtmrf7lOLquK38pyzCruJ4o/xDYSCgv3UbnVCc Iz8yTeuB3F1zY5ghV+YBcr5i0fr1P0qZoD0G4fVwaardWZ+WHSpwDicjTGwCJkfaiSqw HOudm4uWiWh4gCYqBfBA5foKOntp5Nms/AVt+a/QTaq5Te5mMxRkdwgnK5S811Yh40kW dg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3n1k7qrqy5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Jan 2023 08:22:14 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30B8MDAq021340 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Jan 2023 08:22:13 GMT Received: from hu-namajain-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 11 Jan 2023 00:22:10 -0800 From: Naman Jain To: Bjorn Andersson , Andy Gross , Konrad Dybcio CC: Naman Jain , , , Subject: [PATCH 1/2] soc: qcom: socinfo: Change socinfo variable name and scope Date: Wed, 11 Jan 2023 13:51:40 +0530 Message-ID: <20230111082141.18109-2-quic_namajain@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230111082141.18109-1-quic_namajain@quicinc.com> References: <20230111082141.18109-1-quic_namajain@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: IH2hRJKsGfRYSu6-8ddV1l5FiWjnFDUF X-Proofpoint-ORIG-GUID: IH2hRJKsGfRYSu6-8ddV1l5FiWjnFDUF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-11_03,2023-01-10_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 adultscore=0 malwarescore=0 clxscore=1015 impostorscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301110062 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change socinfo structure variable scope from function to file to make it easy to support custom attributes for sysfs. Also, change variable name to make it more descriptive. Signed-off-by: Naman Jain --- drivers/soc/qcom/socinfo.c | 80 ++++++++++++++++++++------------------ 1 file changed, 42 insertions(+), 38 deletions(-) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 10efdbcfdf05..251c0fd94962 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -175,6 +175,7 @@ struct socinfo { __le32 npartnamemap_offset; __le32 nnum_partname_mapping; }; +static struct socinfo *soc_info; #ifdef CONFIG_DEBUG_FS struct socinfo_params { @@ -502,7 +503,7 @@ DEFINE_IMAGE_OPS(variant); DEFINE_IMAGE_OPS(oem); static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, - struct socinfo *info, size_t info_size) + size_t info_size) { struct smem_image_version *versions; struct dentry *dentry; @@ -513,15 +514,15 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL); - qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt); + qcom_socinfo->info.fmt = __le32_to_cpu(soc_info->fmt); debugfs_create_x32("info_fmt", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.fmt); switch (qcom_socinfo->info.fmt) { case SOCINFO_VERSION(0, 16): - qcom_socinfo->info.feature_code = __le32_to_cpu(info->feature_code); - qcom_socinfo->info.pcode = __le32_to_cpu(info->pcode); + qcom_socinfo->info.feature_code = __le32_to_cpu(soc_info->feature_code); + qcom_socinfo->info.pcode = __le32_to_cpu(soc_info->pcode); debugfs_create_u32("feature_code", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.feature_code); @@ -529,16 +530,20 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, &qcom_socinfo->info.pcode); fallthrough; case SOCINFO_VERSION(0, 15): - qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported); + qcom_socinfo->info.nmodem_supported = __le32_to_cpu(soc_info->nmodem_supported); debugfs_create_u32("nmodem_supported", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.nmodem_supported); fallthrough; case SOCINFO_VERSION(0, 14): - qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters); - qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset); - qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts); - qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset); + qcom_socinfo->info.num_clusters = + __le32_to_cpu(soc_info->num_clusters); + qcom_socinfo->info.ncluster_array_offset = + __le32_to_cpu(soc_info->ncluster_array_offset); + qcom_socinfo->info.num_defective_parts = + __le32_to_cpu(soc_info->num_defective_parts); + qcom_socinfo->info.ndefective_parts_array_offset = + __le32_to_cpu(soc_info->ndefective_parts_array_offset); debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.num_clusters); @@ -550,19 +555,19 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, &qcom_socinfo->info.ndefective_parts_array_offset); fallthrough; case SOCINFO_VERSION(0, 13): - qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id); + qcom_socinfo->info.nproduct_id = __le32_to_cpu(soc_info->nproduct_id); debugfs_create_u32("nproduct_id", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.nproduct_id); - DEBUGFS_ADD(info, chip_id); + DEBUGFS_ADD(soc_info, chip_id); fallthrough; case SOCINFO_VERSION(0, 12): qcom_socinfo->info.chip_family = - __le32_to_cpu(info->chip_family); + __le32_to_cpu(soc_info->chip_family); qcom_socinfo->info.raw_device_family = - __le32_to_cpu(info->raw_device_family); + __le32_to_cpu(soc_info->raw_device_family); qcom_socinfo->info.raw_device_num = - __le32_to_cpu(info->raw_device_num); + __le32_to_cpu(soc_info->raw_device_num); debugfs_create_x32("chip_family", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.chip_family); @@ -574,26 +579,26 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, &qcom_socinfo->info.raw_device_num); fallthrough; case SOCINFO_VERSION(0, 11): - num_pmics = le32_to_cpu(info->num_pmics); - pmic_array_offset = le32_to_cpu(info->pmic_array_offset); + num_pmics = le32_to_cpu(soc_info->num_pmics); + pmic_array_offset = le32_to_cpu(soc_info->pmic_array_offset); if (pmic_array_offset + 2 * num_pmics * sizeof(u32) <= info_size) - DEBUGFS_ADD(info, pmic_model_array); + DEBUGFS_ADD(soc_info, pmic_model_array); fallthrough; case SOCINFO_VERSION(0, 10): case SOCINFO_VERSION(0, 9): - qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id); + qcom_socinfo->info.foundry_id = __le32_to_cpu(soc_info->foundry_id); debugfs_create_u32("foundry_id", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.foundry_id); fallthrough; case SOCINFO_VERSION(0, 8): case SOCINFO_VERSION(0, 7): - DEBUGFS_ADD(info, pmic_model); - DEBUGFS_ADD(info, pmic_die_rev); + DEBUGFS_ADD(soc_info, pmic_model); + DEBUGFS_ADD(soc_info, pmic_die_rev); fallthrough; case SOCINFO_VERSION(0, 6): qcom_socinfo->info.hw_plat_subtype = - __le32_to_cpu(info->hw_plat_subtype); + __le32_to_cpu(soc_info->hw_plat_subtype); debugfs_create_u32("hardware_platform_subtype", 0444, qcom_socinfo->dbg_root, @@ -601,34 +606,34 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, fallthrough; case SOCINFO_VERSION(0, 5): qcom_socinfo->info.accessory_chip = - __le32_to_cpu(info->accessory_chip); + __le32_to_cpu(soc_info->accessory_chip); debugfs_create_u32("accessory_chip", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.accessory_chip); fallthrough; case SOCINFO_VERSION(0, 4): - qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver); + qcom_socinfo->info.plat_ver = __le32_to_cpu(soc_info->plat_ver); debugfs_create_u32("platform_version", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.plat_ver); fallthrough; case SOCINFO_VERSION(0, 3): - qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat); + qcom_socinfo->info.hw_plat = __le32_to_cpu(soc_info->hw_plat); debugfs_create_u32("hardware_platform", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.hw_plat); fallthrough; case SOCINFO_VERSION(0, 2): - qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver); + qcom_socinfo->info.raw_ver = __le32_to_cpu(soc_info->raw_ver); debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root, &qcom_socinfo->info.raw_ver); fallthrough; case SOCINFO_VERSION(0, 1): - DEBUGFS_ADD(info, build_id); + DEBUGFS_ADD(soc_info, build_id); break; } @@ -656,7 +661,7 @@ static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) } #else static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, - struct socinfo *info, size_t info_size) + size_t info_size) { } static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { } @@ -665,14 +670,13 @@ static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { } static int qcom_socinfo_probe(struct platform_device *pdev) { struct qcom_socinfo *qs; - struct socinfo *info; size_t item_size; - info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, + soc_info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, &item_size); - if (IS_ERR(info)) { + if (IS_ERR(soc_info)) { dev_err(&pdev->dev, "Couldn't find socinfo\n"); - return PTR_ERR(info); + return PTR_ERR(soc_info); } qs = devm_kzalloc(&pdev->dev, sizeof(*qs), GFP_KERNEL); @@ -681,25 +685,25 @@ static int qcom_socinfo_probe(struct platform_device *pdev) qs->attr.family = "Snapdragon"; qs->attr.machine = socinfo_machine(&pdev->dev, - le32_to_cpu(info->id)); + le32_to_cpu(soc_info->id)); qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u", - le32_to_cpu(info->id)); + le32_to_cpu(soc_info->id)); qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u", - SOCINFO_MAJOR(le32_to_cpu(info->ver)), - SOCINFO_MINOR(le32_to_cpu(info->ver))); + SOCINFO_MAJOR(le32_to_cpu(soc_info->ver)), + SOCINFO_MINOR(le32_to_cpu(soc_info->ver))); if (offsetof(struct socinfo, serial_num) <= item_size) qs->attr.serial_number = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u", - le32_to_cpu(info->serial_num)); + le32_to_cpu(soc_info->serial_num)); qs->soc_dev = soc_device_register(&qs->attr); if (IS_ERR(qs->soc_dev)) return PTR_ERR(qs->soc_dev); - socinfo_debugfs_init(qs, info, item_size); + socinfo_debugfs_init(qs, item_size); /* Feed the soc specific unique data into entropy pool */ - add_device_randomness(info, item_size); + add_device_randomness(soc_info, item_size); platform_set_drvdata(pdev, qs); From patchwork Wed Jan 11 08:21:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naman Jain X-Patchwork-Id: 13096246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69C2BC46467 for ; Wed, 11 Jan 2023 08:22:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231947AbjAKIW1 (ORCPT ); Wed, 11 Jan 2023 03:22:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229509AbjAKIWY (ORCPT ); Wed, 11 Jan 2023 03:22:24 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86CDE6575; Wed, 11 Jan 2023 00:22:23 -0800 (PST) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30B6s1cc011232; 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Wed, 11 Jan 2023 08:22:18 GMT Received: from hu-namajain-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 11 Jan 2023 00:22:15 -0800 From: Naman Jain To: Bjorn Andersson , Andy Gross , Konrad Dybcio CC: Naman Jain , , , Subject: [PATCH 2/2] soc: qcom: socinfo: Add sysfs attributes for fields in v2-v6 Date: Wed, 11 Jan 2023 13:51:41 +0530 Message-ID: <20230111082141.18109-3-quic_namajain@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230111082141.18109-1-quic_namajain@quicinc.com> References: <20230111082141.18109-1-quic_namajain@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: odWvLrK10hfoMPJ8jvWJeEErqs9czW0c X-Proofpoint-GUID: odWvLrK10hfoMPJ8jvWJeEErqs9czW0c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2023-01-11_03,2023-01-10_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 bulkscore=0 impostorscore=0 adultscore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301110062 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support in sysfs custom attributes for fields in socinfo version v2-v6. This is to support SoC based operations in userland scripts and test scripts. Also, add name mappings for hw-platform type to make the sysfs information more descriptive. Signed-off-by: Naman Jain --- drivers/soc/qcom/socinfo.c | 181 +++++++++++++++++++++++++++++++++++++ 1 file changed, 181 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 251c0fd94962..ff92064c2246 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -41,6 +41,52 @@ */ #define SMEM_HW_SW_BUILD_ID 137 +enum { + HW_PLATFORM_UNKNOWN = 0, + HW_PLATFORM_SURF = 1, + HW_PLATFORM_FFA = 2, + HW_PLATFORM_FLUID = 3, + HW_PLATFORM_SVLTE_FFA = 4, + HW_PLATFORM_SVLTE_SURF = 5, + HW_PLATFORM_MTP_MDM = 7, + HW_PLATFORM_MTP = 8, + HW_PLATFORM_LIQUID = 9, + HW_PLATFORM_DRAGON = 10, + HW_PLATFORM_QRD = 11, + HW_PLATFORM_HRD = 13, + HW_PLATFORM_DTV = 14, + HW_PLATFORM_RCM = 21, + HW_PLATFORM_STP = 23, + HW_PLATFORM_SBC = 24, + HW_PLATFORM_HDK = 31, + HW_PLATFORM_ATP = 33, + HW_PLATFORM_IDP = 34, + HW_PLATFORM_INVALID +}; + +static const char * const hw_platform[] = { + [HW_PLATFORM_UNKNOWN] = "Unknown", + [HW_PLATFORM_SURF] = "Surf", + [HW_PLATFORM_FFA] = "FFA", + [HW_PLATFORM_FLUID] = "Fluid", + [HW_PLATFORM_SVLTE_FFA] = "SVLTE_FFA", + [HW_PLATFORM_SVLTE_SURF] = "SLVTE_SURF", + [HW_PLATFORM_MTP_MDM] = "MDM_MTP_NO_DISPLAY", + [HW_PLATFORM_MTP] = "MTP", + [HW_PLATFORM_RCM] = "RCM", + [HW_PLATFORM_LIQUID] = "Liquid", + [HW_PLATFORM_DRAGON] = "Dragon", + [HW_PLATFORM_QRD] = "QRD", + [HW_PLATFORM_HRD] = "HRD", + [HW_PLATFORM_DTV] = "DTV", + [HW_PLATFORM_STP] = "STP", + [HW_PLATFORM_SBC] = "SBC", + [HW_PLATFORM_HDK] = "HDK", + [HW_PLATFORM_ATP] = "ATP", + [HW_PLATFORM_IDP] = "IDP", + [HW_PLATFORM_INVALID] = "Invalid", +}; + #ifdef CONFIG_DEBUG_FS #define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32 #define SMEM_IMAGE_VERSION_SIZE 4096 @@ -368,6 +414,140 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QRU1062) }, }; +/* sysfs attributes */ +#define ATTR_DEFINE(param) \ + static DEVICE_ATTR(param, 0644, qcom_get_##param, NULL) + +/* Version 2 */ +static ssize_t +qcom_get_raw_id(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%u\n", + le32_to_cpu(soc_info->raw_id)); +} +ATTR_DEFINE(raw_id); + +static ssize_t +qcom_get_raw_version(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%u\n", + le32_to_cpu(soc_info->raw_ver)); +} +ATTR_DEFINE(raw_version); + +/* Version 3 */ +static ssize_t +qcom_get_hw_platform(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + uint32_t hw_plat = le32_to_cpu(soc_info->hw_plat); + + hw_plat = (hw_plat >= HW_PLATFORM_INVALID) ? HW_PLATFORM_INVALID : hw_plat; + return scnprintf(buf, PAGE_SIZE, "%-.32s\n", + hw_platform[hw_plat]); +} +ATTR_DEFINE(hw_platform); + +/* Version 4 */ +static ssize_t +qcom_get_platform_version(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%u\n", + le32_to_cpu(soc_info->plat_ver)); +} +ATTR_DEFINE(platform_version); + +/* Version 5 */ +static ssize_t +qcom_get_accessory_chip(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%u\n", + le32_to_cpu(soc_info->accessory_chip)); +} +ATTR_DEFINE(accessory_chip); + +/* Version 6 */ +static ssize_t +qcom_get_platform_subtype_id(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%u\n", + le32_to_cpu(soc_info->hw_plat_subtype)); +} +ATTR_DEFINE(platform_subtype_id); + +static struct attribute *qcom_custom_socinfo_attrs[7]; + +static const struct attribute_group custom_soc_attr_group = { + .attrs = qcom_custom_socinfo_attrs, +}; + +static void qcom_socinfo_populate_sysfs(struct qcom_socinfo *qcom_socinfo) +{ + int i = 0, socinfo_format = le32_to_cpu(soc_info->fmt); + + /* Note: qcom_custom_socinfo_attrs[] size needs to be in sync with attributes added here. */ + switch (socinfo_format) { + case SOCINFO_VERSION(0, 16): + fallthrough; + case SOCINFO_VERSION(0, 15): + fallthrough; + case SOCINFO_VERSION(0, 14): + fallthrough; + case SOCINFO_VERSION(0, 13): + fallthrough; + case SOCINFO_VERSION(0, 12): + fallthrough; + case SOCINFO_VERSION(0, 11): + fallthrough; + case SOCINFO_VERSION(0, 10): + fallthrough; + case SOCINFO_VERSION(0, 9): + fallthrough; + case SOCINFO_VERSION(0, 8): + fallthrough; + case SOCINFO_VERSION(0, 7): + fallthrough; + case SOCINFO_VERSION(0, 6): + qcom_custom_socinfo_attrs[i++] = + &dev_attr_platform_subtype_id.attr; + fallthrough; + case SOCINFO_VERSION(0, 5): + qcom_custom_socinfo_attrs[i++] = &dev_attr_accessory_chip.attr; + fallthrough; + case SOCINFO_VERSION(0, 4): + qcom_custom_socinfo_attrs[i++] = &dev_attr_platform_version.attr; + fallthrough; + case SOCINFO_VERSION(0, 3): + qcom_custom_socinfo_attrs[i++] = &dev_attr_hw_platform.attr; + fallthrough; + case SOCINFO_VERSION(0, 2): + qcom_custom_socinfo_attrs[i++] = &dev_attr_raw_id.attr; + qcom_custom_socinfo_attrs[i++] = &dev_attr_raw_version.attr; + fallthrough; + case SOCINFO_VERSION(0, 1): + break; + default: + pr_err("Unknown socinfo format: v%u.%u\n", + SOCINFO_MAJOR(socinfo_format), + SOCINFO_MINOR(socinfo_format)); + break; + } + + qcom_custom_socinfo_attrs[i] = NULL; + qcom_socinfo->attr.custom_attr_group = &custom_soc_attr_group; +} + static const char *socinfo_machine(struct device *dev, unsigned int id) { int idx; @@ -696,6 +876,7 @@ static int qcom_socinfo_probe(struct platform_device *pdev) "%u", le32_to_cpu(soc_info->serial_num)); + qcom_socinfo_populate_sysfs(qs); qs->soc_dev = soc_device_register(&qs->attr); if (IS_ERR(qs->soc_dev)) return PTR_ERR(qs->soc_dev);