From patchwork Wed Jan 11 23:55:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13097310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05768C63797 for ; Wed, 11 Jan 2023 23:56:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 934EA10E842; Wed, 11 Jan 2023 23:56:27 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id B611310E176 for ; Wed, 11 Jan 2023 23:56:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673481375; x=1705017375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9GDlP8Sc3SUymk9YKzNteEdxBMuUq0q6vRFLRcKS+14=; b=PUPz2RZC2O1t/s7mciIKFWAe34RzXHo6AL6NAD6mlcCy5v3pcjqg7o1S U6nD2G6TDJcjTXgbs5rdD9Xs3GYgmMX+HeK3ZfqjhDsIxUOIGxH0x6/yD Zq4XrUHdY702v1lHGtMwZTh7qK1XZ2mw0qMiCrPS9iI7EbXjffuIAXCTr m98449TYI4nrgTF4kro5NJq/hc7dyJSl+bJaDCTY8a9JkSfgDGeq8yH8g Nc9v/XjUCYrYk5QYGeN8UxZRlXxdWascujYHkgBraDXrS9D0rAqJtLAmd cObE7iQoFW87fLGIEEGsSNToPeimOaW+D2SFbiQgobyKhfxAqR8l6GmqG w==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="307090895" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="307090895" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831486365" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="831486365" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Jan 2023 15:55:23 -0800 Message-Id: <20230111235531.3353815-2-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> References: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH dii-client 1/9] drm/i915/mtl: Fix bcs default context X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Lucas De Marchi Commit 0d0e7d1eea9e ("drm/i915/mtl: Define engine context layouts") added the engine context for Meteor Lake. In a second revision of the patch it was believed the xcs offsets were wrong due to a tagging issue in the spec. The first version was actually correct, as shown by the intel_lrc_live_selftests/live_lrc_layout test: i915: Running gt_lrc i915: Running intel_lrc_live_selftests/live_lrc_layout bcs0: LRI command mismatch at dword 1, expected 1108101d found 11081019 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:236:DP-1] disconnected bcs0: HW register image: [0000] 00000000 1108101d 00022244 ffff0008 00022034 00000088 00022030 00000088 ... bcs0: SW register image: [0000] 00000000 11081019 00022244 00090009 00022034 00000000 00022030 00000000 The difference in the 2 additional dwords (0x1d vs 0x19) are the offsets 0x120 / 0x124 that are indeed part of the context image. Bspec: 45585 Fixes: 0d0e7d1eea9e ("drm/i915/mtl: Define engine context layouts") Signed-off-by: Lucas De Marchi Signed-off-by: Radhakrishna Sripada Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_lrc.c | 37 +---------------------------- 1 file changed, 1 insertion(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 7771a19008c6..bbeeb6dde7ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -288,39 +288,6 @@ static const u8 dg2_xcs_offsets[] = { END }; -static const u8 mtl_xcs_offsets[] = { - NOP(1), - LRI(13, POSTED), - REG16(0x244), - REG(0x034), - REG(0x030), - REG(0x038), - REG(0x03c), - REG(0x168), - REG(0x140), - REG(0x110), - REG(0x1c0), - REG(0x1c4), - REG(0x1c8), - REG(0x180), - REG16(0x2b4), - NOP(4), - - NOP(1), - LRI(9, POSTED), - REG16(0x3a8), - REG16(0x28c), - REG16(0x288), - REG16(0x284), - REG16(0x280), - REG16(0x27c), - REG16(0x278), - REG16(0x274), - REG16(0x270), - - END -}; - static const u8 gen8_rcs_offsets[] = { NOP(1), LRI(14, POSTED), @@ -739,9 +706,7 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine) else return gen8_rcs_offsets; } else { - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) - return mtl_xcs_offsets; - else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) return dg2_xcs_offsets; else if (GRAPHICS_VER(engine->i915) >= 12) return gen12_xcs_offsets; From patchwork Wed Jan 11 23:55:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13097302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2484C46467 for ; Wed, 11 Jan 2023 23:56:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 35D1910E170; Wed, 11 Jan 2023 23:56:17 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3695010E170 for ; Wed, 11 Jan 2023 23:56:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673481375; x=1705017375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nNq5VdyZ6gdn8uc6W6TeHGITiRXB8zfC8f6es86Wlqw=; b=Lc1jUsQb/XQucC3jKB4xwaFWG1VqOmpeIIfkKpGVbFLMKC5vQsScJp77 n+O3TESvmpZuPWYm0ZzqhzohJzXS0I3eFmjB57KBFlfa0D94b4+Wo/aUB yIGOJtw4vA6oL+JAvsRx5XIm5NsQDzRTiEYymd7NP1a2uCQUcNyBTngmp DQvxGuCXDaL5OvQ5erJCyFZCu2tuo9+nh/eNhyLtygKHJf3V3uW5Fs7Gy EtcE9bJL+r9SUPHG8hhdH1eGpOiyySxxNY9EnqoSfc65RJpn3nc6mtdqu olMZ/DIdl5c5OD4JL5l8XyX2UWGBeOJ3jV9GwUg3nSzW2IQdJHwc5EbEe Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="307090893" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="307090893" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831486369" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="831486369" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Jan 2023 15:55:24 -0800 Message-Id: <20230111235531.3353815-3-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> References: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH dii-client 2/9] drm/i915/mtl: Initialize empty clockgating hooks for MTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Clock gating hooks to be initialized for MTL are yet to be implemented. Use a nop till we identify relevant WA's here. Signed-off-by: Radhakrishna Sripada Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/intel_pm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 73c88b1c9545..41046ceca9db 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4819,7 +4819,9 @@ CG_FUNCS(nop); */ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) { - if (IS_PONTEVECCHIO(dev_priv)) + if (IS_METEORLAKE(dev_priv)) + dev_priv->clock_gating_funcs = &nop_clock_gating_funcs; + else if (IS_PONTEVECCHIO(dev_priv)) dev_priv->clock_gating_funcs = &pvc_clock_gating_funcs; else if (IS_DG2(dev_priv)) dev_priv->clock_gating_funcs = &dg2_clock_gating_funcs; From patchwork Wed Jan 11 23:55:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13097303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2B4EC5479D for ; Wed, 11 Jan 2023 23:56:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA68810E176; Wed, 11 Jan 2023 23:56:17 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 891C910E170 for ; Wed, 11 Jan 2023 23:56:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673481375; x=1705017375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0FEhvZ6H4P/KJn4azfOTcreWoiM4JWXcv6Iu4OptvLU=; b=KG3v1QDnreYgvVARNf9CtbPyD29TOJTgR+VLEl+vNBM73mQbpc7X25Iq Qmudk+aMVcxzGDgokagr1g55ZUgviq7aGhmnkErkWfMa8vYCEE1+7E0hK ZegSV0gcD7qZcDGq59dMPagAAkCnKPUsLsMAHWngP+8V6CGgH9bNolIbj AO/beD+3h6vWTWn2r6UmKfBjmh8YOcYzI26tg23bej0gZxKBdvexogcx+ mSJR/y+hySDHvP5IR1kY8gGwLrr4aHQVPyM8iuL1kC7jhvjf3lp4sZ0xe 6KYORU1B/3LqviGA/Yli79F2w6Z1+Q8KrDzfTB8HEbE0yggJUY0CZ7qY6 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="307090894" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="307090894" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831486372" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="831486372" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Jan 2023 15:55:25 -0800 Message-Id: <20230111235531.3353815-4-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> References: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH dii-client 3/9] drm/i915/mtl: Fix Wa_14015855405 implementation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The patch "2357f2b271ad drm/i915/mtl: Initial display workarounds" extended the workaround Wa_16015201720 to MTL. However the registers that the original WA implamented moved for MTL. Implement the workaround with the correct register. Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds") Cc: Matt Atwood Cc: Lucas De Marchi Signed-off-by: Radhakrishna Sripada Reviewed-by: Balasubramani Vivekanandan --- drivers/gpu/drm/i915/display/intel_dmc.c | 35 ++++++++++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 10 +++++-- 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 4124b3d37110..216915256eb6 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -372,15 +372,12 @@ static void disable_all_event_handlers(struct drm_i915_private *i915) } } -static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) +static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) { enum pipe pipe; - if (DISPLAY_VER(i915) < 13) - return; - /* - * Wa_16015201720:adl-p,dg2, mtl + * Wa_16015201720:adl-p,dg2 * The WA requires clock gating to be disabled all the time * for pipe A and B. * For pipe C and D clock gating needs to be disabled only @@ -396,6 +393,34 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) PIPEDMC_GATING_DIS, 0); } +static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) +{ + /* + * Wa_14015855405 + * The WA requires clock gating to be disabled all the time + * for pipe A and B. + * For pipe C and D clock gating needs to be disabled only + * during initializing the firmware. + * TODO/FIXME: WA deviates wrt. enable/disable for Pipes C, D. Needs recheck. + * For now carry-forward the implementation for dg2. + */ + if (enable) + intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, + MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B | + MTL_PIPEDMC_GATING_DIS_C | MTL_PIPEDMC_GATING_DIS_D); + else + intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, + MTL_PIPEDMC_GATING_DIS_C | MTL_PIPEDMC_GATING_DIS_D, 0); +} + +static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) +{ + if (DISPLAY_VER(i915) >= 14) + return mtl_pipedmc_clock_gating_wa(i915, enable); + else if (DISPLAY_VER(i915) == 13) + return adlp_pipedmc_clock_gating_wa(i915, enable); +} + /** * intel_dmc_load_program() - write the firmware from memory to register. * @dev_priv: i915 drm device. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8b2cf980f323..d43f0f8e061c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1786,9 +1786,13 @@ * GEN9 clock gating regs */ #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) -#define DARBF_GATING_DIS (1 << 27) -#define PWM2_GATING_DIS (1 << 14) -#define PWM1_GATING_DIS (1 << 13) +#define DARBF_GATING_DIS REG_BIT(27) +#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15) +#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14) +#define PWM2_GATING_DIS REG_BIT(14) +#define MTL_PIPEDMC_GATING_DIS_C REG_BIT(13) +#define PWM1_GATING_DIS REG_BIT(13) +#define MTL_PIPEDMC_GATING_DIS_D REG_BIT(12) #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) #define TGL_VRH_GATING_DIS REG_BIT(31) From patchwork Wed Jan 11 23:55:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13097309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0452FC46467 for ; Wed, 11 Jan 2023 23:56:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6ABAE10E841; Wed, 11 Jan 2023 23:56:26 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 17D0B10E176 for ; Wed, 11 Jan 2023 23:56:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673481376; x=1705017376; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VeEEMEfaDJi7WipJm4u0djyub4z8+tTttj8kY2PiqJk=; b=HrB5NCUuUwh63L/BEmFM+S302yYR68pQGwZ9z5mEjozcwI0ZHzjG3MZO Chv4b7K2I9rasRza+PeO1loJV8U+RuV8ddMoHv87eNr7Y39Q7GBGvUIKS WJadbeBGkhY4r30wAGfuR90MCkXUqyZL/BjZNZpxT86dlL2/Iz5yE+m9P 0v6wv/V/S8FaQOXj8JBgg8kZQh/AHatCZnAQi+DuLgrCkChhRqgA+N5Kg EZS3JYWJrsB30SpL/aui86ZwolOP5zfUjAbJ0jlLdMaMM5yyzZ4BXERFQ HvYKeUiwlaZUKZvuSFXinyVsGEb+KLYLKEy384VGfzwmcNi8T9DvVki5O Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="307090897" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="307090897" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831486376" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="831486376" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Jan 2023 15:55:26 -0800 Message-Id: <20230111235531.3353815-5-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> References: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH dii-client 4/9] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Paulo Zanoni Meteorlake has separate Media and render gt, it is necessary to process the interrupts for the gt separately. As part of it make sure IRQ reset and postinstall also work on Media gt. Signed-off-by: Paulo Zanoni Signed-off-by: Tvrtko Ursulin Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 54ea28cf8a1a..26d176ec4a66 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3170,14 +3170,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv) { struct intel_gt *gt = to_gt(dev_priv); struct intel_uncore *uncore = gt->uncore; + unsigned int i; dg1_master_intr_disable(dev_priv->uncore.regs); - gen11_gt_irq_reset(gt); - gen11_display_irq_reset(dev_priv); + for_each_gt(gt, dev_priv, i) { + gen11_gt_irq_reset(gt); - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); - GEN3_IRQ_RESET(uncore, GEN8_PCU_); + uncore = gt->uncore; + GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); + GEN3_IRQ_RESET(uncore, GEN8_PCU_); + } + + gen11_display_irq_reset(dev_priv); } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, @@ -3837,13 +3842,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) { - struct intel_gt *gt = to_gt(dev_priv); - struct intel_uncore *uncore = gt->uncore; u32 gu_misc_masked = GEN11_GU_MISC_GSE; + struct intel_gt *gt; + unsigned int i; - gen11_gt_irq_postinstall(gt); + for_each_gt(gt, dev_priv, i) { + gen11_gt_irq_postinstall(gt); - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked, + gu_misc_masked); + } if (HAS_DISPLAY(dev_priv)) { icp_irq_postinstall(dev_priv); @@ -3852,8 +3860,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) GEN11_DISPLAY_IRQ_ENABLE); } - dg1_master_intr_enable(uncore->regs); - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs); + intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR); } static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) From patchwork Wed Jan 11 23:55:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13097306 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A1B1C54EBC for ; Wed, 11 Jan 2023 23:56:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E72610E83E; Wed, 11 Jan 2023 23:56:20 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4193910E838 for ; Wed, 11 Jan 2023 23:56:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673481376; x=1705017376; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K0ux4J3aJ283Z6NQWZc+KUG7MV9Kn6PfbuHN6h1lPAU=; b=K7o2ddZMU1XfkKwWfIQm05aVV+JOKYpH/iYcmLfClncYW4h8U8RzeVU6 QIdyxMNAEZ/6IBtGMkPHLarKonVYatWnh0iGEbhDx2Y+7ubnb/s/U+VTe cmBRc56/9gaDZd+InpkCTtdDNFmUjVNbtzRem8H+B8oTfDIdZjr+yBySr MotL2ZqT/H/FH7QEouftvzuSG05tp0aywLsnBenUIN79j0RNE3BZBYywg ycC00xTR+u1G8uiNoTh+LGp377JEhxs+Me8zMtfyZjwEJs9oQjW5JeUmU 706AxCOhaYYM6Cdd6gdxRvsAYyw/J9Y+MmUQTPI9ftlFnYVgbv4x4hBxu A==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="307090900" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="307090900" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831486378" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="831486378" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Jan 2023 15:55:27 -0800 Message-Id: <20230111235531.3353815-6-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> References: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH dii-client 5/9] drm/i915/gt: generate per gt debugfs files X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Andi Shyti In the view of multi-gt we want independent per gt debug files. In debugfs create gt0/ gt1/ ... gtN/ for gt related files. In platforms with 2 gt's, the debugfs would be structured as follows: /sys/kernel/debug/dri └── 0    ├── gt0    │   ├── drpc    │   ├── engines    │   ├── forcewake    │   ├── frequency    │   └── rps_boost    └─- gt1    :   ├── drpc    :   ├── engines    :   ├── forcewake       ├── frequency       └── rps_boost Cc: Tvrtko Ursulin Signed-off-by: Andi Shyti Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 +++- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 5 ++++- drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++ 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c index 5fc2df01aa0d..4dc23b8d3aa2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c @@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root) void intel_gt_debugfs_register(struct intel_gt *gt) { struct dentry *root; + char gtname[4]; if (!gt->i915->drm.primary->debugfs_root) return; - root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root); + snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id); + root = debugfs_create_dir(gtname, gt->i915->drm.primary->debugfs_root); if (IS_ERR(root)) return; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index bb4dfe707a7d..e46aac1a41e6 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -42,6 +42,8 @@ struct intel_guc { /** @capture: the error-state-capture module's data and objects */ struct intel_guc_state_capture *capture; + struct dentry *dbgfs_node; + /** @sched_engine: Global engine used to submit requests to GuC */ struct i915_sched_engine *sched_engine; /** diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c index 68331c538b0a..71b1f23b64c1 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c @@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log) */ n_subbufs = 8; + if (!guc->dbgfs_node) + return -ENOENT; + guc_log_relay_chan = relay_open("guc_log", - dev_priv->drm.primary->debugfs_root, + guc->dbgfs_node, subbuf_size, n_subbufs, &relay_callbacks, dev_priv); if (!guc_log_relay_chan) { diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c index 284d6fbc2d08..2f93cc4e408a 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c @@ -54,6 +54,8 @@ void intel_uc_debugfs_register(struct intel_uc *uc, struct dentry *gt_root) if (IS_ERR(root)) return; + uc->guc.dbgfs_node = root; + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), uc); intel_guc_debugfs_register(&uc->guc, root); From patchwork Wed Jan 11 23:55:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13097308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC551C54EBC for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="307090901" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="307090901" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831486382" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="831486382" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Jan 2023 15:55:28 -0800 Message-Id: <20230111235531.3353815-7-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> References: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH dii-client 6/9] drm/i915/debugfs: Multiplex upper layer interfaces to act on all gt's X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Andi Shyti Commit 82a149a62b6b5 ('drm/i915/gt: move remaining debugfs interfaces into gt') moves gt related debugfs files in the gtX/ directories to act on specific gt's individually. The original files are kept intact in the same location in order to not break userspace users. But they were performing only on the root tile (tile 0). Add a multiplexing functionality to the higher directories files so that they can perform the operations on all the tiles in a with a single write. In the read case they provide an or'ed value amongst the tiles. Cc: Maciej Patelczyk Signed-off-by: Andi Shyti Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_debugfs.c | 38 ++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index a356ca490159..d64e9e3a439d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -575,14 +575,36 @@ static int i915_wa_registers(struct seq_file *m, void *unused) static int i915_wedged_get(void *data, u64 *val) { struct drm_i915_private *i915 = data; + struct intel_gt *gt; + unsigned int i; - return intel_gt_debugfs_reset_show(to_gt(i915), val); + *val = 0; + + for_each_gt(gt, i915, i) { + int ret; + u64 v; + + ret = intel_gt_debugfs_reset_show(gt, &v); + if (ret) + return ret; + + /* at least one tile should be wedged */ + *val |= !!v; + if (*val) + break; + } + + return 0; } static int i915_wedged_set(void *data, u64 val) { struct drm_i915_private *i915 = data; - intel_gt_debugfs_reset_store(to_gt(i915), val); + struct intel_gt *gt; + unsigned int i; + + for_each_gt(gt, i915, i) + intel_gt_debugfs_reset_store(gt, val); return 0; } @@ -732,7 +754,11 @@ static int i915_sseu_status(struct seq_file *m, void *unused) static int i915_forcewake_open(struct inode *inode, struct file *file) { struct drm_i915_private *i915 = inode->i_private; - intel_gt_pm_debugfs_forcewake_user_open(to_gt(i915)); + struct intel_gt *gt; + unsigned int i; + + for_each_gt(gt, i915, i) + intel_gt_pm_debugfs_forcewake_user_open(gt); return 0; } @@ -740,7 +766,11 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) static int i915_forcewake_release(struct inode *inode, struct file *file) { struct drm_i915_private *i915 = inode->i_private; - intel_gt_pm_debugfs_forcewake_user_release(to_gt(i915)); + struct intel_gt *gt; + unsigned int i; + + for_each_gt(gt, i915, i) + intel_gt_pm_debugfs_forcewake_user_release(gt); return 0; } From patchwork Wed Jan 11 23:55:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13097305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9599C46467 for ; Wed, 11 Jan 2023 23:56:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7D18E10E838; Wed, 11 Jan 2023 23:56:19 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1AB5310E2C5 for ; Wed, 11 Jan 2023 23:56:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673481376; x=1705017376; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w4V4wt3JHqbj3QI6M+dSkYv5uC+o73NfOa2u5/uhXBA=; b=DJLF5p9bgCOXwB6Vh2DN2ZuQFmQbAMwQ1CDCXSscmm5bUc2ho8Imn8Ix SoLKiIoDX1u649+2mKC4Wb3EuRy8okfTi8VvaW2cv02Qfs6wZJqMeuvHg 148y+6tHeBmcK6J0wmdmby7wldQIZFpyPA4ehSVXplD6fr04jo+E4r4vS EXqx/LfD76OhkLcuFr/CRG/2ADsaw6EjKdjamMvj1p/MhCmXR04Q4TqBP 8osFx80KzAXjueEbYpyuyBU/Azb3cOOtcBrTTP0eKzp6nVeZ37eTdhgVz 1yIJUTFeo83P/ASJy9Iz0zeqQblGG8tYZf1bURCKvIliwHG62OqLLfPsk Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="307090902" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="307090902" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831486387" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="831486387" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Jan 2023 15:55:29 -0800 Message-Id: <20230111235531.3353815-8-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> References: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH dii-client 7/9] drm/i915/fbdev: lock the fbdev obj before vma pin X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tejas Upadhyay lock the fbdev obj before calling into i915_vma_pin_iomap(). This helps to solve below : <7>[ 93.563308] i915 0000:00:02.0: [drm:intelfb_create [i915]] no BIOS fb, allocating a new one <4>[ 93.581844] ------------[ cut here ]------------ <4>[ 93.581855] WARNING: CPU: 12 PID: 625 at drivers/gpu/drm/i915/gem/i915_gem_pages.c:424 i915_gem_object_pin_map+0x152/0x1c0 [i915] v2 : - Remove err variable - Chris - Pass false as its not interruptible - Chris Bug-id: VLK-38439 Fixes: b473df22760f9 ("backport "drm/i915: Add ww context to intel_dpt_pin, v2.") Cc: Chris Wilson Cc: Matthew Auld Signed-off-by: Tejas Upadhyay Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_fbdev.c | 24 ++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 03ed4607a46d..40808d57f0d0 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -210,6 +210,7 @@ static int intelfb_create(struct drm_fb_helper *helper, bool prealloc = false; void __iomem *vaddr; struct drm_i915_gem_object *obj; + struct i915_gem_ww_ctx ww; int ret; mutex_lock(&ifbdev->hpd_lock); @@ -290,13 +291,24 @@ static int intelfb_create(struct drm_fb_helper *helper, info->fix.smem_len = vma->size; } - vaddr = i915_vma_pin_iomap(vma); - if (IS_ERR(vaddr)) { - drm_err(&dev_priv->drm, - "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr); - ret = PTR_ERR(vaddr); - goto out_unpin; + for_i915_gem_ww(&ww, ret, false) { + ret = i915_gem_object_lock(vma->obj, &ww); + + if (ret) + continue; + + vaddr = i915_vma_pin_iomap(vma); + if (IS_ERR(vaddr)) { + drm_err(&dev_priv->drm, + "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr); + ret = PTR_ERR(vaddr); + continue; + } } + + if (ret) + goto out_unpin; + info->screen_base = vaddr; info->screen_size = vma->size; From patchwork Wed Jan 11 23:55:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13097311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 072FFC54EBC for ; Wed, 11 Jan 2023 23:56:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 279F210E843; Wed, 11 Jan 2023 23:56:28 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id DD45010E170 for ; Wed, 11 Jan 2023 23:56:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673481375; x=1705017375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IKlAlzd9mJ7LxpNfVic4ExHFHNgKreQe+KrAwzZJ0Xg=; b=kkWsr0pT8mGfq5hKAa6F3OC7lMQlBEqTzemxMb6cmNK4v2anxLMn3g4T GsrHD920eDlhBSUUg2tQZZ2fkf00r9e32qA7R4f0E/+eKm+o7TCyB4v9h jl/8xof4nDpp3Wewzoggja+bVug+L5LCx5KMYmHTkGd+cMIli4P9MpM1V phy62RCZcCEGSy/DtgCuK5WmIO4qi5H0P6nL9CABB5YWNQQaqJ1JSIU2b vDgRemxRMGbweClvUinnrdbTafKFnH6DEMMiGa9TcnCqVCrV6iL0kUq4k lNsZAHcFK7JbWAepUet3/WfVd7+JB6fKUQUrapD/NpjTK1XtwB02sf4lL g==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="307090899" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="307090899" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831486389" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="831486389" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Jan 2023 15:55:30 -0800 Message-Id: <20230111235531.3353815-9-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> References: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH dii-client 8/9] drm/i915/mtl: Skip pcode qgv restrictions for MTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Communicating QGV points restriction to PUnit happens via PM Demand instead of the Pcode mailbox in the previous platforms. GV point restriction is handled by the PM demand code. Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_bw.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 1c236f02b380..6791b25eb72d 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -124,6 +124,9 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, { int ret; + if (DISPLAY_VER(dev_priv) >= 14) + return 0; + /* bspec says to keep retrying for at least 1 ms */ ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG, points_mask, From patchwork Wed Jan 11 23:55:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13097307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8116DC5479D for ; Wed, 11 Jan 2023 23:56:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F13010E83F; Wed, 11 Jan 2023 23:56:20 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6CE4310E176 for ; Wed, 11 Jan 2023 23:56:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673481376; x=1705017376; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SQ22vN3h73dKPedccgjBF0XVtKc1E52/qDLJFl4E+/Y=; b=UXp9YwJwMgsf+QWehUYsQ0mViUIntDepuUHV7qXVqmhI+/y2TkwO/+o3 DVT2sLbBYJnZN4eP89Qt4T0eFsKDapvxKevqVfghhcOtltipmSHmNc5Zo 1ig0UO85FWl31VlkvqJFwV+/JYO72qpJTymyBGlCZSizKG86hLmK4ox8I XJZDawUXUfecrnjoQkMH5Qq4Cl6ti50nnm7UAFbBS/NdY11ZacCXhM/su zqNTFlzK1vhEahzMhR9r1iffu9sYDaBh4Nn0sZK0DGgxGStPSjTrDrdfD hMHZwXxc28iEHW2fCMFXsF2M3RkL1bNrhlqGKxGI3WRbJzAOoUg9kfQ5L A==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="307090903" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="307090903" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831486392" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="831486392" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Jan 2023 15:55:31 -0800 Message-Id: <20230111235531.3353815-10-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> References: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH dii-client 9/9] drm/i915/display/mtl: Program latch to phy reset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: José Roberto de Souza Latch reset of phys during DC9 and when driver is unloaded to avoid phy reset. Specification ask us to program it closer to the step that enables DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy latch during driver load. BSpec: 49197 Cc: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 1a23ecd4623a..9b6dfd5f1259 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1646,6 +1646,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, intel_power_well_enable(dev_priv, well); mutex_unlock(&power_domains->lock); + if (DISPLAY_VER(dev_priv) == 14) + intel_de_rmw(dev_priv, DC_STATE_EN, + HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); + /* 4. Enable CDCLK. */ intel_cdclk_init_hw(dev_priv); @@ -1700,6 +1704,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) /* 3. Disable CD clock */ intel_cdclk_uninit_hw(dev_priv); + if (DISPLAY_VER(dev_priv) == 14) + intel_de_rmw(dev_priv, DC_STATE_EN, 0, + HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH); + /* * 4. Disable Power Well 1 (PG1). * The AUX IO power wells are toggled on demand, so they are already diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d43f0f8e061c..d84d05cc49de 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7383,6 +7383,8 @@ enum skl_power_gate { #define DC_STATE_DISABLE 0 #define DC_STATE_EN_DC3CO REG_BIT(30) #define DC_STATE_DC3CO_STATUS REG_BIT(29) +#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21) +#define HOLD_PHY_PG1_LATCH REG_BIT(20) #define DC_STATE_EN_UPTO_DC5 (1 << 0) #define DC_STATE_EN_DC9 (1 << 3) #define DC_STATE_EN_UPTO_DC6 (2 << 0)