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Thu, 12 Jan 2023 09:18:39 +0000 From: Ming Qian To: mchehab@kernel.org, hverkuil-cisco@xs4all.nl Cc: shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, xiahong.bao@nxp.com, eagle.zhou@nxp.com, tao.jiang_2@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/2] media: add RealVideo format Date: Thu, 12 Jan 2023 17:18:17 +0800 Message-Id: X-Mailer: git-send-email 2.38.1 In-Reply-To: References: X-ClientProxiedBy: SG2PR04CA0152.apcprd04.prod.outlook.com (2603:1096:4::14) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB6341:EE_|AM9PR04MB8923:EE_ X-MS-Office365-Filtering-Correlation-Id: 97875b8a-4c09-4e93-c51a-08daf47dfdd6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: b3G4awc3QU8Nr02rpfGrbOchXgvkfOjfR5G1A7i6QLuRwX6xzsWlPBXZynBeVW8B6KKnsbRXBENakt+99yjfQJABt9ABiUZ8rVL5HoXLbfUHHCpgQR4px2tXb3pIQ6ZNpqGmbZmr46DkdDMEVhsg9S8UsvR6s3VpZjwPe66s1a7Z0s0bAy5bQLFsxFPs2EOPX5SRenAFnszS773U3QFYR8CYu4uUpUmGLgU8UVPLENm4ylV2v6FN8cCsnZ7e0VeNAlkG84Qqnq4KDV/NO3zeNAL5f7LcBiUIEODLB/JYEKz2xp7c3YHeU4JG1Xj+bpoxi8UpbpsoVAoa7RtRStTUjxQ0JRiuvIEODiEMUFQG9Iamyc1cND83oNsX9BgysKgBQa9loepYJyoZ9xUk6KeyOP5eHqokvFLzC9yAfF/1rus+mWX7+Gg6UNldELViZxi6N3/5eodrUWn3l33WwbpYao+qrb9/gfgEy9KHjdmELyrfPWrThP6Fh4kVdunU2ZUI10YVRybr/5m1xUOee/OS0GsaLrzsRkILqpbfCffWj2ffGKofycR1UUlOPiUGDFStfRXvK8A2mKH/4mu491qZxaFTkV8TeqRI9ecs7TwQdhbM3XmCigXv6G+HP1SyKFi7JkCkFd8rI2MGjnKpgWi5V/c2aSIwCKgvcXnHmoWrtTBrV41vFhcQMUXm7PANbRvfijStOtg1FtCEDnRTqkKxrw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AM6PR04MB6341.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(376002)(136003)(346002)(396003)(366004)(451199015)(316002)(2616005)(26005)(41300700001)(5660300002)(8936002)(7416002)(66476007)(66946007)(8676002)(66556008)(4326008)(44832011)(2906002)(52116002)(6512007)(6506007)(86362001)(6666004)(186003)(36756003)(38100700002)(478600001)(38350700002)(6486002);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: q3iETQ+JgwGAxKSom8sU1umbb2zKzelGrHtaOgsKcJCUKZhnrXjB//Sq1MtoVrQqQmhFPYWHioh+gsKZgxf7z5urTWPgXQfbrGrQa+DEaXB02nXe8rCUk/Mr82s0Iw7ONOxKTqhSj9rjLh5GLJ37gy8lNKMJu5tJJAbyB+XF69+WAo7sHzB2Z+lp8ZbW3ELvvfvzgEEptboVX52CKGkARJVhbpRKTon7XQBaKEDsjGPd6MIe9/zDwSheeiVkp6qe+H78M7/MsQ5F1HPU6gWWwlqaKoFaIZQY+fI4qVS8I3960vRWmd/a3UFm0Tn6yiGoLwUMzSj4D2AmLM4dZiQJzY8BD/oJhxwJKVsu4puJvhNF7n7aN+tNxNk8TeZszTz2byjGB1NagKYI5MoxyPQ3bSBtDyJUx49X+umDDMfRiRCBswe0v7KIoudmWswdmUC7p2fRWOB4lRJlL8I4OLUsBJReMMAQSdKTUqTNsAL2sESHe2rgDeIcHyUfeAjvadm1UoNzWLJbUakO7VC8p5qpN1mkKbd9qEiINF7KDl9jZL6O+MHMPkcJwyNXWv7/M6cLviocjeqwZ1tjX/pFMi3g1mp8+wf2W+zYckyvrAYVrVhNK28NGN+hNGv04f1/v6AwYi23GYvdoZBAbHDXvBE06fX3uS9pjLAJ3cm0MrsDH29ct2k1Dd/2AdvWxEmG4GvQYFVaBKUtfwSD6fYEomJVidvtZXnhLpRYUiGqbdixU3q+CVtDA5Kt58kISmemJlqK64/kP/KvuX3AqyMJmt/iD43NaeyQZEJTVwm5w2eC15yaV5X+KMA4Sct1YbNdhf+zS8rhCMHsAqLS/LJgdN79ozprQJKzY7zlCGUd9mufmBrmup40F4YSdm8CpHbT4ZWdIMPBSef+hy1BrdgPjxkwolT+y7hdTobWYkkMUuhLw0Fg4tFFwlrE67yc4MiJUgzRR5pvdhhf7daOFsr9jglllXXDE8ERfyV+W+OGSjqyEF688y6gP8Et8bpkdkL7CIbY/0lDqpdVcomOTpq/hwFgcgqBkFb0pHP6gkdbTElzslqUDEkJdxEpXtxRWOE8w0VVMDhIzm2iXcR0cYgsSTGsbZ3POpH23J7l9rAdnMix2KDI8jERiCeoSaC3nLjcAUgLrYui28r0CXxd8x8ACb1iW0lwWTOouuubOBUZ5/TuffmeRhPtbHhwkVZiSNQeuIO2GRMHa3tDk2wcxbp0hbLWlpR4Ne/fS011pR5TUPChBlAgG5r83sTbDjdz6dURaltz4iWmpCOUtB94/KY0pOhjFRg0e5smZKyaut2FzpRX4xKZKEA5yE1p7aOPzaH+qG/OXnI0QiReUiDQEzy2m8a2xgfbCoh/Ildwi+LAW5wTAX3Zl+3FsElAXb2qnJy6lYTOWaXEdCs0vtm6uDhU86XFoFMM2aZ+HGGjv0nxVXNlXG5Sb65LlhL0jZbvWGArgHMuw6Dv1s8bdu6X2H7B5FFxt2f978psZ6F7VOm91lAqWkg+IHMJPdkxxyKzIuwVAXdl2V6GDnsMA9HDxSfu4HjVZAIanj6Q7nxVEv5+h38F4kZtj5cNk1cXW6UOuKT3slVZ X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 97875b8a-4c09-4e93-c51a-08daf47dfdd6 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2023 09:18:39.5802 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lTGtIfxgET2TU94+gbEQW6qLKI7s7wBE7cKao6Y7hBGsunh5HE4qMcVHaNhbVDfbvTXEpHqPSN9YHnrTRY0Nzg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB8923 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org RealVideo, or also spelled as Real Video, is a suite of proprietary video compression formats developed by RealNetworks - the specific format changes with the version. RealVideo codecs are identified by four-character codes. RV10 and RV20 are the H.263-based codecs. RV30 and RV40 are RealNetworks' proprietary H.264-based codecs. RV60 is RealNetworks' proprietary HEVC-based codecs. Signed-off-by: Ming Qian --- .../userspace-api/media/v4l/pixfmt-compressed.rst | 11 +++++++++++ drivers/media/v4l2-core/v4l2-ioctl.c | 1 + include/uapi/linux/videodev2.h | 1 + 3 files changed, 13 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst index a0230f357680..22035d92c788 100644 --- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst +++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst @@ -237,6 +237,17 @@ Compressed Formats Metadata associated with the frame to decode is required to be passed through the ``V4L2_CID_STATELESS_FWHT_PARAMS`` control. See the :ref:`associated Codec Control ID `. + * .. _V4L2-PIX-FMT-RV: + + - ``V4L2_PIX_FMT_RV`` + - 'RV00' + - RealVideo, or also spelled as Real Video, is a suite of proprietary + video compression formats developed by RealNetworks - + the specific format changes with the version. + RealVideo codecs are identified by four-character codes. + RV10 and RV20 are the H.263-based codecs. + RV30 and RV40 are RealNetworks' proprietary H.264-based codecs. + RV60 is RealNetworks' proprietary HEVC-based codecs. .. raw:: latex diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index 9b5b04b8aa69..c375261d169f 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1473,6 +1473,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ case V4L2_PIX_FMT_FWHT_STATELESS: descr = "FWHT Stateless"; break; /* used in vicodec */ case V4L2_PIX_FMT_SPK: descr = "Sorenson Spark"; break; + case V4L2_PIX_FMT_RV: descr = "RealVideo"; break; case V4L2_PIX_FMT_CPIA1: descr = "GSPCA CPiA YUV"; break; case V4L2_PIX_FMT_WNVA: descr = "WNVA"; break; case V4L2_PIX_FMT_SN9C10X: descr = "GSPCA SN9C10X"; break; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 262ef10cfa02..0a7ddb023d7c 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -740,6 +740,7 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ #define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */ #define V4L2_PIX_FMT_SPK v4l2_fourcc('S', 'P', 'K', '0') /* Sorenson Spark */ +#define V4L2_PIX_FMT_RV v4l2_fourcc('R', 'V', '0', '0') /* RealVideo */ /* Vendor-specific formats */ #define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */ From patchwork Thu Jan 12 09:18:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ming Qian X-Patchwork-Id: 13097713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D199C54EBD for ; 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RV30 and RV40 are support by amphion decoder. Signed-off-by: Ming Qian --- drivers/media/platform/amphion/vdec.c | 7 +++++++ drivers/media/platform/amphion/vpu_malone.c | 19 +++++++++++++++++++ drivers/media/platform/amphion/vpu_malone.h | 1 + 3 files changed, 27 insertions(+) diff --git a/drivers/media/platform/amphion/vdec.c b/drivers/media/platform/amphion/vdec.c index 09304b96f40d..7e47465ee749 100644 --- a/drivers/media/platform/amphion/vdec.c +++ b/drivers/media/platform/amphion/vdec.c @@ -172,6 +172,13 @@ static const struct vpu_format vdec_formats[] = { .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED }, + { + .pixfmt = V4L2_PIX_FMT_RV, + .mem_planes = 1, + .comp_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED + }, {0, 0, 0, 0}, }; diff --git a/drivers/media/platform/amphion/vpu_malone.c b/drivers/media/platform/amphion/vpu_malone.c index 67ba637c4c7f..6e3626b74c7a 100644 --- a/drivers/media/platform/amphion/vpu_malone.c +++ b/drivers/media/platform/amphion/vpu_malone.c @@ -68,6 +68,8 @@ #define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000) #define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000) +#define MALONE_DEC_FMT_RV_MASK BIT(21) + enum vpu_malone_stream_input_mode { INVALID_MODE = 0, FRAME_LVL, @@ -478,6 +480,8 @@ u32 vpu_malone_get_version(struct vpu_shared_addr *shared) { struct malone_iface *iface = shared->iface; + vpu_malone_enable_format(V4L2_PIX_FMT_RV, iface->fw_version & MALONE_DEC_FMT_RV_MASK); + return iface->fw_version; } @@ -563,8 +567,21 @@ static struct malone_fmt_mapping fmt_mappings[] = { {V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG}, {V4L2_PIX_FMT_VP8, MALONE_FMT_VP8}, {V4L2_PIX_FMT_SPK, MALONE_FMT_SPK}, + {V4L2_PIX_FMT_RV, MALONE_FMT_RV}, }; +void vpu_malone_enable_format(u32 pixelformat, int enable) +{ + u32 i; + + for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) { + if (pixelformat == fmt_mappings[i].pixelformat) { + fmt_mappings[i].is_disabled = enable ? 0 : 1; + return; + } + } +} + static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat) { u32 i; @@ -989,6 +1006,7 @@ static const struct malone_padding_scode padding_scodes[] = { {SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, {SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, {SCODE_PADDING_EOS, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_RV, {0x34010000, 0x0}}, {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}}, {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, @@ -1001,6 +1019,7 @@ static const struct malone_padding_scode padding_scodes[] = { {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, {SCODE_PADDING_ABORT, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_RV, {0x34010000, 0x0}}, {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}}, {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}}, {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}}, diff --git a/drivers/media/platform/amphion/vpu_malone.h b/drivers/media/platform/amphion/vpu_malone.h index 02a9d9530970..c95b53629199 100644 --- a/drivers/media/platform/amphion/vpu_malone.h +++ b/drivers/media/platform/amphion/vpu_malone.h @@ -41,5 +41,6 @@ int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance); int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance); u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared); bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt); +void vpu_malone_enable_format(u32 pixelformat, int enable); #endif