From patchwork Fri Jan 13 12:37:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 13100712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DCB2C54EBD for ; Fri, 13 Jan 2023 12:38:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pGJK4-0000VU-Ic; Fri, 13 Jan 2023 07:38:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGJK2-0000VL-U3 for qemu-devel@nongnu.org; Fri, 13 Jan 2023 07:38:14 -0500 Received: from collins.uni-paderborn.de ([2001:638:502:c003::14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGJK0-00063s-I3 for qemu-devel@nongnu.org; Fri, 13 Jan 2023 07:38:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.uni-paderborn.de; s=20170601; h=Content-Transfer-Encoding:MIME-Version :Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=yi4ZeNALlvAg+NVpSBuZH/Ot2FdIcujd5SQASNUGg6E=; b=AxDtbwWEvmr2YyQNyo/u7F+43C oo+YpSQ6yKTOMxFsTviCuqwbwIS7MaF1Stv/j9hcAmM5sZWpTZNt9OD6h1U3typ0tuO5BQaC5EgG6 M+LHAIDXctknM6NU/V+bXZfa8Njdpirqp/dLKNpKwnbtziIWwpOm90L7mQ8F7oP8YqL4=; X-Envelope-From: From: Bastian Koppelmann To: qemu-devel@nongnu.org Cc: kbastian@mail.uni-paderborn.de, philmd@linaro.org Subject: [PATCH] target/tricore: Fix OPC2_32_RCRW_IMASK translation Date: Fri, 13 Jan 2023 13:37:59 +0100 Message-Id: <20230113123759.677960-1-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 X-IMT-Source: Intern X-PMX-Version: 6.4.9.2830568, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2023.1.13.122717, AntiVirus-Engine: 5.96.0, AntiVirus-Data: 2022.12.20.5960002 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de Received-SPF: pass client-ip=2001:638:502:c003::14; envelope-from=kbastian@mail.uni-paderborn.de; helo=collins.uni-paderborn.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org we were mixing up the "c" and "d" registers. We used "d" as a destination register und "c" as the source. According to the TriCore ISA manual 1.6 vol 2 it is the other way round. Signed-off-by: Bastian Koppelmann Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653 --- target/tricore/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index df9e46c649..8de4e56b1f 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -5794,11 +5794,11 @@ static void decode_rcrw_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RCRW_IMASK: - tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f); + tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); tcg_gen_movi_tl(temp2, (1 << width) - 1); - tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp); + tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); tcg_gen_movi_tl(temp2, const4); - tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp); + tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); break; case OPC2_32_RCRW_INSERT: temp3 = tcg_temp_new();