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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v7 1/7] x86/cpu, kvm: Add support for cpuid leaf 80000021/EAX (FeatureExt2Eax) Date: Mon, 16 Jan 2023 17:01:53 -0600 Message-ID: <20230116230159.1511393-2-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230116230159.1511393-1-kim.phillips@amd.com> References: <20230116230159.1511393-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B074:EE_|PH0PR12MB5433:EE_ X-MS-Office365-Filtering-Correlation-Id: 37b6511d-9a2c-42b2-576c-08daf815b8b0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AUpvgUHrU/2X2k4HKWHW3baiNlnOMuDp0tD85HxeHvO1eEiK7qRdlx+dTUZH39bPWLVoEdchO8Oh6IJna5XWkNrdqCHwgkR8Nx9nVnM+4Ku1rV464DZG9Au37hybyc4GcqRHCv1Nxqgu+21gPP0PrwnqLONbz/GDCYWSUvL99YIOsqM7ARYbahdBqHQaqNqK1apOqaO2BP5EUwjglnhY+Xr4NGXYS6wRIWcxXbMAAeB8mM7bYj8eL6eaXbMzOaQk2ETNh7FxpuhmgBh75YWoCsCYdE5tD3Vxy2SPfNYtaiv1W5M6UwagiKxN6wObbKMQj9XKwg7Nvx0D+NALsw5VfkodKfRrIH9DJWcZiWTKcf8ks60BCSTezT8e7aY5tJltykon0IdUIlGh5u6IbB66l4KsGnp13JLlPwWtrsvzOrj/S7k2+k+HyssJhN0bElEP/sGfEISJEopCKVpoxj+uAFjXoBsqoBVzfiqMq/Q8IghuoS7FBusPb08HYQGNeE59dtkTK3xAFPNhM5WwZXvO65be0meYBvF4Ybt1/ss7zQ7/Oienl/YwaHMpqye28SdFw0x5tsEGF/KU00jeX8FpIv2azFL7NX1hi4BTugQXTt3X6OF2BUlFLw1YMXD6RKJdvK+61jTyJNdPUtTuo2lZichfRudo9U8Q33+882fxdtXZGi15YzraGQy2BWnIdlt5bPIXreqyZ+mzyB2i62Q/JB8mFa8k/We2ihB/1peFSCE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199015)(46966006)(36840700001)(40470700004)(81166007)(83380400001)(36860700001)(82740400003)(86362001)(356005)(5660300002)(70586007)(4326008)(2906002)(7416002)(44832011)(6916009)(8936002)(8676002)(70206006)(41300700001)(82310400005)(40480700001)(2616005)(186003)(26005)(16526019)(336012)(1076003)(426003)(47076005)(6666004)(316002)(54906003)(7696005)(40460700003)(478600001)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 23:02:20.2131 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37b6511d-9a2c-42b2-576c-08daf815b8b0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B074.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5433 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add the 80000021/EAX leaf that advertises features in later Zen processors. The majority of the features will be used in the kernel and thus a separate leaf is appropriate. Include KVM's reverse_cpuid entry because features are used by VM guests, too. Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeature.h | 7 +++++-- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/include/asm/disabled-features.h | 3 ++- arch/x86/include/asm/required-features.h | 3 ++- arch/x86/kernel/cpu/common.c | 3 +++ arch/x86/kvm/reverse_cpuid.h | 1 + 6 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 1a85e1fb0922..ce0c8f7d3218 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -32,6 +32,7 @@ enum cpuid_leafs CPUID_8000_0007_EBX, CPUID_7_EDX, CPUID_8000_001F_EAX, + CPUID_8000_0021_EAX, }; #define X86_CAP_FMT_NUM "%d:%d" @@ -94,8 +95,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) || \ + CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 20, feature_bit) || \ REQUIRED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS != 20)) + BUILD_BUG_ON_ZERO(NCAPINTS != 21)) #define DISABLED_MASK_BIT_SET(feature_bit) \ ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \ @@ -118,8 +120,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) || \ + CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 20, feature_bit) || \ DISABLED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS != 20)) + BUILD_BUG_ON_ZERO(NCAPINTS != 21)) #define cpu_has(c, bit) \ (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 6cfa7143c316..a84536876794 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -13,7 +13,7 @@ /* * Defines x86 CPU feature bits */ -#define NCAPINTS 20 /* N 32-bit words worth of info */ +#define NCAPINTS 21 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ /* diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index c44b56f7ffba..5dfa4fb76f4b 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -124,6 +124,7 @@ #define DISABLED_MASK17 0 #define DISABLED_MASK18 0 #define DISABLED_MASK19 0 -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20) +#define DISABLED_MASK20 0 +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21) #endif /* _ASM_X86_DISABLED_FEATURES_H */ diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h index aff774775c67..7ba1726b71c7 100644 --- a/arch/x86/include/asm/required-features.h +++ b/arch/x86/include/asm/required-features.h @@ -98,6 +98,7 @@ #define REQUIRED_MASK17 0 #define REQUIRED_MASK18 0 #define REQUIRED_MASK19 0 -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20) +#define REQUIRED_MASK20 0 +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21) #endif /* _ASM_X86_REQUIRED_FEATURES_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index ce40e7caa555..d762654d16a0 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1093,6 +1093,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c) if (c->extended_cpuid_level >= 0x8000001f) c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); + if (c->extended_cpuid_level >= 0x80000021) + c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); + init_scattered_cpuid_features(c); init_speculation_control(c); diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index 042d0aca3c92..81f4e9ce0c77 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -68,6 +68,7 @@ static const struct cpuid_reg reverse_cpuid[] = { [CPUID_12_EAX] = {0x00000012, 0, CPUID_EAX}, [CPUID_8000_001F_EAX] = {0x8000001f, 0, CPUID_EAX}, [CPUID_7_1_EDX] = { 7, 1, CPUID_EDX}, + [CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX}, }; /* From patchwork Mon Jan 16 23:01:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 13103822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60C12C67871 for ; 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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v7 2/7] x86/cpu, kvm: Add the NO_NESTED_DATA_BP feature Date: Mon, 16 Jan 2023 17:01:54 -0600 Message-ID: <20230116230159.1511393-3-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230116230159.1511393-1-kim.phillips@amd.com> References: <20230116230159.1511393-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B074:EE_|PH8PR12MB7025:EE_ X-MS-Office365-Filtering-Correlation-Id: 620d73ac-ca5e-47f4-7065-08daf815c0a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sIsnQkEVSW1easYSeJAzyYnFvib8bOT2SFHInmWjLdzHfE72KnD3XC3vgaZw3TQ43Zy8Id8BzVG7o6H4bLw0CqAvk+nkVZ/ahlnvjyZWcaew+pKB05bh76jzP1DmZ6tNIcbqeO+UeVJMALrY2TDS08R4u804A8Gxt9XlqehdHcFZhqV8O0NqO16zqXNkJcQbOKMiLfyVj/n+iFx1oyPceGrjvYus5GcI5a+dCgrJmvV38j7FuDuRIx12dB6k8Y/HOTQm9h51d4Vm4xbMBNHfVNwJLf4mWyUXtOwaM91qNFCHfXVwjQp9JH1EMHYlWsog9ftt08J1/5x315mnr7+qDmIFNZa62yTS8uo6srtuLRzKQms4/kQBTTL2LqoQgkAzZfwQSq8eLtF2K81wYowD5/rdmTBd0TgF8IZAgtNhMCcqqNTqwDFnuqhWNjE0lXVoDHhDF0iDzKHSKFsL6If/lVLdjySpLzL9+5jt9pjdKtwqVcHdQtiHME2bPpvl4TjM9qaZKcsaBXHJJSD+hpTNHhOTeug8LaT9XosaHg8M1DEgvwPhfTmIk5lljbVITn/a4J/EIudn5KlhVADUfYDvKM1g4uW+7eM+eQwQLeFwej3Zy7zUZEMceS5nCSWfuWlS4uWKgbGoDvZ2aY5syZrPx4lgtRfZbUvXcuKPBv4/clKc01qoV2VmLlla8xcjOseeEx5kcPuEwsvGBWSgJhkH/GF5k8I/43vIPXAAXAFssgI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(136003)(376002)(346002)(451199015)(46966006)(36840700001)(40470700004)(36756003)(6666004)(26005)(82310400005)(16526019)(186003)(4326008)(478600001)(82740400003)(81166007)(356005)(7696005)(40460700003)(40480700001)(83380400001)(2616005)(86362001)(336012)(1076003)(36860700001)(47076005)(426003)(44832011)(8936002)(7416002)(5660300002)(2906002)(8676002)(70586007)(70206006)(6916009)(54906003)(41300700001)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 23:02:33.5567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 620d73ac-ca5e-47f4-7065-08daf815c0a4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B074.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7025 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The "Processor ignores nested data breakpoints" feature was being open-coded for KVM in __do_cpuid_func(). Add it to its newly added CPUID leaf 0x80000021 EAX proper, and propagate it in kvm_set_cpu_caps() instead. Also drop the bit description comments now it's more self-describing. Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 3 +++ arch/x86/kvm/cpuid.c | 8 ++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index a84536876794..8255b95a7987 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -428,6 +428,9 @@ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ +/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ +#define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" AMD No Nested Data Breakpoints */ + /* * BUG word(s) */ diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 596061c1610e..c9081e3a1b66 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -741,6 +741,10 @@ void kvm_set_cpu_caps(void) 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | F(SME_COHERENT)); + kvm_cpu_cap_mask(CPUID_8000_0021_EAX, + F(NO_NESTED_DATA_BP) + ); + kvm_cpu_cap_mask(CPUID_C000_0001_EDX, F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | @@ -1222,9 +1226,9 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) break; case 0x80000021: entry->ebx = entry->ecx = entry->edx = 0; + cpuid_entry_override(entry, CPUID_8000_0021_EAX); /* * Pass down these bits: - * EAX 0 NNDBP, Processor ignores nested data breakpoints * EAX 2 LAS, LFENCE always serializing * EAX 6 NSCB, Null selector clear base * @@ -1235,7 +1239,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) * KVM doesn't support SMM_CTL. * EAX 9 SMM_CTL MSR is not supported */ - entry->eax &= BIT(0) | BIT(2) | BIT(6); + entry->eax &= BIT(2) | BIT(6); entry->eax |= BIT(9); if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)) entry->eax |= BIT(2); From patchwork Mon Jan 16 23:01:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 13103823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED279C54EBE for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000B076.mail.protection.outlook.com (10.167.17.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6002.11 via Frontend Transport; Mon, 16 Jan 2023 23:02:44 +0000 Received: from fritz.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 16 Jan 2023 17:02:43 -0600 From: Kim Phillips To: CC: Kim Phillips , Borislav Petkov , "Boris Ostrovsky" , Dave Hansen , "H. Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v7 3/7] x86/cpu, kvm: Move the LFENCE_RDTSC / LFENCE always serializing feature Date: Mon, 16 Jan 2023 17:01:55 -0600 Message-ID: <20230116230159.1511393-4-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230116230159.1511393-1-kim.phillips@amd.com> References: <20230116230159.1511393-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B076:EE_|CH3PR12MB8329:EE_ X-MS-Office365-Filtering-Correlation-Id: 787a174d-c0eb-499c-5681-08daf815c764 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HQKdx3PUtqjXB1rUtEKvICcGc2sp1SJea05LmSxuGbOfFtqEVZGrimXXiB+oSDdsYN2c+n+XxTLVN0FjPk2lyNkxvuZqKNLtYDUPGiqD7zB7zjO6JXoCHuJycPtF9GddiB8hOP7K78/746bYn0xudiesWathSBFRpRxhgw48Yb04OUlrnwpEweeFXDbFhTGFkwrf8O0S+0HSOKNj1GtZCBbmqxL0bjSq9lYwupC4L1e+qUzPFlygolusDs2xOQMY0d5aTSfoz3fZveeG9nex8B6xvZbztgJaeXH6aW/Tyn98u7/Lp6Ws/WB7f6XrSq4iePGO9DJpP/fqM+7A8HeTRSraLxy28W/mC+LXt9XItQTzgMsTIjT4IkSAEZZ5Qolsl6MJbyku8VdQ3+4LMhUPj+kM4lrvuP1nVuy1llsflgHdCIEPREon3yfWxEL2+yvUSsX+bumT/I8R0r9NKNfsF/JP1lkGg0HBhTBrXK6nphCEEEbVw9QM0Xhuo1ssOb91JCzEO8WKnjHL4pe5jcfCD3F74Ez2yPFvmd0J0PWxdy8oAD5c5PwgEqSRXkNulsKigCyk1PNtU3EEbzuaim14JQCdz9NiklPcuXZ4p629YUNmH/khMdDil6Dv/SaXe1Ednzapw+rzijEbetLd/7EmAmDHqDKc/NWrI1PgFP3rnnxwmWgjIYMlKKpnsmCRWcmlYN2275JowN+hPUobEDHoXnxXEnzK57S/1JRIbr4edkA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(39860400002)(376002)(346002)(451199015)(36840700001)(40470700004)(46966006)(6666004)(26005)(8936002)(6916009)(36756003)(7696005)(2616005)(1076003)(316002)(478600001)(16526019)(5660300002)(40480700001)(186003)(7416002)(4326008)(40460700003)(356005)(82740400003)(41300700001)(70586007)(81166007)(86362001)(8676002)(54906003)(70206006)(83380400001)(82310400005)(47076005)(44832011)(2906002)(426003)(336012)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 23:02:44.8809 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 787a174d-c0eb-499c-5681-08daf815c764 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B076.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8329 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The LFENCE_RDTSC / LFENCE always serializing feature was a scattered bit and open-coded for KVM in __do_cpuid_func(). Add it to its newly added CPUID leaf 0x80000021 EAX proper, and propagate it in kvm_set_cpu_caps() instead. Drop the bit description comments now it's more self-describing. Also, in amd_init(), don't bother setting DE_CFG[1] any more if we already have the X86_FEATURE_LFENCE_RDTSC feature (set by hardware). Whilst there, switch to using the more efficient cpu_feature_enabled() instead of static_cpu_has(). Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 3 ++- arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kvm/cpuid.c | 9 ++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 8255b95a7987..b22b2e8fef00 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -97,7 +97,7 @@ #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */ -#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ +/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */ #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ #define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */ @@ -430,6 +430,7 @@ /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" AMD No Nested Data Breakpoints */ +#define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index f769d6d08b43..208c2ce8598a 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -956,7 +956,7 @@ static void init_amd(struct cpuinfo_x86 *c) init_amd_cacheinfo(c); - if (cpu_has(c, X86_FEATURE_XMM2)) { + if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { /* * Use LFENCE for execution serialization. On families which * don't have that MSR, LFENCE is already serializing. diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index c9081e3a1b66..d7a13716b7c8 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -742,8 +742,10 @@ void kvm_set_cpu_caps(void) F(SME_COHERENT)); kvm_cpu_cap_mask(CPUID_8000_0021_EAX, - F(NO_NESTED_DATA_BP) + F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) ); + if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) + kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); kvm_cpu_cap_mask(CPUID_C000_0001_EDX, F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | @@ -1229,7 +1231,6 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) cpuid_entry_override(entry, CPUID_8000_0021_EAX); /* * Pass down these bits: - * EAX 2 LAS, LFENCE always serializing * EAX 6 NSCB, Null selector clear base * * Other defined bits are for MSRs that KVM does not expose: @@ -1239,10 +1240,8 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) * KVM doesn't support SMM_CTL. * EAX 9 SMM_CTL MSR is not supported */ - entry->eax &= BIT(2) | BIT(6); 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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v7 4/7] x86/cpu, kvm: Add the Null Selector Clears Base feature Date: Mon, 16 Jan 2023 17:01:56 -0600 Message-ID: <20230116230159.1511393-5-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230116230159.1511393-1-kim.phillips@amd.com> References: <20230116230159.1511393-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B07A:EE_|MN0PR12MB6150:EE_ X-MS-Office365-Filtering-Correlation-Id: 4c167d6d-804d-476b-17c4-08daf815d15b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: x6tfkbFo9j1M1kTkgM9OJFThoid7IwTJLyfsuZ5mKzTB4dOphDxXVPZTxCNggYQLZr6ptxrDVn4mN90Iq9qnVoeIzSfMYZavk2IvkzH7PiLdRx1Y89zi8DD6ushIMGEYd/HIKMCJllK6avWFx86t1iDqna46LlfyQAadbbXbFM8QTzPH/bx9sYUFdFIo76Gc9QWZqXCiolsnfP5FLWzEwGdgLcH6B08icqNLAFRPpnqzOnozVkMVXmKtAT0NMijQoGcU1anSTa28Ntl8UaSwACvCNQHvKS+rHvYEc8pRG25wbeHjZLvyG+I7lO7Q+9I78cEAD9zAN/cgmB9LXLnE7pa/QHYM34vgEGpoF/gCRF0QIqHMg04QYJhllS2if1K3BGhf8oPBDbAObvQcTKpXdsXIcMlpkZ3z26YraG1OUrpFNiMwcsw+eHJ69H83xNrLf7gft0aeLKoVEFhv5d9RMk+QJ1M3CdvaaiVqylpzxKIYvD6LrM739nohgAiAkqBUh1yBC2x0hlSIdRhydboYcDlQ3zw7Ouu94/5EuS9zncFmTZZdA4OS9bOxTkMOR1wxV5cIyk0nO/vjqsIbGAuR1W2NPCTopfP9iRiml6zimIPKRYLTNPQzFjMZVwgfxyoAxJ7tG1PGisrOU+6uQUPw9ubxPxgY08jz1Dy4jH5Gv5saCTuzb0q48NVzGLBOoDtWkZ8UZZkC7x+jbjUcGi+GuxqKoFisFV30UACp3LM6s3U= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(346002)(396003)(39860400002)(451199015)(36840700001)(46966006)(40470700004)(316002)(54906003)(6916009)(8936002)(5660300002)(7416002)(83380400001)(70206006)(4326008)(70586007)(36756003)(8676002)(41300700001)(356005)(426003)(47076005)(81166007)(336012)(2616005)(1076003)(82740400003)(40460700003)(36860700001)(7696005)(86362001)(40480700001)(26005)(186003)(82310400005)(6666004)(16526019)(478600001)(2906002)(44832011)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 23:03:01.5974 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c167d6d-804d-476b-17c4-08daf815d15b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B07A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6150 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The Null Selector Clears Base feature was being open-coded for KVM in __do_cpuid_func(). Add it to its newly added CPUID leaf 0x80000021 EAX proper, and propagate it in kvm_set_cpu_caps() instead. Also drop the bit description comments now it's more self-describing. Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/cpuid.c | 10 +++------- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b22b2e8fef00..ccef41ff718c 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -431,6 +431,7 @@ /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" AMD No Nested Data Breakpoints */ #define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ +#define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" AMD Null Selector Clears Base */ /* * BUG word(s) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index d7a13716b7c8..afa86241f752 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -742,10 +742,12 @@ void kvm_set_cpu_caps(void) F(SME_COHERENT)); kvm_cpu_cap_mask(CPUID_8000_0021_EAX, - F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) + F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | F(NULL_SEL_CLR_BASE) ); if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); + if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) + kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); kvm_cpu_cap_mask(CPUID_C000_0001_EDX, F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | @@ -1230,9 +1232,6 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) entry->ebx = entry->ecx = entry->edx = 0; cpuid_entry_override(entry, CPUID_8000_0021_EAX); /* - * Pass down these bits: - * EAX 6 NSCB, Null selector clear base - * * Other defined bits are for MSRs that KVM does not expose: * EAX 3 SPCL, SMM page configuration lock * EAX 13 PCMSR, Prefetch control MSR @@ -1240,10 +1239,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) * KVM doesn't support SMM_CTL. * EAX 9 SMM_CTL MSR is not supported */ - entry->eax &= BIT(6); entry->eax |= BIT(9); - if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) - entry->eax |= BIT(6); break; /*Add support for Centaur's CPUID instruction*/ case 0xC0000000: From patchwork Mon Jan 16 23:01:57 2023 Content-Type: text/plain; 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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v7 5/7] x86/cpu, kvm: Add the SMM_CTL MSR not present feature Date: Mon, 16 Jan 2023 17:01:57 -0600 Message-ID: <20230116230159.1511393-6-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230116230159.1511393-1-kim.phillips@amd.com> References: <20230116230159.1511393-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B074:EE_|PH8PR12MB7279:EE_ X-MS-Office365-Filtering-Correlation-Id: 23e84c55-9cc9-4ca9-5ae2-08daf815d853 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4EQlhAM+JVXNigzOusH78Zyg0+8INA+7CO6e3yGv5hRhncBw9lJYvd1oTWx+XvWiDpyEhBSnje+kP9JPJBrzQuRP/IwShvltF+UMgmfr8pv0qqaAh8G2F30zZsYK3LjLLUtIeHR4aaW1ztvPUvVylAD4X5/Eb1RmtljIEYd3h0NbSFrEbk6QOAIyieSQvd1Yhl6q7DVwiAcWGPYSE+FnnlWUpjGUfVzxB7ot4CyWeI06YRBErsOwZsgknpV3pdlYs/XgQJDoxMVfRAPckrphWREFeBhxfNoT0b5mD4jXfOpGHHQAhiuM0tJZClax7/zs+uVPHpBL8PVGO33jpsSMgO2ksTUgEwB4mQj8BemYKOdV3hsHsuWDqu40P+ssPIzZuf+BEShPiYIOvgcP95wgz8WjHKW+9N+HL0MhlAQCV8Rl+/g1zwAIdj8393s0WoIPM0sbOTw8KRTWpdysOumg3mSpftHSZtPgT+NW4zbXq3b4LE+YYA1WTkN+QC/k6I1QIWGbpoCTYHCwVJAdvZFYmXrz3zqk+9iThV67P4IXWZxeuYPNV0HuyLWHVNRxpgLV4DzAvIjHJDXHnG9n+xaLRZgWDKwjPU9GOUeihhe6Q250AJvuAuj6fWw3QupA/MLoEAhuxFT3UMX2ZrDg5usdN3QoRqnSs3mKI1gGUwrO6ptu0v7Qnji+9K5u/CjRePaGxZrn0eZgnbCSXSDRZIJcPhxAdvnaBH1AvvOzfGeVro4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(39860400002)(346002)(376002)(451199015)(36840700001)(40470700004)(46966006)(36756003)(81166007)(40480700001)(356005)(40460700003)(316002)(8676002)(8936002)(54906003)(4326008)(44832011)(5660300002)(41300700001)(70206006)(6916009)(7416002)(70586007)(26005)(186003)(16526019)(86362001)(426003)(336012)(47076005)(7696005)(2616005)(83380400001)(478600001)(1076003)(6666004)(82310400005)(2906002)(82740400003)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 23:03:13.2908 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23e84c55-9cc9-4ca9-5ae2-08daf815d853 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B074.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7279 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The SMM_CTL MSR not present feature was being open-coded for KVM in __do_cpuid_func(). Add it to its newly added CPUID leaf 0x80000021 EAX proper, and propagate it in kvm_set_cpu_caps() instead. Also drop the bit description comments now the code is more self-describing, and retain the SmmPgCfgLock and PrefetchCtlMsr feature bit comments at the kvm_cpu_cap_mask() callsite. Signed-off-by: Kim Phillips --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/cpuid.c | 13 +++---------- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index ccef41ff718c..861d312c7955 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -432,6 +432,7 @@ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" AMD No Nested Data Breakpoints */ #define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ #define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" AMD Null Selector Clears Base */ +#define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9) /* "" AMD SMM_CTL MSR is not present */ /* * BUG word(s) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index afa86241f752..9ba75ad9d976 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -742,12 +742,14 @@ void kvm_set_cpu_caps(void) F(SME_COHERENT)); kvm_cpu_cap_mask(CPUID_8000_0021_EAX, - F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | F(NULL_SEL_CLR_BASE) + F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | + F(NULL_SEL_CLR_BASE) | 0 /* PrefetchCtlMsr */ ); if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); + kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR); kvm_cpu_cap_mask(CPUID_C000_0001_EDX, F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | @@ -1231,15 +1233,6 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) case 0x80000021: entry->ebx = entry->ecx = entry->edx = 0; cpuid_entry_override(entry, CPUID_8000_0021_EAX); - /* - * Other defined bits are for MSRs that KVM does not expose: - * EAX 3 SPCL, SMM page configuration lock - * EAX 13 PCMSR, Prefetch control MSR - * - * KVM doesn't support SMM_CTL. - * EAX 9 SMM_CTL MSR is not supported - */ - entry->eax |= BIT(9); break; /*Add support for Centaur's CPUID instruction*/ case 0xC0000000: From patchwork Mon Jan 16 23:01:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 13103829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 253AFC67871 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000B07A.mail.protection.outlook.com (10.167.17.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6002.11 via Frontend Transport; Mon, 16 Jan 2023 23:03:25 +0000 Received: from fritz.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 16 Jan 2023 17:03:23 -0600 From: Kim Phillips To: CC: Kim Phillips , Borislav Petkov , "Boris Ostrovsky" , Dave Hansen , "H. Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v7 6/7] x86/cpu: Support AMD Automatic IBRS Date: Mon, 16 Jan 2023 17:01:58 -0600 Message-ID: <20230116230159.1511393-7-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230116230159.1511393-1-kim.phillips@amd.com> References: <20230116230159.1511393-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B07A:EE_|PH7PR12MB5758:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d692f9b-461a-423f-0bf9-08daf815df64 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 57ud84a9GvF1+oQmtu/P14ZvPeFzN6ZY/QXDmbC2oIYIjqYKvjRVSrXhZD54KddvIaqYNidhgfkWJEbJKRHz+42CQ+wY5OPoRv7kQwHnWIp3Uqf1DsOtQY4bpzu180HKU4Gl37lCPfVs1RWD3a+z87Wqvz0DqA15DqIxV3PX8v4516Ay2q9fP8+plyd5WZ+OkYbNUBlBA2zNzIoZdCpgESCbWBaCsisA3Oz/0xlxjmcOmBUdi8GkF5N1kK8Jg6dzerqQYa8nLA/K18ejyUQZTW6DIGaQ/q2X/VNssQe/Et2O9+1OR4yF5CghqQOEQIlaO/Bti1oTHhVpbZTYeSp27ji/U2FUT0r5adzb1pQtloBhz0zwPw5XSnT3qcO5peDrpZQ47Kz9EpeDI/q7LA5UcchHXXR/nyOd/x2C+BR83EeQukG8eGG7k5GyPOt5xbLjAJGuZyfBTTocg8MFIUQC9mNkHu1C1GdxuCMKLiQxv5+WdkqHhOnGr9qoU52JPE1/SlXd3X7oZLyARz+o0rNr9P+5UPGEnCkPoK4u9S3bqDskhv/Cjj9XaNst3tfhz0A8kBb6Wuie2zXsapfrUk0epI9UHdUKTktUa/xD246Dh9Ik0tNR4fQGXUq5uL4/13WOPCJQt6gK7KC97e2mAXW+SKpYrUCsNi3I1T4vFLkylJbRNwM7MQt1DOjOkV3otjc5BbkZvTraMYj0CR8gmVsdmBA3b+ISy9lrUhYVdy4ih4Y= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(376002)(39860400002)(136003)(346002)(451199015)(46966006)(40470700004)(36840700001)(47076005)(83380400001)(426003)(40480700001)(40460700003)(82310400005)(36860700001)(44832011)(356005)(81166007)(36756003)(86362001)(82740400003)(316002)(336012)(2906002)(8676002)(54906003)(70586007)(1076003)(6916009)(4326008)(8936002)(5660300002)(7416002)(70206006)(41300700001)(2616005)(26005)(6666004)(186003)(16526019)(478600001)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 23:03:25.1442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d692f9b-461a-423f-0bf9-08daf815df64 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B07A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5758 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The AMD Zen4 core supports a new feature called Automatic IBRS. It is a "set-and-forget" feature that means that, like Intel's Enhanced IBRS, h/w manages its IBRS mitigation resources automatically across CPL transitions. The feature is advertised by CPUID_Fn80000021_EAX bit 8 and is enabled by setting MSR C000_0080 (EFER) bit 21. Enable Automatic IBRS by default if the CPU feature is present. It typically provides greater performance over the incumbent generic retpolines mitigation. Reuse the SPECTRE_V2_EIBRS spectre_v2_mitigation enum. AMD Automatic IBRS and Intel Enhanced IBRS have similar bugs.c enablement. Add NO_EIBRS_PBRSB to cpu_vuln_whitelist, since AMD Automatic IBRS isn't affected by PBRSB-eIBRS. The kernel command line option spectre_v2=eibrs is used to select AMD Automatic IBRS, if available. Signed-off-by: Kim Phillips Acked-by: Dave Hansen --- Documentation/admin-guide/hw-vuln/spectre.rst | 6 +++--- .../admin-guide/kernel-parameters.txt | 6 +++--- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/bugs.c | 20 +++++++++++-------- arch/x86/kernel/cpu/common.c | 19 ++++++++++-------- 6 files changed, 32 insertions(+), 22 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/spectre.rst b/Documentation/admin-guide/hw-vuln/spectre.rst index c4dcdb3d0d45..3fe6511c5405 100644 --- a/Documentation/admin-guide/hw-vuln/spectre.rst +++ b/Documentation/admin-guide/hw-vuln/spectre.rst @@ -610,9 +610,9 @@ kernel command line. retpoline,generic Retpolines retpoline,lfence LFENCE; indirect branch retpoline,amd alias for retpoline,lfence - eibrs enhanced IBRS - eibrs,retpoline enhanced IBRS + Retpolines - eibrs,lfence enhanced IBRS + LFENCE + eibrs Enhanced/Auto IBRS + eibrs,retpoline Enhanced/Auto IBRS + Retpolines + eibrs,lfence Enhanced/Auto IBRS + LFENCE ibrs use IBRS to protect kernel Not specifying this option is equivalent to diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 6cfa6e3996cf..839fa0fefb58 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5729,9 +5729,9 @@ retpoline,generic - Retpolines retpoline,lfence - LFENCE; indirect branch retpoline,amd - alias for retpoline,lfence - eibrs - enhanced IBRS - eibrs,retpoline - enhanced IBRS + Retpolines - eibrs,lfence - enhanced IBRS + LFENCE + eibrs - Enhanced/Auto IBRS + eibrs,retpoline - Enhanced/Auto IBRS + Retpolines + eibrs,lfence - Enhanced/Auto IBRS + LFENCE ibrs - use IBRS to protect kernel Not specifying this option is equivalent to diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 861d312c7955..d5acc4dc5906 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -432,6 +432,7 @@ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" AMD No Nested Data Breakpoints */ #define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ #define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" AMD Null Selector Clears Base */ +#define X86_FEATURE_AUTOIBRS (20*32+ 8) /* "" AMD Automatic IBRS */ #define X86_FEATURE_NO_SMM_CTL_MSR (20*32+ 9) /* "" AMD SMM_CTL MSR is not present */ /* diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a85019756003..cb3d0f6e6ac2 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -25,6 +25,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ #define EFER_SCE (1<<_EFER_SCE) #define EFER_LME (1<<_EFER_LME) @@ -33,6 +34,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) /* Intel MSRs. Some also available on other CPUs */ diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 4a0add86c182..cf81848b72f4 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1238,9 +1238,9 @@ static const char * const spectre_v2_strings[] = { [SPECTRE_V2_NONE] = "Vulnerable", [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines", [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE", - [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS", - [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE", - [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines", + [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced / Automatic IBRS", + [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced / Automatic IBRS + LFENCE", + [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced / Automatic IBRS + Retpolines", [SPECTRE_V2_IBRS] = "Mitigation: IBRS", }; @@ -1309,7 +1309,7 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) cmd == SPECTRE_V2_CMD_EIBRS_LFENCE || cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) && !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { - pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n", + pr_err("%s selected but CPU doesn't have Enhanced or Automatic IBRS. Switching to AUTO select\n", mitigation_options[i].option); return SPECTRE_V2_CMD_AUTO; } @@ -1495,8 +1495,12 @@ static void __init spectre_v2_select_mitigation(void) pr_err(SPECTRE_V2_EIBRS_EBPF_MSG); if (spectre_v2_in_ibrs_mode(mode)) { - x86_spec_ctrl_base |= SPEC_CTRL_IBRS; - update_spec_ctrl(x86_spec_ctrl_base); + if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) { + msr_set_bit(MSR_EFER, _EFER_AUTOIBRS); + } else { + x86_spec_ctrl_base |= SPEC_CTRL_IBRS; + update_spec_ctrl(x86_spec_ctrl_base); + } } switch (mode) { @@ -1580,8 +1584,8 @@ static void __init spectre_v2_select_mitigation(void) /* * Retpoline protects the kernel, but doesn't protect firmware. IBRS * and Enhanced IBRS protect firmware too, so enable IBRS around - * firmware calls only when IBRS / Enhanced IBRS aren't otherwise - * enabled. + * firmware calls only when IBRS / Enhanced / Automatic IBRS aren't + * otherwise enabled. * * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because * the user might select retpoline on the kernel command line and if diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index d762654d16a0..b441758d2680 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1229,8 +1229,8 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ - VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), - VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), + VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), + VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), /* Zhaoxin Family 7 */ VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), @@ -1341,8 +1341,16 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); - if (ia32_cap & ARCH_CAP_IBRS_ALL) + /* + * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature + * flag and protect from vendor-specific bugs via the whitelist. + */ + if ((ia32_cap & ARCH_CAP_IBRS_ALL) || cpu_has(c, X86_FEATURE_AUTOIBRS)) { setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); + if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && + !(ia32_cap & ARCH_CAP_PBRSB_NO)) + setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); + } if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { @@ -1404,11 +1412,6 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) setup_force_cpu_bug(X86_BUG_RETBLEED); } - if (cpu_has(c, X86_FEATURE_IBRS_ENHANCED) && - !cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && - !(ia32_cap & ARCH_CAP_PBRSB_NO)) - setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); - if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) return; From patchwork Mon Jan 16 23:01:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 13103830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D76FC46467 for ; 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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Tom Lendacky , "Alexey Kardashevskiy" , , , Subject: [PATCH v7 7/7] x86/cpu, kvm: Propagate the AMD Automatic IBRS feature to the guest Date: Mon, 16 Jan 2023 17:01:59 -0600 Message-ID: <20230116230159.1511393-8-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230116230159.1511393-1-kim.phillips@amd.com> References: <20230116230159.1511393-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B074:EE_|DS0PR12MB7510:EE_ X-MS-Office365-Filtering-Correlation-Id: 7b655dbb-7406-4d11-0278-08daf815e955 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Va/F70FyosLkAyJ4xjDoL/GcR7+WMyBr9lp9PXaVA8dZ1SOet238HRkMHGGKa2jhS8aAGOYq87QdgIU7Ba9bo3apRL6kV7oDPLu2PMYBf5k/vj5N+Gq3c746g0TuAWhETIcr4as9m13QRSQqDF+jwUJ5IYO3OwXwqC8vwlk0bclFvMQ7j8av52lzDmmRgtRf+PWZjn6hC4+HDXXW+57+gFIs56lIgwX9HrynQ1E1CbRlVO9viRB8WJ71LTfavTEoK+v/rPklG3UWO7UTQqgxVGwgXOg4Q9DdSIbjLmvnNccPtUnUbfmgFYezj+DhmDVUZVw7uRjzXAQs14j1mRUP+w9/ZE0kDHj0G5Bu0hP2BHEsVhuYBoJy+cCrC/myggXZ/KlBo6jlkhZp1IuDJGq/6v/IWKFxfNtRHt2BPo5uutyzgqtIhEOMRb2CvDZbFxJhb5svHg60PF6ShUEGKvpq7zG80PMcX72POGFTr1dVqtYNSl+xXUDDdUfy6Tm27Gs4IX6mefKTmE6Wjvh/jGK9IGF0LJDGI8Z+858+oI2JEh1GsTr2GPCenzAz+SRMPjxih27MWiO0CHdsZRjyZxIFBTbheQPXcz23+0Dw3az+8A+a7OlcbiAiLIQUhmj6I415Je/J0fTGtAInZm5JoWCr4JlcsGlJiEzrEqz9qc0OawLA3H3J0O7O+dfsLh2WfCWLjajd+KSCDD7RoNZPKL0qUuLM6ItM1wEIDqLzjx2YYug= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(346002)(39860400002)(376002)(451199015)(36840700001)(40470700004)(46966006)(36756003)(6916009)(356005)(86362001)(8936002)(44832011)(70586007)(8676002)(70206006)(4326008)(2906002)(7416002)(81166007)(82740400003)(36860700001)(83380400001)(5660300002)(7696005)(40460700003)(316002)(6666004)(54906003)(41300700001)(40480700001)(82310400005)(478600001)(426003)(47076005)(2616005)(336012)(16526019)(1076003)(26005)(186003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 23:03:41.8228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b655dbb-7406-4d11-0278-08daf815e955 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B074.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7510 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add the AMD Automatic IBRS feature bit to those being propagated to the guest, and enable the guest EFER bit. Signed-off-by: Kim Phillips --- arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/svm/svm.c | 3 +++ arch/x86/kvm/x86.c | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 9ba75ad9d976..293ef07b34c3 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -743,7 +743,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_mask(CPUID_8000_0021_EAX, F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | - F(NULL_SEL_CLR_BASE) | 0 /* PrefetchCtlMsr */ + F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ ); if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 9a194aa1a75a..60c7c880266b 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4969,6 +4969,9 @@ static __init int svm_hardware_setup(void) tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX); + if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) + kvm_enable_efer_bits(EFER_AUTOIBRS); + /* Check for pause filtering support */ if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { pause_filter_count = 0; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index da4bbd043a7b..8dd0cb230ef5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1685,6 +1685,9 @@ static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) { + if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS)) + return false; + if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) return false;