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Reviewed-by: Rob Herring Signed-off-by: Brad Larson --- .../devicetree/bindings/arm/amd,pensando.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml diff --git a/Documentation/devicetree/bindings/arm/amd,pensando.yaml b/Documentation/devicetree/bindings/arm/amd,pensando.yaml new file mode 100644 index 000000000000..e5c2591834a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amd,pensando.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amd,pensando.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Platforms + +maintainers: + - Brad Larson + +properties: + $nodename: + const: "/" + compatible: + oneOf: + + - description: Boards with Pensando Elba SoC + items: + - enum: + - amd,pensando-elba-ortano + - const: amd,pensando-elba + +additionalProperties: true + +... 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Signed-off-by: Brad Larson --- Changes since v6: - Add reset-names and resets properties - Add if/then on property amd,pensando-elba-sd4hc to set reg property values for minItems and maxItems --- .../devicetree/bindings/mmc/cdns,sdhci.yaml | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml index 8b1a0fdcb5e3..f7dd6f990f96 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -16,12 +16,14 @@ properties: compatible: items: - enum: + - amd,pensando-elba-sd4hc - microchip,mpfs-sd4hc - socionext,uniphier-sd4hc - const: cdns,sd4hc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: maxItems: 1 @@ -111,12 +113,36 @@ properties: minimum: 0 maximum: 0x7f + reset-names: + items: + - const: hw + + resets: + description: + optional. phandle to the system reset controller with line index + for mmc hw reset line if exists. + maxItems: 1 + required: - compatible - reg - interrupts - clocks +if: + properties: + compatible: + const: amd,pensando-elba-sd4hc +then: + properties: + reg: + minItems: 2 +else: + properties: + reg: + minItems: 1 + maxItems: 2 + unevaluatedProperties: false examples: From patchwork Thu Jan 19 03:51:24 2023 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:26.6105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b603af82-32b6-49e8-d5c6-08daf9d09492 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5815 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Document the cadence qspi controller compatible for AMD Pensando Elba SoC boards. The Elba qspi fifo size is 1024. Signed-off-by: Brad Larson --- Changes since v6: - Add 1024 to cdns,fifo-depth property to resolve dtbs_check error --- .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 4707294d8f59..a6556854234f 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -20,11 +20,23 @@ allOf: required: - power-domains + - if: + properties: + compatible: + enum: + - amd,pensando-elba-qspi + then: + properties: + cdns,fifo-depth: + enum: [ 128, 256, 1024 ] + default: 1024 + properties: compatible: oneOf: - items: - enum: + - amd,pensando-elba-qspi - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi @@ -48,7 +60,7 @@ properties: description: Size of the data FIFO in words. $ref: "/schemas/types.yaml#/definitions/uint32" - enum: [ 128, 256 ] + enum: [ 128, 256, 1024 ] default: 128 cdns,fifo-width: From patchwork Thu Jan 19 03:51:25 2023 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:29.6571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d19d78c4-7b59-46e1-b7f4-08daf9d09663 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT046.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6028 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The AMD Pensando Elba SoC has integrated the DW APB SPI Controller Signed-off-by: Brad Larson --- Changes since v6: - Define property amd,pensando-elba-syscon - Move compatible amd,pensando-elba-spi ahead of baikal,bt1-ssi --- .../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index d33b72fabc5d..96b072835de0 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -37,6 +37,18 @@ allOf: else: required: - interrupts + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-spi + then: + properties: + amd,pensando-elba-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: AMD Pensando Elba SoC system controller + required: + - amd,pensando-elba-syscon properties: compatible: @@ -63,6 +75,8 @@ properties: const: intel,keembay-ssi - description: Intel Thunder Bay SPI Controller const: intel,thunderbay-ssi + - description: AMD Pensando Elba SoC SPI Controller + const: amd,pensando-elba-spi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller From patchwork Thu Jan 19 03:51:26 2023 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:32.8535 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ddc0077-103b-4ca0-371c-08daf9d09850 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8211 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add the AMD Pensando Elba SoC system registers compatible Acked-by: Rob Herring Signed-off-by: Brad Larson --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 1b01bd010431..f4b0ed4ff03c 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -38,6 +38,7 @@ properties: - allwinner,sun8i-h3-system-controller - allwinner,sun8i-v3s-system-controller - allwinner,sun50i-a64-system-controller + - amd,pensando-elba-syscon - brcm,cru-clkset - freecom,fsg-cs2-system-controller - fsl,imx93-aonmix-ns-syscfg From patchwork Thu Jan 19 03:51:27 2023 Content-Type: text/plain; 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Thu, 19 Jan 2023 03:52:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT099.mail.protection.outlook.com (10.13.175.171) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6002.13 via Frontend Transport; Thu, 19 Jan 2023 03:52:35 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 18 Jan 2023 21:52:31 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 06/15] dt-bindings: mfd: amd,pensando-elbasr: Add AMD Pensando System Resource chip Date: Wed, 18 Jan 2023 19:51:27 -0800 Message-ID: <20230119035136.21603-7-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119035136.21603-1-blarson@amd.com> References: <20230119035136.21603-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT099:EE_|MN2PR12MB4079:EE_ X-MS-Office365-Filtering-Correlation-Id: fe0166cb-2001-4a19-45b7-08daf9d099ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:35.5827 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe0166cb-2001-4a19-45b7-08daf9d099ee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT099.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4079 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add support for the AMD Pensando SoC System Resource chip using the SPI interface. The device functions are accessed using four chip-selects. This device is present for all Pensando SoC designs. Signed-off-by: Brad Larson --- Changes since v6: - Instead of four nodes, one per chip-select, a single node is used with reset-cells in the parent. - No MFD API is used anymore in the driver so it made sense to move this to drivers/spi. - This driver is common for all Pensando SoC based designs so changed the name to pensando-sr.c to not make it Elba SoC specific. - Added property cs for the chip-select number which is used by the driver to create /dev/pensr0. --- .../bindings/spi/amd,pensando-sr.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/amd,pensando-sr.yaml diff --git a/Documentation/devicetree/bindings/spi/amd,pensando-sr.yaml b/Documentation/devicetree/bindings/spi/amd,pensando-sr.yaml new file mode 100644 index 000000000000..8504652f6e19 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/amd,pensando-sr.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/amd,pensando-sr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Resource Controller + +description: | + AMD Pensando SoC Resource Controller is a set of + control/status registers accessed on four chip-selects. + This device is present in all Pensando SoC based designs. + +maintainers: + - Brad Larson + +properties: + compatible: + contains: + enum: + - amd,pensando-sr + + reg: + minItems: 1 + + cs: + minItems: 1 + maxItems: 4 + description: + Device chip select + + '#reset-cells': + const: 1 + + interrupts: + maxItems: 1 + + spi-max-frequency: true + +required: + - compatible + - cs + - spi-max-frequency + - '#reset-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + + system-controller@0 { + compatible = "amd,pensando-sr"; + reg = <0>; + cs = <0 1 2 3>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; + }; + +... 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:39.7543 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f871b305-0398-468f-cfc9-08daf9d09c6a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT099.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8307 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add entry for AMD PENSANDO maintainer and files Signed-off-by: Brad Larson --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f61eb221415b..74eb977badb4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1890,6 +1890,14 @@ N: allwinner N: sun[x456789]i N: sun50i +ARM/AMD PENSANDO ARM64 ARCHITECTURE +M: Brad Larson +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/amd,pensando* +F: arch/arm64/boot/dts/amd/elba* +F: drivers/spi/spi-pensando-sr.c + ARM/Amlogic Meson SoC CLOCK FRAMEWORK M: Neil Armstrong M: Jerome Brunet From patchwork Thu Jan 19 03:51:29 2023 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:41.3323 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7784123c-8144-48c0-9996-08daf9d09d5b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT099.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4306 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add ARCH_PENSANDO configuration option for AMD Pensando SoC based platforms. Signed-off-by: Brad Larson --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index d1970adf80ab..11d4f73cd341 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -236,6 +236,18 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. +config ARCH_PENSANDO + bool "AMD Pensando Platforms" + help + This enables support for the ARMv8 based AMD Pensando SoC + family to include the Elba SoC. + + AMD Pensando SoCs support a range of Distributed Services + Cards in PCIe format installed into servers. The Elba + SoC includes 16 A-72 CPU cores, 144 programmable P4 + cores for a minimal latency/jitter datapath, and network + interfaces up to 200 Gb/s. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From patchwork Thu Jan 19 03:51:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 13107370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA342C00A5A for ; Thu, 19 Jan 2023 04:16:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230087AbjASEIr (ORCPT ); Wed, 18 Jan 2023 23:08:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229926AbjASD4k (ORCPT ); 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Wed, 18 Jan 2023 21:52:40 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 09/15] arm64: dts: Add AMD Pensando Elba SoC support Date: Wed, 18 Jan 2023 19:51:30 -0800 Message-ID: <20230119035136.21603-10-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119035136.21603-1-blarson@amd.com> References: <20230119035136.21603-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT027:EE_|CH2PR12MB4118:EE_ X-MS-Office365-Filtering-Correlation-Id: 7b3e0d97-7131-4c50-2b9e-08daf9d0a3c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CUfl6dvGblkl5p59EVqBtiRjlDN0V5MsHYIVWT7pHupW0DVfY0eQwD5DDqyw9BgG8LwwVT7YMayVwKIcgh2Oq2siR55bM1cfZ83Sd8xQolKfpRCgJOM1w13/fDaPRDiG0biyiqI98DV+u+XZj6zf3jGgbZh4Np2zECBVGUZxpAve9ZawCFALGhPam3od086AfylSYbCts8AQS2KMg8YGu7sHSLw14VqyaXWZMfRMydDjQlQv1zV+ZkTCR1kDUTICmEyv/Z1LPyZncajII48QZzxNXqDg6LhM5G9XqNNg7dSuAk2HLiz2OnwXGF9u+jLIb+ZpfLg5vU1A0KzodDlt7neMEWYA2ZjdBUkwmG+8nvoPzJTkDCcu4pRO45/2BOZ6+5uSbYWFeJK5FnKvjcOEyz0uqo/rQYlcBE34hFO8bpHU5Cvef2JhLLRPMUboYJ1Qf9WnhAi6SQ7IPXLyul12fHQXtqBOjTuEJ/eSrx5s3TZMfOJXHnVCAWIPg2OsA9fgiw4c+wJg9cYFoehT7EMVYk2FIElPNMfvQXs1WdhYLfOEFnvcquExWH+PDoO0NJZkEwLQ1SQSaWur8AVRz1DwD66hrO3NdxCg49nOtUYUnO0vTHJCTdh8+jRRK/TFLWQS2pHNgZIupMmFdFBAfZV1yx8R8HgSR3lVc4YhgD1pz6f6OezMfL7/P4drulfXYYtDHuOhS+4oCClVTIgSZ0adgMVNlau7hWl1N6pUmACuff8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(376002)(346002)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(81166007)(82740400003)(70206006)(36860700001)(356005)(8936002)(5660300002)(30864003)(7416002)(2906002)(70586007)(7406005)(4326008)(40480700001)(8676002)(16526019)(40460700003)(41300700001)(6916009)(82310400005)(2616005)(26005)(186003)(1076003)(336012)(83380400001)(426003)(47076005)(6666004)(316002)(54906003)(478600001)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:52.0971 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7b3e0d97-7131-4c50-2b9e-08daf9d0a3c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4118 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add AMD Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson --- Changes since v6: - Single node for spi0 system-controller and squash the reset-controller child into parent --- arch/arm64/boot/dts/amd/Makefile | 1 + arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++ arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 82 ++++++++ arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ arch/arm64/boot/dts/amd/elba.dtsi | 192 ++++++++++++++++++ 6 files changed, 598 insertions(+) create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile index 68103a8b0ef5..8502cc2afbc5 100644 --- a/arch/arm64/boot/dts/amd/Makefile +++ b/arch/arm64/boot/dts/amd/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi new file mode 100644 index 000000000000..37aadd442db8 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + }; + + cluster1 { + core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; + }; + + cluster2 { + core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; + core2 { cpu = <&cpu10>; }; + core3 { cpu = <&cpu11>; }; + }; + + cluster3 { + core0 { cpu = <&cpu12>; }; + core1 { cpu = <&cpu13>; }; + core2 { cpu = <&cpu14>; }; + core3 { cpu = <&cpu15>; }; + }; + }; + + /* CLUSTER 0 */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x0>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x1>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x2>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x3>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + }; + + /* CLUSTER 1 */ + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x100>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x101>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x102>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x103>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + }; + + /* CLUSTER 2 */ + cpu8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x200>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x201>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x202>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x203>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + l2_2: l2-cache2 { + compatible = "cache"; + }; + + /* CLUSTER 3 */ + cpu12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x300>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x301>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x302>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x303>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + l2_3: l2-cache3 { + compatible = "cache"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi new file mode 100644 index 000000000000..1abcb1264108 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&ahb_clk { + clock-frequency = <400000000>; +}; + +&emmc_clk { + clock-frequency = <200000000>; +}; + +&flash_clk { + clock-frequency = <400000000>; +}; + +&ref_clk { + clock-frequency = <156250000>; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + cdns,read-delay = <0>; + cdns,tshsl-ns = <0>; + cdns,tsd2d-ns = <0>; + cdns,tchsh-ns = <0>; + cdns,tslch-ns = <0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-hw-reset; + reset-names = "hw"; + resets = <&rstc 0>; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, + <&porta 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + rstc: system-controller@0 { + compatible = "amd,pensando-sr"; + reg = <0>; + cs = <0 1 2 3>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts new file mode 100644 index 000000000000..c3f4da2f7449 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Device Tree file for AMD Pensando Elba Board. + * + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" + +/ { + model = "AMD Pensando Elba Board"; + compatible = "amd,pensando-elba-ortano", "amd,pensando-elba"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + spi1 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi new file mode 100644 index 000000000000..734893fef2c3 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "flash"; + reg = <0x10000 0xfff0000>; + }; + + partition@f0000 { + label = "golduenv"; + reg = <0xf0000 0x10000>; + }; + + partition@100000 { + label = "boot0"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "golduboot"; + reg = <0x180000 0x200000>; + }; + + partition@380000 { + label = "brdcfg0"; + reg = <0x380000 0x10000>; + }; + + partition@390000 { + label = "brdcfg1"; + reg = <0x390000 0x10000>; + }; + + partition@400000 { + label = "goldfw"; + reg = <0x400000 0x3c00000>; + }; + + partition@4010000 { + label = "fwmap"; + reg = <0x4010000 0x20000>; + }; + + partition@4030000 { + label = "fwsel"; + reg = <0x4030000 0x20000>; + }; + + partition@4090000 { + label = "bootlog"; + reg = <0x4090000 0x20000>; + }; + + partition@40b0000 { + label = "panicbuf"; + reg = <0x40b0000 0x20000>; + }; + + partition@40d0000 { + label = "uservars"; + reg = <0x40d0000 0x20000>; + }; + + partition@4200000 { + label = "uboota"; + reg = <0x4200000 0x400000>; + }; + + partition@4600000 { + label = "ubootb"; + reg = <0x4600000 0x400000>; + }; + + partition@4a00000 { + label = "mainfwa"; + reg = <0x4a00000 0x1000000>; + }; + + partition@5a00000 { + label = "mainfwb"; + reg = <0x5a00000 0x1000000>; + }; + + partition@6a00000 { + label = "diaguboot"; + reg = <0x6a00000 0x400000>; + }; + + partition@8000000 { + label = "diagfw"; + reg = <0x8000000 0x7fe0000>; + }; + + partition@ffe0000 { + label = "ubootenv"; + reg = <0xffe0000 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi new file mode 100644 index 000000000000..285d776aa67b --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +#include +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + model = "Elba ASIC Board"; + compatible = "amd,pensando-elba"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + dma-coherent; + + ahb_clk: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + emmc_clk: oscillator2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + flash_clk: oscillator3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + ref_clk: oscillator4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@400 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x400 0x0 0x100>; + clocks = <&ahb_clk>; + #address-cells = <1>; + #size-cells = <0>; + i2c-sda-hold-time-ns = <480>; + snps,sda-timeout-ms = <750>; + interrupts = ; + status = "disabled"; + }; + + wdt0: watchdog@1400 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x1400 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + + qspi: spi@2400 { + compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor"; + reg = <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&flash_clk>; + cdns,fifo-depth = <1024>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x7fff0000>; + status = "disabled"; + }; + + spi0: spi@2800 { + compatible = "amd,pensando-elba-spi"; + reg = <0x0 0x2800 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + amd,pensando-elba-syscon = <&syscon>; + clocks = <&ahb_clk>; + interrupts = ; + num-cs = <2>; + status = "disabled"; + }; + + gpio0: gpio@4000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x4000 0x0 0x78>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; + + uart0: serial@4800 { + compatible = "ns16550a"; + reg = <0x0 0x4800 0x0 0x100>; + clocks = <&ref_clk>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + gic: interrupt-controller@800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ + <0x0 0xa00000 0x0 0x200000>, /* GICR */ + <0x0 0x60000000 0x0 0x2000>, /* GICC */ + <0x0 0x60010000 0x0 0x1000>, /* GICH */ + <0x0 0x60020000 0x0 0x2000>; /* GICV */ + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + ranges; + interrupt-controller; + interrupts = ; + + /* + * Elba specific pre-ITS is enabled using the + * existing property socionext,synquacer-pre-its + */ + gic_its: msi-controller@820000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x820000 0x0 0x10000>; + msi-controller; + #msi-cells = <1>; + socionext,synquacer-pre-its = + <0xc00000 0x1000000>; + }; + }; + + emmc: mmc@30440000 { + compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc"; + reg = <0x0 0x30440000 0x0 0x10000>, + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ + clocks = <&emmc_clk>; + interrupts = ; + cdns,phy-input-delay-sd-highspeed = <0x4>; + cdns,phy-input-delay-legacy = <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>; + mmc-ddr-1_8v; + status = "disabled"; + }; + + syscon: syscon@307c0000 { + compatible = "amd,pensando-elba-syscon", "syscon"; + reg = <0x0 0x307c0000 0x0 0x3000>; + }; + }; +}; From patchwork Thu Jan 19 03:51:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 13107386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9382EC678D4 for ; Thu, 19 Jan 2023 04:18:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229540AbjASERr (ORCPT ); Wed, 18 Jan 2023 23:17:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230130AbjASEJA (ORCPT ); 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Wed, 18 Jan 2023 21:52:48 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 10/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Wed, 18 Jan 2023 19:51:31 -0800 Message-ID: <20230119035136.21603-11-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119035136.21603-1-blarson@amd.com> References: <20230119035136.21603-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT027:EE_|IA1PR12MB8519:EE_ X-MS-Office365-Filtering-Correlation-Id: 29024b7a-1eb3-4428-7347-08daf9d0a55b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GbrIGNeWJjCYz93GGOL0rpN/lbrcpICbo3kxJxlGMu/ve9YXdoAl2QZqzb8MkY0H578lNgrO5SQg2kVfO0JlOf9EbVBU+JGu0a8a6L/F5WWXO7pMYkYMoHNz4q9Kx8w6ogLYWuLTHvsWXEA8SPcW1gb+oO8LbOMoO8uMDPl7ONYKtWvmbrJq4/MR8klwg11v68B8eM11AMDJUyxcdqr78U+AQZxiMJHZATjuTFUPGDg/jDGlcuX6I7eitwIVHJBh/94YAzRweCXEsB+J+zf7rZrBOGl8wkNkIUzZ/qeL4Hhl3G3h52Yi55OhmSg1AK2Yvs1CpaiAwOT8IecSfa+2jPYVr7qiT+DYVSwxh3Rv+Rws+gw1GeQYyGmMfs7+EefXTJf6VlRsCbK3L3zEWTUJygIEPLsA9vLnP+LsRh8isrz8IJAVzlKtpyNd+GmsZK6o1HW57ylTLT6eN55SRy3jfpWyLJPln3/vziM+aRUaBkCR92IYBUw9dcC67sa9EapGdLBDj3SdiU9K5RHpj40RRsCPUSxjAUI6M5kFIJP+Ex4JszsLD/XKKNN7lFuFHvrqkbriFyryQutcBBRAktQ0JBS4OPl+7ShBCgDYj8fwYoWngQ8KDZLiA9GzK8NcToIKnq5hoxrRp6Anozf55xhsaQH+MFbg65AJpcZgewM4AEaWW9APFUnN5KKfqKFkW+0DJAq16I/slGhoffyATn0vjBf4/0HG14oo0+ZRovbKj6o= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(346002)(376002)(136003)(451199015)(36840700001)(40470700004)(46966006)(40460700003)(82740400003)(81166007)(8936002)(7416002)(16526019)(5660300002)(7406005)(6666004)(36860700001)(36756003)(41300700001)(8676002)(6916009)(40480700001)(82310400005)(1076003)(70586007)(2906002)(426003)(4326008)(47076005)(336012)(70206006)(2616005)(54906003)(356005)(26005)(316002)(478600001)(186003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:54.7688 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 29024b7a-1eb3-4428-7347-08daf9d0a55b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8519 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson --- Changes since v6: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 676313e1bdad..e042781d3db5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -89,6 +90,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -978,6 +980,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1700,6 +1709,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion = false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram = true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1825,6 +1836,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pensando_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1850,6 +1865,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pensando_cdns_qspi, + }, { /* end of table */ } }; From patchwork Thu Jan 19 03:51:32 2023 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:56.2218 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf8082cd-80d4-4fdc-2983-08daf9d0a639 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6918 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller with device specific chip-select control. The Elba SoC provides four chip-selects where the native DW IP supports two chip-selects. The Elba DW_SPI instance has two native CS signals that are always overridden. Signed-off-by: Brad Larson --- Changes since v6: - Add use of macros GENMASK() and BIT() - Change ELBA_SPICS_SHIFT() to ELBA_SPICS_OFFSET() --- drivers/spi/spi-dw-mmio.c | 78 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 26c40ea6dd12..9b6f876227e8 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -53,6 +53,24 @@ struct dw_spi_mscc { void __iomem *spi_mst; /* Not sparx5 */ }; +struct dw_spi_elba { + struct regmap *syscon; +}; + +/* + * Elba SoC does not use ssi, pin override is used for cs 0,1 and + * gpios for cs 2,3 as defined in the device tree. + * + * cs: | 1 0 + * bit: |---3-------2-------1-------0 + * | cs1 cs1_ovr cs0 cs0_ovr + */ +#define ELBA_SPICS_REG 0x2468 +#define ELBA_SPICS_OFFSET(cs) ((cs) << 1) +#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs)) +#define ELBA_SPICS_SET(cs, val) \ + ((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs)) + /* * The Designware SPI controller (referred to as master in the documentation) * automatically deasserts chip select when the tx fifo is empty. The chip @@ -237,6 +255,65 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev, return 0; } +static void dw_spi_elba_override_cs(struct dw_spi_elba *dwselba, int cs, int enable) +{ + regmap_update_bits(dwselba->syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs), + ELBA_SPICS_SET(cs, enable)); + +} + +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws = spi_master_get_devdata(spi->master); + struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); + struct dw_spi_elba *dwselba = dwsmmio->priv; + u8 cs; + + cs = spi->chip_select; + if (cs < 2) + dw_spi_elba_override_cs(dwselba, spi->chip_select, enable); + + /* + * The DW SPI controller needs a native CS bit selected to start + * the serial engine. + */ + spi->chip_select = 0; + dw_spi_set_cs(spi, enable); + spi->chip_select = cs; +} + +static int dw_spi_elba_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + const char *syscon_name = "amd,pensando-elba-syscon"; + struct device_node *np = pdev->dev.of_node; + struct dw_spi_elba *dwselba; + struct device_node *node; + struct regmap *regmap; + + node = of_parse_phandle(np, syscon_name, 0); + if (!node) { + dev_err(&pdev->dev, "failed to find %s\n", syscon_name); + return -ENODEV; + } + + regmap = syscon_node_to_regmap(node); + if (IS_ERR(regmap)) { + dev_err(&pdev->dev, "syscon regmap lookup failed\n"); + return PTR_ERR(regmap); + } + + dwselba = devm_kzalloc(&pdev->dev, sizeof(*dwselba), GFP_KERNEL); + if (!dwselba) + return -ENOMEM; + + dwselba->syscon = regmap; + dwsmmio->priv = dwselba; + dwsmmio->dws.set_cs = dw_spi_elba_set_cs; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +429,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init}, { /* end of table */} }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:58.9091 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ebe0c8a-02f8-4e04-35bf-08daf9d0a7d3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6842 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org SoCs with device specific Cadence implementation, such as setting byte-enables before the write, need to override writel(). Add a callback where the default is writel() for all existing chips. Signed-off-by: Brad Larson --- Changes since v6: - No change to this patch but as some patches are deleted and this is a respin the three successive patches to sdhci-cadence.c are patches 12, 13, and 14 which do the following: 1. Add ability for Cadence specific design to have priv writel(). 2. Add Elba SoC support that requires its own priv writel() for byte-lane control . 3. Add support for mmc hardware reset. --- drivers/mmc/host/sdhci-cadence.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 6f2de54a5987..708d4297f241 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -67,6 +67,7 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; bool enhanced_strobe; + void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -90,6 +91,12 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, }; +static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + writel(val, reg); +} + static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, u8 addr, u8 data) { @@ -104,17 +111,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); tmp |= SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); if (ret) return ret; tmp &= ~SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 0, 10); @@ -191,7 +198,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); tmp &= ~SDHCI_CDNS_HRS06_MODE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); + priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); } static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) @@ -223,7 +230,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) */ for (i = 0; i < 2; i++) { tmp |= SDHCI_CDNS_HRS06_TUNE_UP; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), @@ -386,6 +393,7 @@ static int sdhci_cdns_probe(struct platform_device *pdev) priv->nr_phy_params = nr_phy_params; priv->hrs_addr = host->ioaddr; priv->enhanced_strobe = false; + priv->priv_writel = cdns_writel; host->ioaddr += SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe; From patchwork Thu Jan 19 03:51:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 13107375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61B16C00A5A for ; Thu, 19 Jan 2023 04:18:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230467AbjASERl (ORCPT ); Wed, 18 Jan 2023 23:17:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230182AbjASEJA (ORCPT ); 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Wed, 18 Jan 2023 21:52:56 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Date: Wed, 18 Jan 2023 19:51:34 -0800 Message-ID: <20230119035136.21603-14-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119035136.21603-1-blarson@amd.com> References: <20230119035136.21603-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT027:EE_|DS7PR12MB8249:EE_ X-MS-Office365-Filtering-Correlation-Id: 04ee84fc-d626-468e-b6bb-08daf9d0a858 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: B3R2yumuqZgFzcecbh2Mk0/O77KzzU40GVKbWHw3op1Bz7GEOlFXwS3IOuHfv7Z1+cuMgHPnAfqGdX5/iKH2DyxoJbGU6ZXG4ASPy3hHY31YW1t2FP+3DM0g92yS2o70GZ/5cJu1Yp3ZH9+MH+MP9xlC6DCBTGBpLToNzeBx0cOJymQdahAxKwx9YD5PLrPbSKaq1ITm50qkFUjEmvjtUR1rKHueERjCaDRkcvgUK9tEMm/V+4cHeAZfybWu4Pxt2W4UOmY8MEJu+TGpaL5zVfp0BOO6rmCiiniRmUOTHwtZ8nCftNRrZCNntlUiLCftHTQ9oxZn8K47Z0QMd7+OwVMx8/f+N6KsOhV9dT/1MRMm7TleNyHEGLKGvJ1aneN/OziMtEktJhsCGk7cWwq3nQN5u57f54lRLe8QI86vmu/n75YTIkviDjNZqZwNp83UrF+nAGcER4Y1M8+8WZVDzBuUJBj3L+PHX4wIMNR+Z35RoW82mF2qMzqWw/0XCp7iuO5Lpoul9HKBTmUPKS4VHFQ8eufidRl5CU31aza34soklEihVkQbd3NHsORAB1WUJydLjv8yhkIqV0e1wEiN0oh0DpcbyWBmicC7r37E9sA7s2orGOxJAwd/0Z5S8G0v2dxKT+IlfacdP3OX1/gRUrPMOOS5V6qI/rInINW5PvrfKvDPDPzpyzBa6YZZAnWtVB/sD/V25tpfKt5Ni7/TKg3wosSPJWntBmKwy50L8Z4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(346002)(396003)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(36756003)(82310400005)(4326008)(2616005)(426003)(47076005)(6916009)(41300700001)(16526019)(70206006)(70586007)(26005)(8676002)(186003)(83380400001)(7416002)(316002)(2906002)(6666004)(478600001)(7406005)(356005)(40480700001)(54906003)(40460700003)(81166007)(36860700001)(336012)(8936002)(1076003)(82740400003)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:52:59.7840 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04ee84fc-d626-468e-b6bb-08daf9d0a858 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8249 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add support for AMD Pensando Elba SoC which explicitly controls byte-lane enables on writes. Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which allows Elba SoC sdhci_elba_ops to overwrite the SDHCI IO memory accessors. Signed-off-by: Brad Larson --- Changes since v6: - Previously patch 16/17 --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 131 ++++++++++++++++++++++++++++--- 2 files changed, 123 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 5e19a961c34d..9e41115cc753 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -255,6 +255,7 @@ config MMC_SDHCI_CADENCE tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" depends on MMC_SDHCI_PLTFM depends on OF + select MMC_SDHCI_IO_ACCESSORS help This selects the Cadence SD/SDIO/eMMC driver. diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 708d4297f241..e92aa79a8be2 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; + void __iomem *ctl_addr; /* write control */ + spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); unsigned int nr_phy_params; @@ -77,6 +79,11 @@ struct sdhci_cdns_phy_cfg { u8 addr; }; +struct sdhci_cdns_drv_data { + int (*init)(struct platform_device *pdev); + const struct sdhci_pltfm_data pltfm_data; +}; + static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, @@ -316,6 +323,92 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, sdhci_set_uhs_signaling(host, timing); } +/* Elba control register bits [6:3] are byte-lane enables */ +#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) + +/* + * The Pensando Elba SoC explicitly controls byte-lane enabling on writes + * which includes writes to the HRS registers. + */ +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + writel(val, reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) +{ + elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg); +} + +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables = GENMASK(1, 0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writew(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables = BIT(0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writeb(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static const struct sdhci_ops sdhci_elba_ops = { + .write_l = elba_write_l, + .write_w = elba_write_w, + .write_b = elba_write_b, + .set_clock = sdhci_set_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, +}; + +static int elba_drv_init(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + struct resource *iomem; + void __iomem *ioaddr; + + host->mmc->caps |= (MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA); + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!iomem) + return -ENOMEM; + + /* Byte-lane control register */ + ioaddr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ioaddr)) + return PTR_ERR(ioaddr); + + priv->ctl_addr = ioaddr; + priv->priv_writel = elba_priv_writel; + spin_lock_init(&priv->wrlock); + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + + return 0; +} + static const struct sdhci_ops sdhci_cdns_ops = { .set_clock = sdhci_set_clock, .get_timeout_clock = sdhci_cdns_get_timeout_clock, @@ -325,13 +418,24 @@ static const struct sdhci_ops sdhci_cdns_ops = { .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, }; -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = { - .ops = &sdhci_cdns_ops, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, }; -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { - .ops = &sdhci_cdns_ops, +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = { + .init = elba_drv_init, + .pltfm_data = { + .ops = &sdhci_elba_ops, + }, +}; + +static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + }, }; static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, @@ -357,7 +461,7 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; - const struct sdhci_pltfm_data *data; + const struct sdhci_cdns_drv_data *data; struct sdhci_pltfm_host *pltfm_host; struct sdhci_cdns_priv *priv; struct clk *clk; @@ -376,10 +480,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev) data = of_device_get_match_data(dev); if (!data) - data = &sdhci_cdns_pltfm_data; + data = &sdhci_cdns_drv_data; nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node); - host = sdhci_pltfm_init(pdev, data, + host = sdhci_pltfm_init(pdev, &data->pltfm_data, struct_size(priv, phy_params, nr_phy_params)); if (IS_ERR(host)) { ret = PTR_ERR(host); @@ -397,6 +501,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev) host->ioaddr += SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe; + if (data->init) { + ret = data->init(pdev); + if (ret) + goto free; + } sdhci_enable_v4_mode(host); __sdhci_read_caps(host, &version, NULL, NULL); @@ -461,7 +570,11 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops = { static const struct of_device_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc", - .data = &sdhci_cdns_uniphier_pltfm_data, + .data = &sdhci_cdns_uniphier_drv_data, + }, + { + .compatible = "amd,pensando-elba-sd4hc", + .data = &sdhci_elba_drv_data, }, { .compatible = "cdns,sd4hc" }, { /* sentinel */ } From patchwork Thu Jan 19 03:51:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 13107371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FE77C678DD for ; Thu, 19 Jan 2023 04:16:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230186AbjASEJT (ORCPT ); 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Wed, 18 Jan 2023 21:52:59 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 14/15] mmc: sdhci-cadence: Support mmc hardware reset Date: Wed, 18 Jan 2023 19:51:35 -0800 Message-ID: <20230119035136.21603-15-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230119035136.21603-1-blarson@amd.com> References: <20230119035136.21603-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT042:EE_|CY8PR12MB7634:EE_ X-MS-Office365-Filtering-Correlation-Id: 32efbb21-267e-4d7a-37b6-08daf9d0aa75 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ndwRT0jnZPfoV7ON/VwYVjHTaDlQqQ8ep80VQBetI2vvHW5sHxS2IoT1ZSzUsOB28JjgCfoDQ5RjuEu+siE0QyifJZqaK1REF71WHthUtGi1kvFLJx+yHTPatCJY66dWdk6x3McTzx9XWfNUM4gVfsLxkexZEiHApxSBEYx03BthZbUUAUfjO+J2UH3R7P19in8dt8M+u69buzXi+9m6TSTh39nnTkAapxbCDJqQ1B7KlNps6fbe2jmRHH75WRh2/XJd1ds81/jf9cGbT1uSq7R3qx5vnUPzbTo/WRb0GLcdBtZGxuK0FSlHoj2g/2cOigc4ljpN0kpM6Ah4KyhAQMU/IlpXB51/lAcdJJ+wwTJdowuANt0LJ1xbqDSiHYbxgf7jLIPm6sskR2UWr4kDVDmBkbd9iB39wFCJql1Tf/5wpmiixiJy+s/+4cbrsmPcErlyAErFbI/Fs0QFVoqdJUxH0255aamP+D9qhYIRze4vZpLi7PrvvLlc2IvhkRPUqcDeQfZGuAchwo1vyj1ww/ZPD7sXzTQQ83vdvLxg/ju14DuoXVLzie9H/T1Hwe7l/h7GillFSzs+5WcSUZZC899syZslq9rs0cL2qnhAPHNvtnIK0Ez67u6JX9qDga/jNpf4sOU74/Ixaw0aYkEj+d96g8D202H4+Qt3O1zBCRC+BD8tbydfMY0oCH3xSdyjOLGgDFKNpHTzY4/8HG5m5yEXSbqcZlVGOnyQmROz+lA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(136003)(346002)(39860400002)(376002)(451199015)(36840700001)(40470700004)(46966006)(36756003)(40480700001)(54906003)(186003)(316002)(40460700003)(6666004)(478600001)(36860700001)(5660300002)(7406005)(7416002)(2906002)(8676002)(70206006)(4326008)(8936002)(6916009)(41300700001)(70586007)(356005)(82740400003)(82310400005)(81166007)(336012)(2616005)(1076003)(26005)(16526019)(83380400001)(426003)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:53:03.3106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 32efbb21-267e-4d7a-37b6-08daf9d0aa75 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7634 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add support for mmc hardware reset using a reset-controller that would need to be enabled in the device tree with a supporting driver. The default is disabled for all existing designs. Signed-off-by: Brad Larson --- Changes since v6: - Previously patch 17/17 - Changed delay after reset_control_assert() from 9 to 3 usec - Renamed sdhci_mmc_hw_reset() to sdhci_cdns_mmc_hw_reset() --- drivers/mmc/host/sdhci-cadence.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index e92aa79a8be2..62321cef41db 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "sdhci-pltfm.h" @@ -70,6 +71,7 @@ struct sdhci_cdns_priv { spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); + struct reset_control *rst_hw; unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -458,6 +460,24 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, SDHCI_CDNS_HRS06_MODE_MMC_HS400); } +extern unsigned int sdhci_timeout_val; + +static void sdhci_cdns_mmc_hw_reset(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + + dev_dbg(mmc_dev(host->mmc), "emmc hardware reset\n"); + + reset_control_assert(priv->rst_hw); + /* For eMMC, minimum is 1us but give it 3us for good measure */ + udelay(3); + + reset_control_deassert(priv->rst_hw); + /* For eMMC, minimum is 200us but give it 300us for good measure */ + usleep_range(300, 1000); +} + static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; @@ -521,6 +541,17 @@ static int sdhci_cdns_probe(struct platform_device *pdev) if (ret) goto free; + if (host->mmc->caps & MMC_CAP_HW_RESET) { + priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, "hw"); + if (IS_ERR(priv->rst_hw)) { + ret = PTR_ERR(priv->rst_hw); + if (ret == -ENOENT) + priv->rst_hw = NULL; + } else { + host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset; + } + } + ret = sdhci_add_host(host); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 03:53:06.0816 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d6c73c3-faea-4ef6-a6e6-08daf9d0ac19 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8082 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add support for the AMD Pensando SoC System Resource chip using the SPI interface. The device functions are accessed using four chip-selects and the device can be a CPLD or FPGA depending on functionality. Signed-off-by: Brad Larson --- Changes since v6: - Previously patch 14/17 - After the change to the device tree node and squashing reset-cells into the parent simplified this to not use any MFD API and move it to drivers/spi/pensando-sr.c. - Change the naming to remove elba since this driver is common for all Pensando SoC designs . - Default yes SPI_PENSANDO_SR for ARCH_PENSANDO --- drivers/spi/Kconfig | 14 ++ drivers/spi/Makefile | 1 + drivers/spi/spi-pensando-sr.c | 454 ++++++++++++++++++++++++++++++++++ 3 files changed, 469 insertions(+) create mode 100644 drivers/spi/spi-pensando-sr.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3b1c0878bb85..1e8605c59a0e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -730,6 +730,20 @@ config SPI_PCI1XXXX This driver can be built as module. If so, the module will be called as spi-pci1xxxx. +config SPI_PENSANDO_SR + bool "AMD Pensando SoC System Resource chip" + depends on SPI_MASTER=y + depends on (ARCH_PENSANDO && OF) || COMPILE_TEST + default y if ARCH_PENSANDO + select REGMAP_SPI + select MFD_SYSCON + help + Support for the AMD Pensando SoC System Resource chip using the + SPI interface. This driver provides userspace access to the SPI + device functions via multiple chip selects. The device can be + a CPLD or FPGA depending on the functionality required and is + present in all Pensando SoC based designs. + config SPI_PIC32 tristate "Microchip PIC32 series SPI" depends on MACH_PIC32 || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index be9ba40ef8d0..71e0a95c6d88 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o obj-$(CONFIG_SPI_ORION) += spi-orion.o +obj-$(CONFIG_SPI_PENSANDO_SR) += spi-pensando-sr.o obj-$(CONFIG_SPI_PCI1XXXX) += spi-pci1xxxx.o obj-$(CONFIG_SPI_PIC32) += spi-pic32.o obj-$(CONFIG_SPI_PIC32_SQI) += spi-pic32-sqi.o diff --git a/drivers/spi/spi-pensando-sr.c b/drivers/spi/spi-pensando-sr.c new file mode 100644 index 000000000000..91c64bcfba04 --- /dev/null +++ b/drivers/spi/spi-pensando-sr.c @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Pensando SoC System Resource Driver + * + * Userspace interface and reset driver support for SPI + * connected Pensando SoC System Resource Chip. This + * device is present in all Pensando SoC based designs. + * This file is derived in part from spi/spidev.c. + * + * Copyright (C) 2006 SWAPP + * Andrea Paterniani + * Copyright (C) 2007 David Brownell (simplification, cleanup) + * Copyright 2023 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PENSR_MAX_REG 0xff +#define PENSR_CTRL0_REG 0x10 +#define PENSR_SPI_CMD_REGRD 0x0b +#define PENSR_SPI_CMD_REGWR 0x02 +#define SPI_IOC_MAGIC 'k' + +#define SPI_MSGSIZE(N) \ + ((((N)*(sizeof(struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \ + ? ((N)*(sizeof(struct spi_ioc_transfer))) : 0) +#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)]) + +struct spi_ioc_transfer { + __u64 tx_buf; + __u64 rx_buf; + __u32 len; + __u32 speed_hz; + __u16 delay_usecs; + __u8 bits_per_word; + __u8 cs_change; + __u8 tx_nbits; + __u8 rx_nbits; + __u8 word_delay_usecs; + __u8 pad; +}; + +struct pensr_device { + struct spi_device *spi_dev; + struct reset_controller_dev rcdev; + struct mutex buf_lock; + spinlock_t spi_lock; + u8 *tx_buffer; + u8 *rx_buffer; +}; + +static dev_t pensr_devt; +static struct pensr_device *pensr; +static struct class *pensr_class; +static unsigned int bufsiz = 4096; + +static struct spi_ioc_transfer * +pensr_spi_get_ioc_message(unsigned int cmd, + struct spi_ioc_transfer __user *u_ioc, + unsigned int *n_ioc) +{ + u32 tmp; + + /* Check type, command number and direction */ + if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC + || _IOC_NR(cmd) != _IOC_NR(SPI_IOC_MESSAGE(0)) + || _IOC_DIR(cmd) != _IOC_WRITE) + return ERR_PTR(-ENOTTY); + + tmp = _IOC_SIZE(cmd); + if ((tmp % sizeof(struct spi_ioc_transfer)) != 0) + return ERR_PTR(-EINVAL); + *n_ioc = tmp / sizeof(struct spi_ioc_transfer); + if (*n_ioc == 0) + return NULL; + + /* copy into scratch area */ + return memdup_user(u_ioc, tmp); +} + +static long +pensr_spi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + struct spi_transfer t[2] = { 0 }; + struct spi_ioc_transfer *u_xfers; + struct spi_ioc_transfer *u_xfer; + struct pensr_device *pensr; + struct spi_device *spi_dev; + unsigned int n_xfers; + struct spi_message m; + u8 *tx_buf; + u8 *rx_buf; + int ret; + + /* Check type and command number */ + if (_IOC_TYPE(cmd) != SPI_IOC_MAGIC) + return -ENOTTY; + + pensr = filp->private_data; + if (!pensr) + return -ESHUTDOWN; + + tx_buf = pensr->tx_buffer; + rx_buf = pensr->rx_buffer; + + spin_lock_irq(&pensr->spi_lock); + spi_dev = spi_dev_get(pensr->spi_dev); + spin_unlock_irq(&pensr->spi_lock); + if (spi_dev == NULL) + return -ESHUTDOWN; + + /* Use the buffer lock here for triple duty: + * - prevent I/O (from us) so calling spi_setup() is safe; + * - prevent concurrent SPI_IOC_WR_* from morphing + * data fields while SPI_IOC_RD_* reads them; + * - SPI_IOC_MESSAGE needs the buffer locked "normally". + */ + mutex_lock(&pensr->buf_lock); + + u_xfers = pensr_spi_get_ioc_message(cmd, + (struct spi_ioc_transfer __user *)arg, &n_xfers); + if (IS_ERR(u_xfers)) { + ret = PTR_ERR(u_xfers); + goto done; + } + if (!u_xfers) + goto done; + u_xfer = u_xfers; + + t[0].tx_buf = tx_buf; + t[0].len = u_xfer->len; + if (copy_from_user(tx_buf, (const u8 __user *) (uintptr_t) u_xfer->tx_buf, u_xfer->len)) { + ret = -EFAULT; + goto done; + } + + if (n_xfers > 1) { + u_xfer++; + t[1].rx_buf = rx_buf; + t[1].len = u_xfer->len; + } + + spi_message_init_with_transfers(&m, t, n_xfers); + ret = spi_sync(spi_dev, &m); + if (ret < 0) + goto done; + + if (n_xfers > 1) { + if (copy_to_user((u8 __user *)(uintptr_t)u_xfer->rx_buf, rx_buf, u_xfer->len)) { + ret = -EFAULT; + goto done; + } + } + +done: + mutex_unlock(&pensr->buf_lock); + spi_dev_put(spi_dev); + return ret; +} + +static int pensr_spi_open(struct inode *inode, struct file *filp) +{ + struct spi_device *spi_dev; + int status = -ENXIO; + u8 current_cs; + + if (!pensr) + return -ENODEV; + + filp->private_data = pensr; + current_cs = iminor(inode); + spi_dev = pensr->spi_dev; + spi_dev->chip_select = current_cs; + spi_dev->cs_gpiod = spi_dev->controller->cs_gpiods[current_cs]; + spi_setup(spi_dev); + + if (!pensr->tx_buffer) { + pensr->tx_buffer = kmalloc(bufsiz, GFP_KERNEL); + memset(pensr->tx_buffer, 0, bufsiz); + if (!pensr->tx_buffer) { + status = -ENOMEM; + goto err_alloc_tx_buf; + } + } + if (!pensr->rx_buffer) { + pensr->rx_buffer = kmalloc(bufsiz, GFP_KERNEL); + memset(pensr->rx_buffer, 0, bufsiz); + if (!pensr->rx_buffer) { + status = -ENOMEM; + goto err_alloc_rx_buf; + } + } + stream_open(inode, filp); + return 0; + +err_alloc_rx_buf: + kfree(pensr->tx_buffer); + pensr->tx_buffer = NULL; +err_alloc_tx_buf: + return status; +} + +static int pensr_spi_release(struct inode *inode, struct file *filp) +{ + filp->private_data = NULL; + return 0; +} + +static const struct file_operations pensr_spi_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = pensr_spi_ioctl, + .open = pensr_spi_open, + .release = pensr_spi_release, + .llseek = no_llseek, +}; + +static int pensr_regs_read(struct pensr_device *pensr, u32 reg, u32 *val) +{ + struct spi_device *spi_dev = pensr->spi_dev; + struct spi_transfer t[2] = { 0 }; + struct spi_message m; + u8 txbuf[3]; + u8 rxbuf[1]; + int ret; + + txbuf[0] = PENSR_SPI_CMD_REGRD; + txbuf[1] = reg; + txbuf[2] = 0x0; + t[0].tx_buf = (u8 *)txbuf; + t[0].len = 3; + + rxbuf[0] = 0x0; + t[1].rx_buf = rxbuf; + t[1].len = 1; + + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret = spi_sync(spi_dev, &m); + if (ret == 0) { + /* 3 Tx + 1 Rx = 4 */ + *val = rxbuf[0]; + } + return ret; +} + +static int pensr_regs_write(struct pensr_device *pensr, u32 reg, u32 val) +{ + struct spi_device *spi_dev = pensr->spi_dev; + struct spi_transfer t[1] = { 0 }; + struct spi_message m; + u8 txbuf[4]; + int ret; + + spi_dev->chip_select = 0; + spi_dev->cs_gpiod = spi_dev->controller->cs_gpiods[0]; + spi_setup(spi_dev); + + txbuf[0] = PENSR_SPI_CMD_REGWR; + txbuf[1] = reg; + txbuf[2] = val; + txbuf[3] = 0; + + t[0].tx_buf = txbuf; + t[0].len = 4; + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret = spi_sync(spi_dev, &m); + return ret; +} + +static int pensr_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct pensr_device *pensr = + container_of(rcdev, struct pensr_device, rcdev); + struct spi_device *spi_dev = pensr->spi_dev; + unsigned int val; + int ret; + + spin_lock_irq(&pensr->spi_lock); + spi_dev->chip_select = 0; + spi_dev->cs_gpiod = spi_dev->controller->cs_gpiods[spi_dev->chip_select]; + spi_setup(spi_dev); + + ret = pensr_regs_read(pensr, PENSR_CTRL0_REG, &val); + if (ret) { + dev_err(&spi_dev->dev, "error reading ctrl0 reg\n"); + goto done; + } + + val |= BIT(6); + ret = pensr_regs_write(pensr, PENSR_CTRL0_REG, val); + if (ret) + dev_err(&spi_dev->dev, "error writing ctrl0 reg\n"); + +done: + spin_unlock_irq(&pensr->spi_lock); + return ret; +} + +static int pensr_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct pensr_device *pensr = + container_of(rcdev, struct pensr_device, rcdev); + struct spi_device *spi_dev = pensr->spi_dev; + unsigned int val; + int ret; + + spin_lock_irq(&pensr->spi_lock); + spi_dev->chip_select = 0; + spi_dev->cs_gpiod = spi_dev->controller->cs_gpiods[spi_dev->chip_select]; + spi_setup(spi_dev); + + ret = pensr_regs_read(pensr, PENSR_CTRL0_REG, &val); + if (ret) { + dev_err(&spi_dev->dev, "error reading ctrl0 reg\n"); + goto done; + } + + val &= ~BIT(6); + ret = pensr_regs_write(pensr, PENSR_CTRL0_REG, val); + if (ret) + dev_err(&spi_dev->dev, "error writing ctrl0 reg\n"); + +done: + spin_unlock_irq(&pensr->spi_lock); + return ret; +} + +static const struct reset_control_ops pensr_reset_ops = { + .assert = pensr_reset_assert, + .deassert = pensr_reset_deassert, +}; + +static int pensr_spi_probe(struct spi_device *spi_dev) +{ + struct device_node *np; + struct property *prop; + struct device *dev; + struct cdev *cdev; + const __be32 *p; + int status; + u32 num_cs; + u32 cs; + + np = spi_dev->dev.parent->of_node; + status = of_property_read_u32(np, "num-cs", &num_cs); + if (status) + return dev_err_probe(&spi_dev->dev, status, + "number of chip-selects not defined"); + + status = alloc_chrdev_region(&pensr_devt, 0, num_cs, "pensr"); + if (status) + return dev_err_probe(&spi_dev->dev, status, + "failed to alloc chrdev region\n"); + + pensr_class = class_create(THIS_MODULE, "pensr"); + if (IS_ERR(pensr_class)) { + unregister_chrdev(MAJOR(pensr_devt), "pensr"); + return dev_err_probe(&spi_dev->dev, PTR_ERR(pensr_class), + "failed to create class\n"); + } + + cdev = cdev_alloc(); + if (!cdev) { + dev_err(&spi_dev->dev, "allocation of cdev failed"); + status = -ENOMEM; + goto cdev_failed; + } + cdev->owner = THIS_MODULE; + cdev_init(cdev, &pensr_spi_fops); + + status = cdev_add(cdev, pensr_devt, num_cs); + if (status) { + dev_err(&spi_dev->dev, "register of cdev failed"); + goto cdev_delete; + } + + /* Allocate driver data */ + pensr = kzalloc(sizeof(*pensr), GFP_KERNEL); + if (!pensr) { + status = -ENOMEM; + dev_err(&spi_dev->dev, "allocate driver data failed"); + goto cdev_delete; + } + + pensr->spi_dev = spi_dev; + spin_lock_init(&pensr->spi_lock); + mutex_init(&pensr->buf_lock); + + /* Create a device for each chip select */ + np = spi_dev->dev.of_node; + of_property_for_each_u32(np, "cs", prop, p, cs) { + dev = device_create(pensr_class, + &spi_dev->dev, + MKDEV(MAJOR(pensr_devt), cs), + pensr, + "pensr0.%d", + cs); + if (IS_ERR(dev)) { + status = IS_ERR(dev); + dev_err(&spi_dev->dev, "error creating device\n"); + goto cdev_delete; + } + dev_dbg(&spi_dev->dev, "created device major %u, minor %d\n", + MAJOR(pensr_devt), cs); + } + + spi_set_drvdata(spi_dev, pensr); + + /* Register emmc hardware reset */ + pensr->rcdev.nr_resets = 1; + pensr->rcdev.owner = THIS_MODULE; + pensr->rcdev.dev = &spi_dev->dev; + pensr->rcdev.ops = &pensr_reset_ops; + pensr->rcdev.of_node = spi_dev->dev.of_node; + status = reset_controller_register(&pensr->rcdev); + if (status) + return dev_err_probe(&spi_dev->dev, status, + "failed to register reset controller\n"); + return status; + +cdev_delete: + cdev_del(cdev); +cdev_failed: + device_destroy(pensr_class, pensr_devt); + return status; +} + +static const struct of_device_id pensr_dt_match[] = { + { .compatible = "amd,pensando-sr" }, + { /* sentinel */ } +}; + +static struct spi_driver pensr_spi_driver = { + .probe = pensr_spi_probe, + .driver = { + .name = "pensando-sr", + .of_match_table = pensr_dt_match, + }, +}; +builtin_driver(pensr_spi_driver, spi_register_driver)