From patchwork Sat Jan 21 02:07:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kechen Lu X-Patchwork-Id: 13110807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 471E8C25B4E for ; Sat, 21 Jan 2023 02:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229687AbjAUCIe (ORCPT ); Fri, 20 Jan 2023 21:08:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229379AbjAUCIc (ORCPT ); Fri, 20 Jan 2023 21:08:32 -0500 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2060c.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe5b::60c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73E5270C6B; Fri, 20 Jan 2023 18:08:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=l4BJb9DLk1O9H+P8pK9tVKGOkZqkU+uIZVmdd/0CAnmz37BpyTDoZ2vFPx0UaFbS5W9Xr/sEaf+cr/Mp5au1+REZQpDNvSUgivN0y6cGP9yH29RugHBwsOPIFT/K4bQ1eldRQzVRBpEqR+2EKmSGfcfe3TXi2BMjGZrQwiLyhXr93zP0G+g53WGb+l//A+8ETEXU/a0oBVDlRFW4vRPbZEFAc5AnBXrYRKUxLLY9mk0zFrZWFaziuvHqi1MluimlK1pVhUx4t1ZzGtBTs4mQ7VrqQz5JlqjEypx1jcIyhcN5MBmYhAB5mdy1Nb/4okQWOWPEUOjKJdRDayKdFjm/BA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0UtdJPgEJRLGg3MP6pZGLNmQi8vyiG7Nt3n6OLlsZHw=; b=KVGlzu9VKcJisYyKSYgKm63EV1ulLiC984qXHwoBj59tPo3zLliiYqDM7xEGDOSKBxwaXWgnieC1hJyzCz1HhnvxvYBgYcxjucO4784zG7fCDv0rPizAqxnBjT3a+HPwh94YZCMYjK7eIad6KspFZEm1ZR/JTakCXdXJJyv7B2qTqw/OacOrkMsbWmXT8LKArNBR8fbvfsdaxzV6khsdyUNRcqwOT0pvWZBQUy3PuxRY8u/cV1s0NvjsEJpTCawlTDq1prRkvX1e+O+WzREbm3zNEKwrAaEvXC1aAQsBhZhqLTrjgFotZlVt+AGfBTNEXOas0iRwh/slrEueISabkw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0UtdJPgEJRLGg3MP6pZGLNmQi8vyiG7Nt3n6OLlsZHw=; b=WBtKKBWuBsOZbVS3EcLbElOQVz9gu+StUIGSWaAwIVRlfSbQm0vinb/RY+GVo1T8IlCuUO1rKMXat4y5drGCLOjfcYATT6o6mFhfDjPqFLFSRGx4AIuSl2DDHyeRCe7yiJJotPJ+saTnhZc9jPdIFg+oKFuu65hIiDklU6F4yOlFhuPGsYGIBW0tQiU25EeoUFUkXHV2tuZN5rVEXyswImXsYNJzHYspeAl+OLJsmhY+W3ymcahriaYJIBp1RpfdXlixukq92SVAzX55WvxKafQML9z1dnoReYO8uPIi0O7IZNaOlbt36DiuDUGEhdcDDgRzSXgglbydwmihQe2ktA== Received: from DM6PR06CA0050.namprd06.prod.outlook.com (2603:10b6:5:54::27) by DM4PR12MB6134.namprd12.prod.outlook.com (2603:10b6:8:ad::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27; Sat, 21 Jan 2023 02:08:18 +0000 Received: from DM6NAM11FT071.eop-nam11.prod.protection.outlook.com (2603:10b6:5:54:cafe::71) by DM6PR06CA0050.outlook.office365.com (2603:10b6:5:54::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27 via Frontend Transport; Sat, 21 Jan 2023 02:08:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT071.mail.protection.outlook.com (10.13.173.48) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6023.16 via Frontend Transport; Sat, 21 Jan 2023 02:08:18 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:11 -0800 Received: from dvt1-1.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:10 -0800 From: Kechen Lu To: , , CC: , , , , , , Subject: [RFC PATCH v6 1/6] KVM: x86: only allow exits disable before vCPUs created Date: Sat, 21 Jan 2023 02:07:33 +0000 Message-ID: <20230121020738.2973-2-kechenl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230121020738.2973-1-kechenl@nvidia.com> References: <20230121020738.2973-1-kechenl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT071:EE_|DM4PR12MB6134:EE_ X-MS-Office365-Filtering-Correlation-Id: 04657633-ff94-4129-b63f-08dafb545d35 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Yz7meaWOs+2CszvNGBmb42ddWT5FTqpEN5ETV8BGkDsjKjL1urBekFnTez4cmlrdxYoD6UFXBL5iA0+ioj2arXoLjYj4JHVAWPFv74fZnl8C9gWQrMsNkL3VpaB3OHNaeWapb1WZIegrEM9fYgdu/RuH6j4kCn//xvaJUU0HS8dK/I8ZxRpEVZBIjhz0t3mgUp9Tm6F/ynJEmumi4okSSAwukkBBQgA4xw4rsi5pCfH9Iyd2OuEH4Sk053LIDV3yhLSsmZI0HNXBiDvMVhGzdZ7Zw9ybX3Btiv24+WUb3UMt0a8//4FoRbougs1ogkSBEU1xTHoqdjnQ+7Vi/FXyD2J0kuHqYmBbp+BD12mDOp3R0mKv/vJ1LBT/uGrlEzm6UGjrSY0aYacj5CwXNAFFGW9GyPJPkhJXQNt/ptEhyt2TeGq8WPJT32XuZuoeI/J0/tRywsv9VGqPHkR8qyUPBYo/A5shcBfs+vVnxIWE2TuiZ5AQn2HixOIuOuhdf4j1pGmaO2Q4A+7tjwQzS+3aAga5pAirh2QCDmVk2LE0d0aEnSTcGXVFsV1O/OSfV+OyvPzDRlBqYPSpJqYgTP7RfBkZMQ4rEeG7KiTolE0XH0jlp31E5m8aIv8QNmFRGwKwVLFC9LeAE6uyqADokLipuX+QwKlOhrdsAe++Ay4bkj+D2Gq/ju7vdVaHZmTOghmo/ml+TQ3ijd0NHYD97ryBUg== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(376002)(346002)(396003)(451199015)(36840700001)(40470700004)(46966006)(5660300002)(8936002)(4326008)(8676002)(82310400005)(70206006)(70586007)(6666004)(83380400001)(478600001)(54906003)(26005)(2906002)(16526019)(186003)(110136005)(36756003)(7696005)(2616005)(316002)(41300700001)(40480700001)(82740400003)(36860700001)(40460700003)(86362001)(7636003)(1076003)(47076005)(336012)(356005)(426003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2023 02:08:18.4409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04657633-ff94-4129-b63f-08dafb545d35 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT071.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6134 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sean Christopherson Since VMX and SVM both would never update the control bits if exits are disable after vCPUs are created, only allow setting exits disable flag before vCPU creation. Fixes: 4d5422cea3b6 ("KVM: X86: Provide a capability to disable MWAIT intercepts") Signed-off-by: Sean Christopherson Signed-off-by: Kechen Lu Cc: stable@vger.kernel.org --- Documentation/virt/kvm/api.rst | 1 + arch/x86/kvm/x86.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 9807b05a1b57..fb0fcc566d5a 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -7087,6 +7087,7 @@ branch to guests' 0x200 interrupt vector. :Architectures: x86 :Parameters: args[0] defines which exits are disabled :Returns: 0 on success, -EINVAL when args[0] contains invalid exits + or if any vCPU has already been created Valid bits in args[0] are:: diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index da4bbd043a7b..c8ae9c4f9f08 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -6227,6 +6227,10 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) break; + mutex_lock(&kvm->lock); + if (kvm->created_vcpus) + goto disable_exits_unlock; + if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && kvm_can_mwait_in_guest()) kvm->arch.mwait_in_guest = true; @@ -6237,6 +6241,8 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) kvm->arch.cstate_in_guest = true; r = 0; +disable_exits_unlock: + mutex_unlock(&kvm->lock); break; case KVM_CAP_MSR_PLATFORM_INFO: kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; From patchwork Sat Jan 21 02:07:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kechen Lu X-Patchwork-Id: 13110809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80E61C05027 for ; Sat, 21 Jan 2023 02:08:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229726AbjAUCIh (ORCPT ); Fri, 20 Jan 2023 21:08:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229631AbjAUCIf (ORCPT ); Fri, 20 Jan 2023 21:08:35 -0500 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2049.outbound.protection.outlook.com [40.107.93.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25C717134F; Fri, 20 Jan 2023 18:08:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=cyUYSrW9m3oprNPpwmfDpBUo6lb+4jZwzv2NQ6zFOFzl2rEDEmai9WLlRB0ojyzrCJFWt0fYSnRkicOJqWHgfDBaJ7dhugxezUoO0bIdZTWn1Qr3RPA15edaRnMgtuHdyuZ7MFPZM19oWuw0ewBdDwYvzWnJnKVvmB7PnXRCqz6L1EPGDBg2EXUTYRPuDdiND/wWFYuxuh4r8PNQ6ft78x591okRbXA8R2HeDD10PNGHCkohA6lC9MVIuhRAnCadN0jmt6NBk05/72jsmDNcEdIejp919vPVsGo6yZjrZqw29RH1v0+BwWlk0TwilLjMBNmGrR2ZS/5RnRW4YMfo5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rJ0CKwDChH5AHz+JZG2Szq40T8AbPlyEL7EQWIZ9Cvo=; b=jwThn1Z+IwT5BEm7DnMgK1qoT7UDW9quM+qjyrfpwP/fX75ZGIj5sO0JG6fmfIWgfXBl8aTbv4uTMRdOFlxeuM1zBqaJfkK+uOd5JHdDBydUFMlvvPBTpds5xCJPRNyEq8Przj2M/8GXL0+qF+jbeVv8BjMdUTnKw6SXCjwruO4AN7PH73XTrMz6k8uCa1gv99EeGBNxfpMtc7/uwbimG8iVNFjSND01lnwcK82inxeZvIxAhMw6a12ygnZxpRmHeZXWlbmQD8Z7je7jjLOrOta1bjq5qBmUsf2pIL+tiqfkGluQ36L9EwoZWKgNCkeDG1Bq0qSDlwuZiY6faQqSIA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rJ0CKwDChH5AHz+JZG2Szq40T8AbPlyEL7EQWIZ9Cvo=; b=dj6yCnNTYoLhZmXG7wgNXJ7mdSQCEj1AHvyyrC1QhuTasp2hJQKagjKBNM1NXj6C7aXfcgSvv1cEH71c4CxN//gsGX3NIhA4OWkSCgW4T7bOeNvEjXcrtpTKKIDftwrCNcqeVV4H8TzvREwsjt7ZIzt6iBZXnuRFs8rDG3ToTRhU1ESEFn6A4NhjpdEMI92/rbVI6e1Kjw2F172mavKSB/D7GnWlIXk3KnnQ+hMeij/drt7TnT8SVi0dBQF+SQVT26q9yfktVdT7JX3JVsztSOqQ9yGYJKnW6nzH+WZS5aTF81Vv5i4jr9faBVLhPfrGuIZoCg+osca5V9nbxPNc9Q== Received: from BN9P222CA0016.NAMP222.PROD.OUTLOOK.COM (2603:10b6:408:10c::21) by MW3PR12MB4410.namprd12.prod.outlook.com (2603:10b6:303:5b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27; Sat, 21 Jan 2023 02:08:22 +0000 Received: from BN8NAM11FT069.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10c:cafe::13) by BN9P222CA0016.outlook.office365.com (2603:10b6:408:10c::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27 via Frontend Transport; Sat, 21 Jan 2023 02:08:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT069.mail.protection.outlook.com (10.13.176.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6023.16 via Frontend Transport; Sat, 21 Jan 2023 02:08:21 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:13 -0800 Received: from dvt1-1.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:13 -0800 From: Kechen Lu To: , , CC: , , , , , Subject: [RFC PATCH v6 2/6] KVM: x86: Move *_in_guest power management flags to vCPU scope Date: Sat, 21 Jan 2023 02:07:34 +0000 Message-ID: <20230121020738.2973-3-kechenl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230121020738.2973-1-kechenl@nvidia.com> References: <20230121020738.2973-1-kechenl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT069:EE_|MW3PR12MB4410:EE_ X-MS-Office365-Filtering-Correlation-Id: 501bed2d-4aee-498a-5934-08dafb545f54 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lqHPsHJjNjkViRA4xeXSeUXAD5U0CNR4KKRyFXEejD4dmBO2hb8cSoV6DB6/gh7Sq4qIJADK11nmiGXZP8uIJ04hXsFlY43O34SRPQZN10TA+8LBFVURvRpsoplue2VG5S+QrF+uSBNiICggpvx9Tfgur6CalDHVM1wbMF9/Z1zH3PjV/P5TslYzE7kRnQYZpXpwTVXiClkIT3f4nrGV3wBs551kqA2A4dzY9pmMC9A0swZL4fSzcKe/of6cs4PHapSd3tNLFK/LIqWppeAkXu9AKgnLa8N7eQU/Qicvp13jNilPubNjPtay1baw7xqd8ijHI4hq7kOQQmKxJCqKQ5jnhYzHhCsKu7cC/uKKRz5rnNfZMbx3jotw5f4CtmEKCrpbhmApmMbukb9L/YfBVKY7GYhGcreAJv/wow0k6ajDNL76JWc447TvmxCCTXPNn1Ue/6yuncI92s/VaEXniQyEW4FMS/cfOh6ooOY5JZR+6fkjutLGM+PR7gm4IVz9NA8FiB/W0OgJia8nArbzKO/vGRcRL/yEQZ6fqK1CACpshGYfWFwxrFCJH0C2TMCe2CeijJr1n4niT8wZ8KEOIlQ1RxUr4Do5ktKGnATt36RWiNr2yXE8v/SYuxYv1XkjMgvyu9jmjYmOeVorXXsbxhwsfolcTsHOOOPdzgkwbnv7wPE0THSVTAn2pGwfINo3gmijYA6ANftzkd+7MRhJnw== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(136003)(376002)(346002)(451199015)(46966006)(40470700004)(36840700001)(110136005)(2906002)(26005)(54906003)(186003)(16526019)(2616005)(316002)(7696005)(478600001)(6666004)(36756003)(36860700001)(86362001)(356005)(7636003)(47076005)(82740400003)(40480700001)(1076003)(426003)(40460700003)(336012)(83380400001)(41300700001)(4326008)(5660300002)(30864003)(8936002)(70586007)(70206006)(82310400005)(8676002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2023 02:08:21.9347 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 501bed2d-4aee-498a-5934-08dafb545f54 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT069.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4410 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Make the runtime disabled mwait/hlt/pause/cstate exits flags vCPU scope to allow finer-grained, per-vCPU control. The VM-scoped control is only allowed before vCPUs are created, thus preserving the existing behavior is a simple matter of snapshotting the flags at vCPU creation. Signed-off-by: Kechen Lu Suggested-by: Sean Christopherson Reviewed-by: Sean Christopherson --- arch/x86/include/asm/kvm_host.h | 5 +++++ arch/x86/kvm/cpuid.c | 4 ++-- arch/x86/kvm/lapic.c | 7 +++---- arch/x86/kvm/svm/nested.c | 4 ++-- arch/x86/kvm/svm/svm.c | 12 ++++++------ arch/x86/kvm/vmx/vmx.c | 16 ++++++++-------- arch/x86/kvm/x86.c | 6 +++++- arch/x86/kvm/x86.h | 16 ++++++++-------- 8 files changed, 39 insertions(+), 31 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 6aaae18f1854..41b998234a04 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1009,6 +1009,11 @@ struct kvm_vcpu_arch { #if IS_ENABLED(CONFIG_HYPERV) hpa_t hv_root_tdp; #endif + + bool mwait_in_guest; + bool hlt_in_guest; + bool pause_in_guest; + bool cstate_in_guest; }; struct kvm_lpage_info { diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 596061c1610e..20e427dc608c 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -283,8 +283,8 @@ static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_e best->ebx = xstate_required_size(vcpu->arch.xcr0, true); best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent); - if (kvm_hlt_in_guest(vcpu->kvm) && best && - (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) + if (kvm_hlt_in_guest(vcpu) && + best && (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 4efdb4a4d72c..f0f49d0c6e69 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -151,14 +151,13 @@ static inline u32 kvm_x2apic_id(struct kvm_lapic *apic) static bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu) { return pi_inject_timer && kvm_vcpu_apicv_active(vcpu) && - (kvm_mwait_in_guest(vcpu->kvm) || kvm_hlt_in_guest(vcpu->kvm)); + (kvm_mwait_in_guest(vcpu) || kvm_hlt_in_guest(vcpu)); } bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu) { - return kvm_x86_ops.set_hv_timer - && !(kvm_mwait_in_guest(vcpu->kvm) || - kvm_can_post_timer_interrupt(vcpu)); + return kvm_x86_ops.set_hv_timer && + !(kvm_mwait_in_guest(vcpu) || kvm_can_post_timer_interrupt(vcpu)); } static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index add65dd59756..ed26b6de3007 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -721,7 +721,7 @@ static void nested_vmcb02_prepare_control(struct vcpu_svm *svm, pause_count12 = svm->pause_filter_enabled ? svm->nested.ctl.pause_filter_count : 0; pause_thresh12 = svm->pause_threshold_enabled ? svm->nested.ctl.pause_filter_thresh : 0; - if (kvm_pause_in_guest(svm->vcpu.kvm)) { + if (kvm_pause_in_guest(&svm->vcpu)) { /* use guest values since host doesn't intercept PAUSE */ vmcb02->control.pause_filter_count = pause_count12; vmcb02->control.pause_filter_thresh = pause_thresh12; @@ -1012,7 +1012,7 @@ int nested_svm_vmexit(struct vcpu_svm *svm) vmcb12->control.event_inj = svm->nested.ctl.event_inj; vmcb12->control.event_inj_err = svm->nested.ctl.event_inj_err; - if (!kvm_pause_in_guest(vcpu->kvm)) { + if (!kvm_pause_in_guest(vcpu)) { vmcb01->control.pause_filter_count = vmcb02->control.pause_filter_count; vmcb_mark_dirty(vmcb01, VMCB_INTERCEPTS); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 9a194aa1a75a..dc7176605e01 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1014,7 +1014,7 @@ static void grow_ple_window(struct kvm_vcpu *vcpu) struct vmcb_control_area *control = &svm->vmcb->control; int old = control->pause_filter_count; - if (kvm_pause_in_guest(vcpu->kvm)) + if (kvm_pause_in_guest(vcpu)) return; control->pause_filter_count = __grow_ple_window(old, @@ -1035,7 +1035,7 @@ static void shrink_ple_window(struct kvm_vcpu *vcpu) struct vmcb_control_area *control = &svm->vmcb->control; int old = control->pause_filter_count; - if (kvm_pause_in_guest(vcpu->kvm)) + if (kvm_pause_in_guest(vcpu)) return; control->pause_filter_count = @@ -1229,12 +1229,12 @@ static void init_vmcb(struct kvm_vcpu *vcpu) svm_set_intercept(svm, INTERCEPT_RDPRU); svm_set_intercept(svm, INTERCEPT_RSM); - if (!kvm_mwait_in_guest(vcpu->kvm)) { + if (!kvm_mwait_in_guest(vcpu)) { svm_set_intercept(svm, INTERCEPT_MONITOR); svm_set_intercept(svm, INTERCEPT_MWAIT); } - if (!kvm_hlt_in_guest(vcpu->kvm)) + if (!kvm_hlt_in_guest(vcpu)) svm_set_intercept(svm, INTERCEPT_HLT); control->iopm_base_pa = __sme_set(iopm_base); @@ -1278,7 +1278,7 @@ static void init_vmcb(struct kvm_vcpu *vcpu) svm->nested.vmcb12_gpa = INVALID_GPA; svm->nested.last_vmcb12_gpa = INVALID_GPA; - if (!kvm_pause_in_guest(vcpu->kvm)) { + if (!kvm_pause_in_guest(vcpu)) { control->pause_filter_count = pause_filter_count; if (pause_filter_thresh) control->pause_filter_thresh = pause_filter_thresh; @@ -4362,7 +4362,7 @@ static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu) static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu) { - if (!kvm_pause_in_guest(vcpu->kvm)) + if (!kvm_pause_in_guest(vcpu)) shrink_ple_window(vcpu); } diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index fc9008dbed33..019a20029878 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1689,7 +1689,7 @@ static void vmx_clear_hlt(struct kvm_vcpu *vcpu) * then the instruction is already executing and RIP has already been * advanced. */ - if (kvm_hlt_in_guest(vcpu->kvm) && + if (kvm_hlt_in_guest(vcpu) && vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); } @@ -4412,10 +4412,10 @@ static u32 vmx_exec_control(struct vcpu_vmx *vmx) exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING | CPU_BASED_INVLPG_EXITING); - if (kvm_mwait_in_guest(vmx->vcpu.kvm)) + if (kvm_mwait_in_guest(&vmx->vcpu)) exec_control &= ~(CPU_BASED_MWAIT_EXITING | CPU_BASED_MONITOR_EXITING); - if (kvm_hlt_in_guest(vmx->vcpu.kvm)) + if (kvm_hlt_in_guest(&vmx->vcpu)) exec_control &= ~CPU_BASED_HLT_EXITING; return exec_control; } @@ -4515,7 +4515,7 @@ static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx) } if (!enable_unrestricted_guest) exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; - if (kvm_pause_in_guest(vmx->vcpu.kvm)) + if (kvm_pause_in_guest(&vmx->vcpu)) exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; if (!kvm_vcpu_apicv_active(vcpu)) exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | @@ -4661,7 +4661,7 @@ static void init_vmcs(struct vcpu_vmx *vmx) vmcs_write16(LAST_PID_POINTER_INDEX, kvm->arch.max_vcpu_ids - 1); } - if (!kvm_pause_in_guest(kvm)) { + if (!kvm_pause_in_guest(&vmx->vcpu)) { vmcs_write32(PLE_GAP, ple_gap); vmx->ple_window = ple_window; vmx->ple_window_dirty = true; @@ -5833,7 +5833,7 @@ static void shrink_ple_window(struct kvm_vcpu *vcpu) */ static int handle_pause(struct kvm_vcpu *vcpu) { - if (!kvm_pause_in_guest(vcpu->kvm)) + if (!kvm_pause_in_guest(vcpu)) grow_ple_window(vcpu); /* @@ -7379,7 +7379,7 @@ static int vmx_vcpu_create(struct kvm_vcpu *vcpu) vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); vmx_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); - if (kvm_cstate_in_guest(vcpu->kvm)) { + if (kvm_cstate_in_guest(vcpu)) { vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R); vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); @@ -7935,7 +7935,7 @@ static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) { - if (!kvm_pause_in_guest(vcpu->kvm)) + if (!kvm_pause_in_guest(vcpu)) shrink_ple_window(vcpu); } diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c8ae9c4f9f08..9a77b55142c6 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11634,6 +11634,10 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) #if IS_ENABLED(CONFIG_HYPERV) vcpu->arch.hv_root_tdp = INVALID_PAGE; #endif + vcpu->arch.mwait_in_guest = vcpu->kvm->arch.mwait_in_guest; + vcpu->arch.hlt_in_guest = vcpu->kvm->arch.hlt_in_guest; + vcpu->arch.pause_in_guest = vcpu->kvm->arch.pause_in_guest; + vcpu->arch.cstate_in_guest = vcpu->kvm->arch.cstate_in_guest; r = static_call(kvm_x86_vcpu_create)(vcpu); if (r) @@ -12885,7 +12889,7 @@ bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) kvm_is_exception_pending(vcpu))) return false; - if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) + if (kvm_hlt_in_guest(vcpu) && !kvm_can_deliver_async_pf(vcpu)) return false; /* diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 9de72586f406..b8e49a9d353d 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -351,24 +351,24 @@ static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec) __rem; \ }) -static inline bool kvm_mwait_in_guest(struct kvm *kvm) +static inline bool kvm_mwait_in_guest(struct kvm_vcpu *vcpu) { - return kvm->arch.mwait_in_guest; + return vcpu->arch.mwait_in_guest; } -static inline bool kvm_hlt_in_guest(struct kvm *kvm) +static inline bool kvm_hlt_in_guest(struct kvm_vcpu *vcpu) { - return kvm->arch.hlt_in_guest; + return vcpu->arch.hlt_in_guest; } -static inline bool kvm_pause_in_guest(struct kvm *kvm) +static inline bool kvm_pause_in_guest(struct kvm_vcpu *vcpu) { - return kvm->arch.pause_in_guest; + return vcpu->arch.pause_in_guest; } -static inline bool kvm_cstate_in_guest(struct kvm *kvm) +static inline bool kvm_cstate_in_guest(struct kvm_vcpu *vcpu) { - return kvm->arch.cstate_in_guest; + return vcpu->arch.cstate_in_guest; } static inline bool kvm_notify_vmexit_enabled(struct kvm *kvm) From patchwork Sat Jan 21 02:07:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kechen Lu X-Patchwork-Id: 13110810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69BEDC05027 for ; Sat, 21 Jan 2023 02:08:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229773AbjAUCIr (ORCPT ); Fri, 20 Jan 2023 21:08:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229742AbjAUCIl (ORCPT ); Fri, 20 Jan 2023 21:08:41 -0500 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 720247134A; Fri, 20 Jan 2023 18:08:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=K53lbHyN7jF4zRBRXxgDyosQOrwysNKHDtG/H7xkY4MJKpiz5CrZPhXR/DFm2hxPDSrskdiT6eBHv4VRcz2spJrUpxYHg1GEZg1YN7Jk1QZMdpDYXO0tqUfk9mAX4Y6GfT2ffXZLNhPWe7du06HGUMpBEgk88EgIYNcpillov4gfHid4JijiAwEVOzAP3DuyQknR4nf1hlfbmCx9mSWreQ9PnmIz5x2d7xyoR2gJQB20tM2j1PaLxMppQjzpctraTxrgs7O6zyo7m26SvwCrG6vm/QCDQXbtJ1p6v7bfjWhq4fxLUpPZ1hOrtsGDpn/BzA6sjszXCedSJFZjHUpO7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=g34zLAdFZOgBMoMDZabEdu1+HOcuYlb+wiyGw6xI8bI=; b=ZFawlHv0pYd4e5TK3IwIzpITAGRFEj068jcdHzrunKhjKc6N3s6AgGxYX1diJmVbGtT61EoWTDXgh47NAPUrcrMsAghERUnTKwnd2m+e45555wA+9YRbmQhGEFOORJ/Wubr6BWI3H03KIQA14a2OTVcTtZS2CB6XOe7f8Tbl8onKtBPDk0Ok73K6tLEQ5Fzzoz7fnt+OnwIa8XqiOm8IVwuCHe890ojhMdhMP+7CXQmdjd+B5m1/biV7hFwuDLBW2+u/sJmcLV4UfrYoq7HUmKVg1ebOHl35Qdui4Ww31qpYXOOa6yT/nQUczp2GTA8ZLLVDTWHRNHzBEj0cKKv3wA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=g34zLAdFZOgBMoMDZabEdu1+HOcuYlb+wiyGw6xI8bI=; b=cLRHh+q48Ah6aqgiozFd1lR2/8OC5sdKZLR8kEgx8fGus9IK5YTsXp5GcPm1hRq/b+B2HuR065PxrOENFwTM+pvSWcAj9r9dXUrTlDd30omMXUHOcS/CcRfmt8EYF9dpVBzLhCdcWzFXkoicVKGJpqul1wNwianpObU95DzhUybISiObRMSbAfJLWrCcakLTIvA5yqVc45B0WTVVWDQq6LKHI0qW1xjhJGxA8oA2yy2gIWQwokbXcUylyIqAMNPLb0DzsGBCLmimhi4N0SZpdK7mQzriai3WqutM7iMT0iqOwhh6I+i7bhSWLZzkGLPurHxNLrS4V2B5uZyjetymvA== Received: from DM6PR03CA0093.namprd03.prod.outlook.com (2603:10b6:5:333::26) by BL0PR12MB4995.namprd12.prod.outlook.com (2603:10b6:208:1c7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.28; Sat, 21 Jan 2023 02:08:24 +0000 Received: from DM6NAM11FT109.eop-nam11.prod.protection.outlook.com (2603:10b6:5:333:cafe::27) by DM6PR03CA0093.outlook.office365.com (2603:10b6:5:333::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27 via Frontend Transport; Sat, 21 Jan 2023 02:08:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT109.mail.protection.outlook.com (10.13.173.178) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6023.16 via Frontend Transport; Sat, 21 Jan 2023 02:08:24 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:16 -0800 Received: from dvt1-1.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:16 -0800 From: Kechen Lu To: , , CC: , , , , , Subject: [RFC PATCH v6 3/6] KVM: x86: Reject disabling of MWAIT interception when not allowed Date: Sat, 21 Jan 2023 02:07:35 +0000 Message-ID: <20230121020738.2973-4-kechenl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230121020738.2973-1-kechenl@nvidia.com> References: <20230121020738.2973-1-kechenl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT109:EE_|BL0PR12MB4995:EE_ X-MS-Office365-Filtering-Correlation-Id: 99f28a90-5f0d-40e5-1fd5-08dafb5460bf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 018X+hba/Xc91E9lDshUWbZ/fcjy9un10vN4NKDFrrNTX91QRI32sv36Yk4zSJUpJEptMYOPMFHtEDsni6egDi6V4bscs0FwhmF28HNjYFxD1tS/6ZgQZAKuj6lrRT7jP/Uw9oTvug5sOj7CB9y13R4HjlNO9X9oQn9EFNUAS+cAnbjDvpK6auzi/LFaTLJTCRKCEuZe1kkJFNoC9sv9o6QglFE3aWA8blvEF4cxmgwImoMnAUldl2r8cRRuyPbisDW3Ali0EADnkzvJJV2dF/cBqzFAtbMrkdPv54gzA8YpVVSHtTEvBozOYgACXBNsJwjxfst0d9xBRtbeYJyvN2iKY8ZcOwHxkzwj9Zrt7ttSTQTzBNr7iXTQYR3dbEBhUiNpzMmcyBO/OdSPpowD/Zwh/OabDkOCahPdlgjysmvKJzTWkC9QvNuxw7N0CqPfkwgoICN5sMLb04goCqBXsvM/2iuffSH7qmlo2RDBfGCv1nGeo/uEc9bJVs3DbgrDqlUiGWnb9AljM10XLisMiazPrpm5yx0zs5Ax2OD1NFyZRVHmQl0NewPH+Gcs1p68OFcARYiBO1fUtbQJ3nv/B2KEE3TCPXeECwJVgAhXi5igXbzxc08EbINdEjDtWSduKdo3SjhPTprvNbkqNt/0A0Dvf+eF+xta7lH+TanIhxLBtaWd4X7zs62Xf6hTSun66QM8cr4yriK8+/dnjt+LIA== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(346002)(136003)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(2616005)(6666004)(7696005)(426003)(70206006)(70586007)(8676002)(4326008)(47076005)(26005)(478600001)(16526019)(186003)(8936002)(5660300002)(2906002)(36860700001)(7636003)(41300700001)(83380400001)(82740400003)(82310400005)(40480700001)(86362001)(356005)(1076003)(110136005)(54906003)(316002)(336012)(40460700003)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2023 02:08:24.3746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 99f28a90-5f0d-40e5-1fd5-08dafb5460bf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4995 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sean Christopherson Reject KVM_CAP_X86_DISABLE_EXITS if userspace attempts to disable MWAIT exits and KVM previously reported (via KVM_CHECK_EXTENSION) that MWAIT is not allowed in guest, e.g. because it's not supported or the CPU doesn't have an aways-running APIC timer. Fixes: 4d5422cea3b6 ("KVM: X86: Provide a capability to disable MWAIT intercepts") Signed-off-by: Sean Christopherson Signed-off-by: Kechen Lu --- arch/x86/kvm/x86.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 9a77b55142c6..60caa3fd40e5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4326,6 +4326,16 @@ static inline bool kvm_can_mwait_in_guest(void) boot_cpu_has(X86_FEATURE_ARAT); } +static u64 kvm_get_allowed_disable_exits(void) +{ + u64 r = KVM_X86_DISABLE_VALID_EXITS; + + if (!kvm_can_mwait_in_guest()) + r &= ~KVM_X86_DISABLE_EXITS_MWAIT; + + return r; +} + static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid2 __user *cpuid_arg) { @@ -4448,10 +4458,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) r = KVM_CLOCK_VALID_FLAGS; break; case KVM_CAP_X86_DISABLE_EXITS: - r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | - KVM_X86_DISABLE_EXITS_CSTATE; - if(kvm_can_mwait_in_guest()) - r |= KVM_X86_DISABLE_EXITS_MWAIT; + r |= kvm_get_allowed_disable_exits(); break; case KVM_CAP_X86_SMM: if (!IS_ENABLED(CONFIG_KVM_SMM)) @@ -6224,15 +6231,14 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, break; case KVM_CAP_X86_DISABLE_EXITS: r = -EINVAL; - if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) + if (cap->args[0] & ~kvm_get_allowed_disable_exits()) break; mutex_lock(&kvm->lock); if (kvm->created_vcpus) goto disable_exits_unlock; - if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && - kvm_can_mwait_in_guest()) + if (cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) kvm->arch.mwait_in_guest = true; if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) kvm->arch.hlt_in_guest = true; From patchwork Sat Jan 21 02:07:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kechen Lu X-Patchwork-Id: 13110813 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 099A5C25B4E for ; Sat, 21 Jan 2023 02:08:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229811AbjAUCI4 (ORCPT ); Fri, 20 Jan 2023 21:08:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229764AbjAUCIo (ORCPT ); Fri, 20 Jan 2023 21:08:44 -0500 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2053.outbound.protection.outlook.com [40.107.220.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D761071349; Fri, 20 Jan 2023 18:08:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MtbrfULDmjgjhJHhfC855Wb7EKLE/SstKVr4mlfxUB2+EH8fZavYxxjhThsCKNsGeQMS8RPEsUmb6IXze2NYP2VSuBG8XRCDx4Gu9xlOcbWkGG+5JBsMpYEm7drJdmZ04rzofKqvVIeVkoiIvotz3Q5EZOf0nnGKb3pFedxDhBNX6b4EobapNf8m3xnQw4RpI/KJElVJ00WyG8keltt88NWp8QTNns8owJiPn4C3D0GyWyZyOUbJVxYJHw1lVd8/KLro1dRS1KorLaB8o/qHFXGN0/S2EwY5dGynTVJqy4y+CIHF5vFos3RW8Qz6nBg7u6o3fm8VZjENFIKTxDSbBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dInFWlQmlWges/kGbbRSqY3B4h+WSZxBeas3OVZFK6Q=; b=f5Pe0x17dt+wNZAJEVxQ6vORone3a0r0BXV8VdvBSVNeClDq4q25GbG73SNoMW80PvAYyfYZ16aAVUryyCgksvr5Hf0xGlp8sTcdem29xYGyd7j/Y7ZAMvBs3FERgTmiIlEp/yYr/M0E/j3b0v1hnrNXI3AswxFIcKMWVxx4j5sgi+26O/7OYpy0nGOnOpyIkArLQJT/lx18/YC/bbCCBYacpBpncfqaAwcwFJ5AYZ2wC3NVgezod/fTvQwu90DPY7/N8z1tAJT9t8LeDKhrbEyMDRYxwPGuoOSl1AwOV6PIyd7A3zMHlK09i2MeHmFCk5aEmmAWxCbp/FurYNI8xw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dInFWlQmlWges/kGbbRSqY3B4h+WSZxBeas3OVZFK6Q=; b=Hhj0WJzIWilwnBXAGZMrfRnue38DmdFVC++0ilImDmFIMDIZbPFSkqQSQQ6CkPbzXTpqqVnU+T5D2459RBIY+Go9hZZJSUEut+wX5qCjlpwyexlWO/IKm6lE8Nu5u7Xgu2UnhaEpgGNnbfxDaugHWFpeVR6AxjY72VjG2DJOYhztDXvS7aAR7trruJ5RdDlTeYgF/6UU12gKEOnk+KpDW9mopqIKmbVz0zzAj252MPbFwYOhgsxNkQwqr4hnbP7L2yqNjeT73Malq2hfuA5MufE55QtW/QUFw8154LNqzeRCzqTKw+U6DSCtpNjrVk100OGQodpVXChQrmZ6Hg7lnA== Received: from BN9P222CA0027.NAMP222.PROD.OUTLOOK.COM (2603:10b6:408:10c::32) by SN7PR12MB6932.namprd12.prod.outlook.com (2603:10b6:806:260::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.24; Sat, 21 Jan 2023 02:08:27 +0000 Received: from BN8NAM11FT069.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10c:cafe::50) by BN9P222CA0027.outlook.office365.com (2603:10b6:408:10c::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27 via Frontend Transport; Sat, 21 Jan 2023 02:08:27 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT069.mail.protection.outlook.com (10.13.176.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6023.16 via Frontend Transport; Sat, 21 Jan 2023 02:08:27 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:17 -0800 Received: from dvt1-1.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:17 -0800 From: Kechen Lu To: , , CC: , , , , , Subject: [RFC PATCH v6 4/6] KVM: x86: Let userspace re-enable previously disabled exits Date: Sat, 21 Jan 2023 02:07:36 +0000 Message-ID: <20230121020738.2973-5-kechenl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230121020738.2973-1-kechenl@nvidia.com> References: <20230121020738.2973-1-kechenl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT069:EE_|SN7PR12MB6932:EE_ X-MS-Office365-Filtering-Correlation-Id: da8e5f79-fe46-4ab3-738f-08dafb5462a7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JrbRwLE34ijLTJ257miHRyX+C4GqtQ1LTiCmr7cCYrZvCutmxas74ekU4T4DOEAFcWWnc5DoNXJ8nOHOijyFFOlGE6aHwHgFt7OQ6vVJcQrlwr/KdyAeFcXVkI0ETsZ9u0E5fKKH1Otc8oEnub7qcaj2FX8/iotWpLR3SbPEZypalfNIZ6v2Ykf+Ttf1Eez4oRv0KPC4kaAqLXH3entc0bct4/rekK0G/9vbnc6rXKlvuSjsX/VtDyOVoPYLxPS+b656Qe0/fjNCvfij1MMTd5dN6zkrb8MhAREo4syUvcCM7qAnw/PfmoizpbyPif7sNTk5f66PwI8ncvclrFoYMgbD7hujXHCuPvujC6M2tN8SRokTZhn0ikuCButpnV54eTnSWHhRx5e5eNq//N0g8ssZMfeliHGO21WwFMeW+ypusTAElfFog7YNl/yToey8i8zEKkE+9//LLes9N6VWAT7ZjtczOrBH0TgJp5ol+wGDRSFtba6EFnf6DEoAmrc+p0US3sgaUjHoePa6zyDX2vB7x0uLK7zQXHBwHOQjcN/vzN2pbRKrpQqqzv6jTzTnKyp5jrgdp6BKsK+Az763fSTbEUwPHaI4+lyOJWi5QCCMG3YFBpPl6cet45r7hSZ3hPid0ckajXdW4AHJJIiU+GH9gAHz86v8B4SGsLHy05W333hRHRvnejlW2HBL/j3X5TjonrgweOKoJBf3odNR+g== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199015)(36840700001)(40470700004)(46966006)(41300700001)(7636003)(8676002)(70206006)(356005)(86362001)(70586007)(5660300002)(82740400003)(36860700001)(8936002)(82310400005)(4326008)(40460700003)(1076003)(186003)(54906003)(2616005)(336012)(110136005)(7696005)(316002)(83380400001)(2906002)(26005)(16526019)(478600001)(36756003)(6666004)(47076005)(40480700001)(426003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2023 02:08:27.4968 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da8e5f79-fe46-4ab3-738f-08dafb5462a7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT069.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6932 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Sean Christopherson Add an OVERRIDE flag to KVM_CAP_X86_DISABLE_EXITS allow userspace to re-enable exits and/or override previous settings. There's no real use case for the per-VM ioctl, but a future per-vCPU variant wants to let userspace toggle interception while the vCPU is running; add the OVERRIDE functionality now to provide consistent between the per-VM and per-vCPU variants. Signed-off-by: Sean Christopherson --- Documentation/virt/kvm/api.rst | 5 +++++ arch/x86/kvm/x86.c | 32 ++++++++++++++++++++++++-------- include/uapi/linux/kvm.h | 4 +++- 3 files changed, 32 insertions(+), 9 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index fb0fcc566d5a..3850202942d0 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -7095,6 +7095,7 @@ Valid bits in args[0] are:: #define KVM_X86_DISABLE_EXITS_HLT (1 << 1) #define KVM_X86_DISABLE_EXITS_PAUSE (1 << 2) #define KVM_X86_DISABLE_EXITS_CSTATE (1 << 3) + #define KVM_X86_DISABLE_EXITS_OVERRIDE (1ull << 63) Enabling this capability on a VM provides userspace with a way to no longer intercept some instructions for improved latency in some @@ -7103,6 +7104,10 @@ physical CPUs. More bits can be added in the future; userspace can just pass the KVM_CHECK_EXTENSION result to KVM_ENABLE_CAP to disable all such vmexits. +By default, this capability only disables exits. To re-enable an exit, or to +override previous settings, userspace can set KVM_X86_DISABLE_EXITS_OVERRIDE, +in which case KVM will enable/disable according to the mask (a '1' == disable). + Do not enable KVM_FEATURE_PV_UNHALT if you disable HLT exits. 7.14 KVM_CAP_S390_HPAGE_1M diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 60caa3fd40e5..3ea5f12536a0 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5484,6 +5484,28 @@ static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, return r; } + +#define kvm_ioctl_disable_exits(a, mask) \ +({ \ + if (!kvm_can_mwait_in_guest()) \ + (mask) &= KVM_X86_DISABLE_EXITS_MWAIT; \ + if ((mask) & KVM_X86_DISABLE_EXITS_OVERRIDE) { \ + (a).mwait_in_guest = (mask) & KVM_X86_DISABLE_EXITS_MWAIT; \ + (a).hlt_in_guest = (mask) & KVM_X86_DISABLE_EXITS_HLT; \ + (a).pause_in_guest = (mask) & KVM_X86_DISABLE_EXITS_PAUSE; \ + (a).cstate_in_guest = (mask) & KVM_X86_DISABLE_EXITS_CSTATE; \ + } else { \ + if ((mask) & KVM_X86_DISABLE_EXITS_MWAIT) \ + (a).mwait_in_guest = true; \ + if ((mask) & KVM_X86_DISABLE_EXITS_HLT) \ + (a).hlt_in_guest = true; \ + if ((mask) & KVM_X86_DISABLE_EXITS_PAUSE) \ + (a).pause_in_guest = true; \ + if ((mask) & KVM_X86_DISABLE_EXITS_CSTATE) \ + (a).cstate_in_guest = true; \ + } \ +}) + static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, struct kvm_enable_cap *cap) { @@ -6238,14 +6260,8 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, if (kvm->created_vcpus) goto disable_exits_unlock; - if (cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) - kvm->arch.mwait_in_guest = true; - if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) - kvm->arch.hlt_in_guest = true; - if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) - kvm->arch.pause_in_guest = true; - if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) - kvm->arch.cstate_in_guest = true; + kvm_ioctl_disable_exits(kvm->arch, cap->args[0]); + r = 0; disable_exits_unlock: mutex_unlock(&kvm->lock); diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 55155e262646..876dcccbfff2 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -823,10 +823,12 @@ struct kvm_ioeventfd { #define KVM_X86_DISABLE_EXITS_HLT (1 << 1) #define KVM_X86_DISABLE_EXITS_PAUSE (1 << 2) #define KVM_X86_DISABLE_EXITS_CSTATE (1 << 3) +#define KVM_X86_DISABLE_EXITS_OVERRIDE (1ull << 63) #define KVM_X86_DISABLE_VALID_EXITS (KVM_X86_DISABLE_EXITS_MWAIT | \ KVM_X86_DISABLE_EXITS_HLT | \ KVM_X86_DISABLE_EXITS_PAUSE | \ - KVM_X86_DISABLE_EXITS_CSTATE) + KVM_X86_DISABLE_EXITS_CSTATE | \ + KVM_X86_DISABLE_EXITS_OVERRIDE) /* for KVM_ENABLE_CAP */ struct kvm_enable_cap { From patchwork Sat Jan 21 02:07:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kechen Lu X-Patchwork-Id: 13110812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2092CC05027 for ; Sat, 21 Jan 2023 02:08:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229781AbjAUCIv (ORCPT ); Fri, 20 Jan 2023 21:08:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229763AbjAUCIo (ORCPT ); Fri, 20 Jan 2023 21:08:44 -0500 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2041.outbound.protection.outlook.com [40.107.92.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A92A707C6; Fri, 20 Jan 2023 18:08:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iIG6km1wkmAXOCUKNiqgy1RVIglG5MrMWOqjela9kn5DUs62G/9l5QEPiwjQbBAqfEsvHeOeXV3cH9pwKDCA2DPCiyx+qbU9wvZX2VHc+LIa6Z8bftYCDYipTBHVIjpUJisLhTwResjrsFCTMKXd0EBUdFpTtf3us61f7Nkf1SvoyC8ZBQQSFZsFpjOSzQzZfWYiE/cEMuJWorhryh/QKQ4ixMhaDj5eyvMnRmeXGiBUzefBAljl3VJPtRN9Ni0tq7q16s4H/vMvj9FNPghVOo9BUJU7hf09xTpa5k+QfB54/1XWUlpyvs08soBu++yGdSrzp7c6h9DMIh599QIYiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pCVwnfon+D+exnG4W9ehny4BDM7lJpQ2S3wz9rg4rFw=; b=D7MWpfXBagCvNghDOfuSxPU+B65puZDHfVxkChNtBaIRVR/KsRcLHgejD/kXU2cS042hzWzxg4xk70o89jxsPrAiHizY+fuv8kM7z9tCvWd88kU9Ki9zRp2t8pBwW4BUzOwJyvUK2UHdZfoLNXstBPFQ6WyWigvd8l+5XLUHVKPM8x9xb5bnCtlDKkRo9TeJk0P3E0AWg65EyaXxXmRWricJwfjFr60wITf51izyFUbrbfXusEdIDd1M6/CjYOzkKnocO9v0ow55mNwz9FjtmIJ4+1Lq22nVixFyBCKvosSQddn0U2Xwf/yCxNzj8PvxqG6IULy1pC8b9gkuZi3Y/g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pCVwnfon+D+exnG4W9ehny4BDM7lJpQ2S3wz9rg4rFw=; b=jE/Nd76SvfBF8D0m2QCABukHBU9RDnduBmkdAb1I2FKJSboY0MjET6Em5dmxUOwmG7yawoWJZIpeDn0lmWFHcsU28qlTy/Vbl9nbcWbYdIzq3rOtUVXydnXilKh2uF59V/kydhqXncZ7GZCMZZNEqaOvsIE8CEofXVMUKC5c/n/DxAS0uZm80snczdNLv9pcP3Xu6KcIGpip319DgPm+y7S0Az937do6ntt3pp3ZAKtMk7Gq+x2pdKYsnF5szTwpZmZzUAyh2ZdcCpzrytCnWkJAjn9GCg2xkfEayUvW8DrDt/+eaRMFEtV0C+HHV4QbJ9lEk5sJhEX1SRsHfuFuAQ== Received: from BN9P222CA0027.NAMP222.PROD.OUTLOOK.COM (2603:10b6:408:10c::32) by CH0PR12MB5121.namprd12.prod.outlook.com (2603:10b6:610:bc::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27; Sat, 21 Jan 2023 02:08:29 +0000 Received: from BN8NAM11FT069.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10c:cafe::50) by BN9P222CA0027.outlook.office365.com (2603:10b6:408:10c::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27 via Frontend Transport; Sat, 21 Jan 2023 02:08:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT069.mail.protection.outlook.com (10.13.176.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6023.16 via Frontend Transport; Sat, 21 Jan 2023 02:08:29 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:19 -0800 Received: from dvt1-1.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:18 -0800 From: Kechen Lu To: , , CC: , , , , , Subject: [RFC PATCH v6 5/6] KVM: x86: add vCPU scoped toggling for disabled exits Date: Sat, 21 Jan 2023 02:07:37 +0000 Message-ID: <20230121020738.2973-6-kechenl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230121020738.2973-1-kechenl@nvidia.com> References: <20230121020738.2973-1-kechenl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT069:EE_|CH0PR12MB5121:EE_ X-MS-Office365-Filtering-Correlation-Id: 63b30690-28d3-4d06-ed8f-08dafb5463a8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xIgkTo1cI7OE4eoLmDiVKPZzKhY04TwXYZXamip44HTbJyRIWK5SpSifeU3dRftMXETa2bDwOOVDM0Habv3yFt+Lp3nf54zSHtuFGj055Mq52nR5yQ8UNuD+H8FbxPgWa30GgcW8DA6hp8aOdoCFkDCZ8fYShOcnsFk4PMfwr/Uc369bnvO+R8uIJbTOLXMtPCcyNTDcV42afV3K0Io29UzV2WWEH6TpnCAj2bBSNUWB5KRpL1CumtjiqG1z47sgVq25Fd9nkQuRwSx5I7n1KPVaN1xSzYhG7d+QT+4NklcGdr6fr1hcIr9XXIG02tiPyAZxV3zy7rxP4Z5jMkkd/YXia7Wz4mkuITjN6bbPW9PtmSDVn2e7ZZsKObshK/wNK2/1T53HKl2jvaRmzVbZPawVnk3tfjqElfaFGPDw+wrACrxxtdaNVFgpjoVuL0ms6PFAFSQ6bp1Nw+evIEQPgTu0ilHb7KKNJ6Plh6xpqaQ55XyrU5uBnQt3nltPBWLNbKWGhgERNGFAVGrTFkVr3EEtV2+iYS9fyMHjkkP3zdMl6nh3Qtk1cwXiHOgm9JsmfxjA/ExoSkcGVxOIlXHBeTZEjiVLS88LeUxlSX6jEhfZeQuVOYosC2N2e66BYvTM4IxBHk7cg6Ps6pKcngI+IIyQvBOYDnaSR+IdggqJp713rd0TRRnawV8+8+ueQMqd3cIHrlI1cNvVLeJSin3omw== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(39860400002)(346002)(396003)(451199015)(46966006)(40470700004)(36840700001)(5660300002)(8936002)(4326008)(82310400005)(8676002)(70586007)(70206006)(36860700001)(36756003)(6666004)(186003)(16526019)(2906002)(54906003)(110136005)(26005)(7696005)(316002)(478600001)(2616005)(83380400001)(41300700001)(356005)(40460700003)(82740400003)(40480700001)(1076003)(86362001)(7636003)(47076005)(336012)(426003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2023 02:08:29.2155 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63b30690-28d3-4d06-ed8f-08dafb5463a8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT069.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5121 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce support of vCPU-scoped ioctl with KVM_CAP_X86_DISABLE_EXITS cap for disabling exits to enable finer-grained VM exits disabling on per vCPU scales instead of whole guest. This patch enables the vCPU-scoped exits control toggling, but keeps the VM-scoped exits control behaviors restriction as before. In use cases like Windows guest running heavy CPU-bound workloads, disabling HLT VM-exits could mitigate host sched ctx switch overhead. Simply HLT disabling on all vCPUs could bring performance benefits, but if no pCPUs reserved for host threads, could happened to the forced preemption as host does not know the time to do the schedule for other host threads want to run. With this patch, we could only disable part of vCPUs HLT exits for one guest, this still keeps performance benefits, and also shows resiliency to host stressing workload running at the same time. In the host stressing workload experiment with Windows guest heavy CPU-bound workloads, it shows good resiliency and having the ~3% performance improvement. E.g. Passmark running in a Windows guest with this patch disabling HLT exits on only half of vCPUs still showing 2.4% higher main score v/s baseline. Suggested-by: Sean Christopherson Suggested-by: Chao Gao Signed-off-by: Kechen Lu --- Documentation/virt/kvm/api.rst | 2 +- arch/x86/include/asm/kvm-x86-ops.h | 1 + arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/kvm/svm/svm.c | 30 ++++++++++++++++++++++++ arch/x86/kvm/vmx/vmx.c | 37 ++++++++++++++++++++++++++++++ arch/x86/kvm/x86.c | 7 ++++++ 6 files changed, 78 insertions(+), 1 deletion(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 3850202942d0..698f476d36dd 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -7102,7 +7102,7 @@ longer intercept some instructions for improved latency in some workloads, and is suggested when vCPUs are associated to dedicated physical CPUs. More bits can be added in the future; userspace can just pass the KVM_CHECK_EXTENSION result to KVM_ENABLE_CAP to disable -all such vmexits. +all such vmexits. VM scoped and vCPU scoped capability are both supported. By default, this capability only disables exits. To re-enable an exit, or to override previous settings, userspace can set KVM_X86_DISABLE_EXITS_OVERRIDE, diff --git a/arch/x86/include/asm/kvm-x86-ops.h b/arch/x86/include/asm/kvm-x86-ops.h index abccd51dcfca..534322c21168 100644 --- a/arch/x86/include/asm/kvm-x86-ops.h +++ b/arch/x86/include/asm/kvm-x86-ops.h @@ -131,6 +131,7 @@ KVM_X86_OP(msr_filter_changed) KVM_X86_OP(complete_emulated_msr) KVM_X86_OP(vcpu_deliver_sipi_vector) KVM_X86_OP_OPTIONAL_RET0(vcpu_get_apicv_inhibit_reasons); +KVM_X86_OP(update_disabled_exits) #undef KVM_X86_OP #undef KVM_X86_OP_OPTIONAL diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 41b998234a04..e21e5d452b5d 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1711,6 +1711,8 @@ struct kvm_x86_ops { * Returns vCPU specific APICv inhibit reasons */ unsigned long (*vcpu_get_apicv_inhibit_reasons)(struct kvm_vcpu *vcpu); + + void (*update_disabled_exits)(struct kvm_vcpu *vcpu); }; struct kvm_x86_nested_ops { diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index dc7176605e01..81c387dfa46c 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4680,6 +4680,33 @@ static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) sev_vcpu_deliver_sipi_vector(vcpu, vector); } +static void svm_update_disabled_exits(struct kvm_vcpu *vcpu) +{ + struct vcpu_svm *svm = to_svm(vcpu); + struct vmcb_control_area *control = &svm->vmcb->control; + + if (kvm_hlt_in_guest(vcpu)) + svm_clr_intercept(svm, INTERCEPT_HLT); + else + svm_set_intercept(svm, INTERCEPT_HLT); + + if (kvm_mwait_in_guest(vcpu)) { + svm_clr_intercept(svm, INTERCEPT_MONITOR); + svm_clr_intercept(svm, INTERCEPT_MWAIT); + } else { + svm_set_intercept(svm, INTERCEPT_MONITOR); + svm_set_intercept(svm, INTERCEPT_MWAIT); + } + + if (kvm_pause_in_guest(vcpu)) { + svm_clr_intercept(svm, INTERCEPT_PAUSE); + } else { + control->pause_filter_count = pause_filter_count; + if (pause_filter_thresh) + control->pause_filter_thresh = pause_filter_thresh; + } +} + static void svm_vm_destroy(struct kvm *kvm) { avic_vm_destroy(kvm); @@ -4825,7 +4852,10 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { .complete_emulated_msr = svm_complete_emulated_msr, .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector, + .vcpu_get_apicv_inhibit_reasons = avic_vcpu_get_apicv_inhibit_reasons, + + .update_disabled_exits = svm_update_disabled_exits, }; /* diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 019a20029878..f5137afdd424 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -8070,6 +8070,41 @@ static void vmx_vm_destroy(struct kvm *kvm) free_pages((unsigned long)kvm_vmx->pid_table, vmx_get_pid_table_order(kvm)); } +static void vmx_update_disabled_exits(struct kvm_vcpu *vcpu) +{ + struct vcpu_vmx *vmx = to_vmx(vcpu); + + if (kvm_hlt_in_guest(vcpu)) + exec_controls_clearbit(vmx, CPU_BASED_HLT_EXITING); + else + exec_controls_setbit(vmx, CPU_BASED_HLT_EXITING); + + if (kvm_mwait_in_guest(vcpu)) + exec_controls_clearbit(vmx, CPU_BASED_MWAIT_EXITING | + CPU_BASED_MONITOR_EXITING); + else + exec_controls_setbit(vmx, CPU_BASED_MWAIT_EXITING | + CPU_BASED_MONITOR_EXITING); + + if (!kvm_pause_in_guest(vcpu)) { + vmcs_write32(PLE_GAP, ple_gap); + vmx->ple_window = ple_window; + vmx->ple_window_dirty = true; + } + + if (kvm_cstate_in_guest(vcpu)) { + vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R); + vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); + vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); + vmx_disable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); + } else { + vmx_enable_intercept_for_msr(vcpu, MSR_CORE_C1_RES, MSR_TYPE_R); + vmx_enable_intercept_for_msr(vcpu, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); + vmx_enable_intercept_for_msr(vcpu, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); + vmx_enable_intercept_for_msr(vcpu, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); + } +} + static struct kvm_x86_ops vmx_x86_ops __initdata = { .name = "kvm_intel", @@ -8207,6 +8242,8 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = { .complete_emulated_msr = kvm_complete_insn_gp, .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector, + + .update_disabled_exits = vmx_update_disabled_exits, }; static unsigned int vmx_handle_intel_pt_intr(void) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 3ea5f12536a0..8c15292c6886 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5552,6 +5552,13 @@ static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, if (vcpu->arch.pv_cpuid.enforce) kvm_update_pv_runtime(vcpu); + return 0; + case KVM_CAP_X86_DISABLE_EXITS: + if (cap->args[0] & ~kvm_get_allowed_disable_exits()) + return -EINVAL; + + kvm_ioctl_disable_exits(vcpu->arch, cap->args[0]); + static_call(kvm_x86_update_disabled_exits)(vcpu); return 0; default: return -EINVAL; From patchwork Sat Jan 21 02:07:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kechen Lu X-Patchwork-Id: 13110811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A923EC25B4E for ; Sat, 21 Jan 2023 02:08:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229744AbjAUCIt (ORCPT ); Fri, 20 Jan 2023 21:08:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229543AbjAUCIo (ORCPT ); Fri, 20 Jan 2023 21:08:44 -0500 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2082.outbound.protection.outlook.com [40.107.220.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C11770C6B; Fri, 20 Jan 2023 18:08:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CVCUc9VS94BuNLynz4eKSrwJ1LfOGSX3/GUCz6aB9sY/1XVxMt2JKZLWvDt9EwBCNteW93nKLZQ9/xHYG3L32XTQQeFD/zn4YqR7AolXzn54UnerD+S0FzvVIe8iMt+1M+8hgW1GpPoSEJAwlNeZyU7WlnH+eladKUspZwl0xd5M78mzWmZXltnEeQMNdfIk/lmxQo7wzLJHZfdIFiXGMMmVZ7QL8/mWyq3cYRtGragODhi7JDkuIgsCw9Ovz0odjyDnDgHAGiIZQ3Fl6QJfzrdTZ26qcJcYSIuJmgP8BiKfdRBinuGIgtvPxlmKprgPfd3tnijRZfxJ+iHLVIXt8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SBELM1s2FXDCN1vghPgHk9ygS4+iUOF75gmUWGNa8YI=; b=b6DWgK345/zpvO4qImQQYDq5vWYWRZf4GRpYFJjbQUMaGFK+OYMDHvt7vikPb6UHzKXX6sDbRxW7QOE4Kf0FTyTScJFkopB/5JXs1YCNBA7s6d2LyFxow0keReFzCUfDnMhpk8hwXUjtGFt4z1+bdEFfJIZt0q8OreLKwbZqc4XWXBHxNyWKaGli2g9RrgFFx8tbkI0scBx2YxEK3O8jKMuWyz2cHj+Yyn7cNfiD/wtfIBTTlpMyUQGBy0Lly43q+e09Sb+JFwwfg+SNl1uJydbb3Yy/zE2Y9Oswkrvmrs0TsT+vfVlyLUG2GGt3vjifYCpdexIBgJ+b/okk+PFNSg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SBELM1s2FXDCN1vghPgHk9ygS4+iUOF75gmUWGNa8YI=; b=tsMV7ftRlbZfsykJfy/N6ytFVYFsuF1Xkcz071Mhq4cNyXlhNMfstqoHr8ML8PvOJCl7GF7GdY6V+7sbZ8Y/aSb/UDSlJnsT1K9f1rXUGf03Orv0oSan8tzSNbhAWcNHgjEyW296SKxPkzQRuiNXhaIJuz1NRGV/an4/fcCst3Om4/Z+ABdoPQtcq7RMqUOvG7fG7eX8t5KNWgOPzo+wgK3XuDIzZUuMK+nrho2kqb8EPxwMOVBFPhQrPyKEWglqwXNYmffZ6LLmQc4KeAy8Ek/bvvNcph2G2/h/cwU/bOFz4X7ZK59PSCb07Z6H3+kAj6wnZx6DZIj7iJKEm7wT3A== Received: from DM6PR03CA0074.namprd03.prod.outlook.com (2603:10b6:5:333::7) by SA0PR12MB4430.namprd12.prod.outlook.com (2603:10b6:806:70::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27; Sat, 21 Jan 2023 02:08:31 +0000 Received: from DM6NAM11FT109.eop-nam11.prod.protection.outlook.com (2603:10b6:5:333:cafe::60) by DM6PR03CA0074.outlook.office365.com (2603:10b6:5:333::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27 via Frontend Transport; Sat, 21 Jan 2023 02:08:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT109.mail.protection.outlook.com (10.13.173.178) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6023.16 via Frontend Transport; Sat, 21 Jan 2023 02:08:31 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:20 -0800 Received: from dvt1-1.nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 20 Jan 2023 18:08:20 -0800 From: Kechen Lu To: , , CC: , , , , , Subject: [RFC PATCH v6 6/6] KVM: selftests: Add tests for VM and vCPU cap KVM_CAP_X86_DISABLE_EXITS Date: Sat, 21 Jan 2023 02:07:38 +0000 Message-ID: <20230121020738.2973-7-kechenl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230121020738.2973-1-kechenl@nvidia.com> References: <20230121020738.2973-1-kechenl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT109:EE_|SA0PR12MB4430:EE_ X-MS-Office365-Filtering-Correlation-Id: 7330a4eb-b44c-490d-f0c3-08dafb5464ef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ar0xGZ+HyYYWQyySeX1mdROw8RjTLsC4BAJhanCoAmhJocsgpaovU/bfdie9FSuCDYkw4mwOKO5Hte23eKaL1OXgenUHT8fT6CxAZSFUL7I3g/ZUBPn/KVTQ+4w8+NVCxzop0VOYK8OLVBQJRAPqpqh1V4omLIN46G5oS0d3USqVBtMTtBu3ouD++qTSNIRcS4LCtpF+dJE4ivZTDOOOI2tm6SIsaLqBsWsPRQRRbasFCzfeXSoE+AFIE9A/DLhnErwbSGWr/4FHCLs9V91wzUpra1dvqUjOeo/ZjWbnSdwnPvuicRx01Y2NOiHsjT/wEDefX5wZpDJGzRy3od4nRJUgDPAozSmPgQruYP+FVBc9XbYbuFB2rOtPme31gc5WU487YbbAMSyiofYRwxC3dGDj3Hx2NpLpZQ8Xca78p45ixhFIElfRenrEW4V6Z8VkjcD2i/P7qKbi7EQT7b41a2bhVwGCXbHuuwmzHpOvYJIIvROl9eYQYKGBxe/IxVSvA9pKFawD/K9nSP3clIxLGsmbeCyNGN1H1t+evUzMC1FwIcOhcAQYRqOoffO3mLPTBr5WDOsv2RBtAQsTQ6ZOWH/Yo2YlUVTNzde7jw0/bPN/YcZgyVB9dMk0tRznWrE6/ZSq0zaY9cWQa21Ru+4Uj2uRoLNLZqKwbG22Vihe2QYvAJjCiPDfhMIG0TQD020svukdJ+MVry3YSwz1TJsAqg== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(376002)(346002)(396003)(451199015)(46966006)(40470700004)(36840700001)(5660300002)(30864003)(8936002)(4326008)(8676002)(82310400005)(70586007)(70206006)(36860700001)(6666004)(186003)(26005)(54906003)(2906002)(16526019)(316002)(7696005)(478600001)(36756003)(2616005)(110136005)(83380400001)(41300700001)(356005)(40460700003)(82740400003)(40480700001)(1076003)(86362001)(7636003)(47076005)(336012)(426003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2023 02:08:31.4211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7330a4eb-b44c-490d-f0c3-08dafb5464ef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT109.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4430 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add selftests for KVM cap KVM_CAP_X86_DISABLE_EXITS overriding flags in VM and vCPU scope both working as expected. Suggested-by: Chao Gao Suggested-by: Shaoqin Huang Suggested-by: Zhi Wang Signed-off-by: Kechen Lu --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/x86_64/disable_exits_test.c | 363 ++++++++++++++++++ 2 files changed, 364 insertions(+) create mode 100644 tools/testing/selftests/kvm/x86_64/disable_exits_test.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index 1750f91dd936..eeeba35e2536 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -114,6 +114,7 @@ TEST_GEN_PROGS_x86_64 += x86_64/sev_migrate_tests TEST_GEN_PROGS_x86_64 += x86_64/amx_test TEST_GEN_PROGS_x86_64 += x86_64/max_vcpuid_cap_test TEST_GEN_PROGS_x86_64 += x86_64/triple_fault_event_test +TEST_GEN_PROGS_x86_64 += x86_64/disable_exits_test TEST_GEN_PROGS_x86_64 += access_tracking_perf_test TEST_GEN_PROGS_x86_64 += demand_paging_test TEST_GEN_PROGS_x86_64 += dirty_log_test diff --git a/tools/testing/selftests/kvm/x86_64/disable_exits_test.c b/tools/testing/selftests/kvm/x86_64/disable_exits_test.c new file mode 100644 index 000000000000..74a2152b35dd --- /dev/null +++ b/tools/testing/selftests/kvm/x86_64/disable_exits_test.c @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Test per-VM and per-vCPU disable exits cap + * 1) Per-VM scope + * 2) Per-vCPU scope + * + */ + +#define _GNU_SOURCE /* for program_invocation_short_name */ +#include +#include +#include +#include +#include + +#include "test_util.h" +#include "kvm_util.h" +#include "svm_util.h" +#include "vmx.h" +#include "processor.h" +#include "asm/kvm.h" +#include "linux/kvm.h" + +/* Arbitrary chosen IPI vector value from sender to halter vCPU */ +#define IPI_VECTOR 0xa5 +/* Number of HLTs halter vCPU thread executes */ +#define LOOP_DURATION 3 + +struct guest_stats { + uint32_t halter_apic_id; + volatile uint64_t hlt_count; + volatile uint64_t wake_count; +}; + +static u64 read_vcpu_stats_halt_exits(struct kvm_vcpu *vcpu) +{ + int i; + struct kvm_stats_header header; + u64 *stats_data; + u64 ret = 0; + struct kvm_stats_desc *stats_desc; + struct kvm_stats_desc *pdesc; + int stats_fd = vcpu_get_stats_fd(vcpu); + + read_stats_header(stats_fd, &header); + if (header.num_desc == 0) { + fprintf(stderr, + "Cannot read halt exits since no KVM stats defined\n"); + return ret; + } + + stats_desc = read_stats_descriptors(stats_fd, &header); + for (i = 0; i < header.num_desc; ++i) { + pdesc = get_stats_descriptor(stats_desc, i, &header); + if (!strncmp(pdesc->name, "halt_exits", 10)) { + stats_data = malloc(pdesc->size * sizeof(*stats_data)); + read_stat_data(stats_fd, &header, pdesc, stats_data, + pdesc->size); + ret = *stats_data; + free(stats_data); + break; + } + } + free(stats_desc); + return ret; +} + +/* HLT multiple times in one vCPU */ +static void halter_guest_code(struct guest_stats *data) +{ + xapic_enable(); + data->halter_apic_id = GET_APIC_ID_FIELD(xapic_read_reg(APIC_ID)); + + for (;;) { + data->hlt_count++; + asm volatile("sti; hlt; cli"); + data->wake_count++; + } +} + +/* Runs on halter vCPU when IPI arrives */ +static void guest_ipi_handler(struct ex_regs *regs) +{ + xapic_write_reg(APIC_EOI, 11); +} + +/* Sender vCPU waits for ~1sec to assume HLT executed */ +static void sender_wait_loop(struct guest_stats *data, uint64_t old_hlt_count, + uint64_t old_wake_count) +{ + uint64_t tsc_start = rdtsc(); + + while (rdtsc() - tsc_start < 4000000000) { + if ((data->wake_count != old_wake_count) && + (data->hlt_count != old_hlt_count)) + break; + } + GUEST_ASSERT((data->wake_count != old_wake_count) && + (data->hlt_count != old_hlt_count)); +} + +/* Sender vCPU loops sending IPI to halter vCPU every ~1sec */ +static void sender_guest_code(struct guest_stats *data) +{ + uint32_t icr_val; + uint32_t icr2_val; + uint64_t old_hlt_count = 0; + uint64_t old_wake_count = 0; + + xapic_enable(); + /* Init interrupt command register for sending IPIs */ + icr_val = (APIC_DEST_PHYSICAL | APIC_DM_FIXED | IPI_VECTOR); + icr2_val = SET_APIC_DEST_FIELD(data->halter_apic_id); + + for (;;) { + /* + * Send IPI to halted vCPU + * First IPI sends here as already waited before sender vCPU + * thread creation + */ + xapic_write_reg(APIC_ICR2, icr2_val); + xapic_write_reg(APIC_ICR, icr_val); + sender_wait_loop(data, old_hlt_count, old_wake_count); + old_wake_count = data->wake_count; + old_hlt_count = data->hlt_count; + } +} + +static void *vcpu_thread(void *arg) +{ + struct kvm_vcpu *vcpu = (struct kvm_vcpu *)arg; + int old; + int r; + + r = pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS, &old); + TEST_ASSERT(r == 0, + "pthread_setcanceltype failed on vcpu_id=%u with errno=%d", + vcpu->id, r); + fprintf(stderr, "vCPU thread running vCPU %u\n", vcpu->id); + vcpu_run(vcpu); + return NULL; +} + +static void cancel_join_vcpu_thread(pthread_t thread, struct kvm_vcpu *vcpu) +{ + void *retval; + int r; + + r = pthread_cancel(thread); + TEST_ASSERT(r == 0, + "pthread_cancel on vcpu_id=%d failed with errno=%d", + vcpu->id, r); + + r = pthread_join(thread, &retval); + TEST_ASSERT(r == 0, + "pthread_join on vcpu_id=%d failed with errno=%d", + vcpu->id, r); +} + +static void vm_run_with_threads(struct kvm_vcpu *halter_vcpu, + struct kvm_vcpu *sender_vcpu) +{ + int r; + pthread_t threads[2]; + + /* Start halter vCPU thread and wait for it to execute first HLT. */ + r = pthread_create(&threads[0], NULL, vcpu_thread, halter_vcpu); + TEST_ASSERT(r == 0, + "pthread_create halter failed errno=%d", errno); + fprintf(stderr, "Halter vCPU thread started\n"); + + sleep(1); + + /* + * After guest halter vCPU executed first HLT, start the sender + * vCPU thread to wakeup halter vCPU + */ + r = pthread_create(&threads[1], NULL, vcpu_thread, sender_vcpu); + TEST_ASSERT(r == 0, "pthread_create sender failed errno=%d", errno); + + sleep(LOOP_DURATION); + + cancel_join_vcpu_thread(threads[0], halter_vcpu); + cancel_join_vcpu_thread(threads[1], sender_vcpu); +} + +/* + * Test case 1: + * Normal VM running with one vCPU keeps executing HLTs, + * another vCPU sending IPIs to wake it up, should expect + * all HLTs exiting to host + * and Test case 2: + * VM scoped exits disabling, HLT instructions + * stay inside guest without exits + */ +static void test_vm_disable_exits_cap(bool cap_enabled) +{ + uint64_t kvm_halt_exits; + struct kvm_vm *vm; + struct kvm_vcpu *halter_vcpu; + struct kvm_vcpu *sender_vcpu; + struct guest_stats *data; + vm_vaddr_t guest_stats_page_vaddr; + + /* Create VM */ + vm = vm_create(2); + + /* + * Before adding any vCPUs, enable the KVM_X86_DISABLE_EXITS cap + * with flag KVM_X86_DISABLE_EXITS_HLT + */ + if (cap_enabled) + vm_enable_cap(vm, KVM_CAP_X86_DISABLE_EXITS, + KVM_X86_DISABLE_EXITS_HLT); + + /* Add vCPU with loops halting */ + halter_vcpu = vm_vcpu_add(vm, 0, halter_guest_code); + + vm_init_descriptor_tables(vm); + vcpu_init_descriptor_tables(halter_vcpu); + vm_install_exception_handler(vm, IPI_VECTOR, guest_ipi_handler); + virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA); + + /* Add vCPU with IPIs waking up halter vCPU */ + sender_vcpu = vm_vcpu_add(vm, 1, sender_guest_code); + + guest_stats_page_vaddr = vm_vaddr_alloc_page(vm); + data = addr_gva2hva(vm, guest_stats_page_vaddr); + memset(data, 0, sizeof(*data)); + + vcpu_args_set(halter_vcpu, 1, guest_stats_page_vaddr); + vcpu_args_set(sender_vcpu, 1, guest_stats_page_vaddr); + + vm_run_with_threads(halter_vcpu, sender_vcpu); + kvm_halt_exits = read_vcpu_stats_halt_exits(halter_vcpu); + if (cap_enabled) + TEST_ASSERT(kvm_halt_exits == 0, + "Halter vCPU had unexpected halt exits occurring after disabling VM-scoped halt exits cap\n"); + else + TEST_ASSERT(kvm_halt_exits == data->hlt_count, + "Halter vCPU had unmatched %lu halt exits - %lu HLTs executed, when not disabling VM halt exits\n", + kvm_halt_exits, data->hlt_count); + fprintf(stderr, "Halter vCPU had %lu halt exits\n", + kvm_halt_exits); + fprintf(stderr, "Guest records %lu HLTs executed, waked %lu times\n", + data->hlt_count, data->wake_count); + + kvm_vm_free(vm); +} + +/* + * Test case 3: + * VM overrides exits disable flags after vCPU created, + * which is not allowed + */ +static void test_vm_disable_exits_cap_with_vcpu_created(void) +{ + int r; + struct kvm_vm *vm; + struct kvm_enable_cap cap = { + .cap = KVM_CAP_X86_DISABLE_EXITS, + .args[0] = KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_OVERRIDE, + }; + + /* Create VM */ + vm = vm_create(1); + /* Add vCPU with loops halting */ + vm_vcpu_add(vm, 0, halter_guest_code); + + /* + * After creating vCPU, the current VM-scoped ABI should + * discard the cap enable of KVM_CAP_X86_DISABLE_EXITS + * and return non-zero. Since vm_enabled_cap() not able + * to assert the return value, so use the __vm_ioctl() + */ + r = __vm_ioctl(vm, KVM_ENABLE_CAP, &cap); + + TEST_ASSERT(r != 0, + "Setting VM-scoped KVM_CAP_X86_DISABLE_EXITS after vCPUs created is not allowed, but it succeeds here\n"); +} + +/* + * Test case 4: + * vCPU scoped halt exits disabling and enabling tests, + * verify overides are working after vCPU created + */ +static void test_vcpu_toggling_disable_exits_cap(void) +{ + uint64_t kvm_halt_exits; + uint64_t kvm_halt_exits_in_guest; + struct kvm_vm *vm; + struct kvm_vcpu *halter_vcpu; + struct kvm_vcpu *sender_vcpu; + struct guest_stats *data; + vm_vaddr_t guest_stats_page_vaddr; + + /* Create VM */ + vm = vm_create(2); + + /* Add vCPU with loops halting */ + halter_vcpu = vm_vcpu_add(vm, 0, halter_guest_code); + /* Set KVM_CAP_X86_DISABLE_EXITS_HLT for halter vCPU */ + vcpu_enable_cap(halter_vcpu, KVM_CAP_X86_DISABLE_EXITS, + KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_OVERRIDE); + + vm_init_descriptor_tables(vm); + vcpu_init_descriptor_tables(halter_vcpu); + vm_install_exception_handler(vm, IPI_VECTOR, guest_ipi_handler); + virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA); + + /* Add vCPU with IPIs waking up halter vCPU */ + sender_vcpu = vm_vcpu_add(vm, 1, sender_guest_code); + + guest_stats_page_vaddr = vm_vaddr_alloc_page(vm); + data = addr_gva2hva(vm, guest_stats_page_vaddr); + memset(data, 0, sizeof(*data)); + + vcpu_args_set(halter_vcpu, 1, guest_stats_page_vaddr); + vcpu_args_set(sender_vcpu, 1, guest_stats_page_vaddr); + + /* + * For the first phase of the running, halt exits + * are disabled, halter vCPU executes HLT instruction + * but never exits to host + */ + vm_run_with_threads(halter_vcpu, sender_vcpu); + kvm_halt_exits_in_guest = data->hlt_count; + fprintf(stderr, "Guest records %lu HLTs with halt exits disabled\n", + data->hlt_count); + /* + * Override and clean KVM_CAP_X86_DISABLE_EXITS flags + * for halter vCPU. Expect to see halt exits occurs then. + */ + vcpu_enable_cap(halter_vcpu, KVM_CAP_X86_DISABLE_EXITS, + KVM_X86_DISABLE_EXITS_OVERRIDE); + /* + * Second phase of the test, after guest halter vCPU + * reenabled halt exits, start the sender + * vCPU thread to wakeup halter vCPU + */ + vm_run_with_threads(halter_vcpu, sender_vcpu); + kvm_halt_exits = read_vcpu_stats_halt_exits(halter_vcpu); + TEST_ASSERT(kvm_halt_exits == data->hlt_count - kvm_halt_exits_in_guest, + "Halter vCPU had unexpected %lu (should be %lu) halt exits\n", + kvm_halt_exits, data->hlt_count - kvm_halt_exits_in_guest); + fprintf(stderr, "Halter vCPU had %lu halt exits\n", + kvm_halt_exits); + fprintf(stderr, "Guest records %lu HLTs executed, waked %lu times\n", + data->hlt_count, data->wake_count); + + kvm_vm_free(vm); +} + +int main(int argc, char *argv[]) +{ + fprintf(stderr, "VM-scoped tests start\n"); + test_vm_disable_exits_cap(false); + test_vm_disable_exits_cap(true); + test_vm_disable_exits_cap_with_vcpu_created(); + fprintf(stderr, "vCPU-scoped test starts\n"); + test_vcpu_toggling_disable_exits_cap(); + return 0; +}